AS91L1006BU July 2004 6-Port JTAG Gateway Description The AS91L1006BU is a one to 6-port JTAG gateway. It partitions a single JTAG chain into six separate chains. These separate chains can be optionally configured to operate as a single chain. The AS91L1006BU device is used to provide enhanced capabilities to the standard IEEE1149.1. It enables the IEEE1149.1 interface to be used in a true Multi-Drop environment without any additional signals. This Multi-Drop capability enables the standard IEEE1149.1 interface to be used not just for stand alone PCB (Printed Circuit Board) testing, but also for complete system testing including all PCBs within a system back plane environment. The AS91L1006BU provides the capability of partitioning the PCB, into multiple smaller IEEE1149.1 scan chains totally under software control. Partitioning the IEEE1149.1 chains on the PCB has several benefits which include easier fault diagnostics capabilities as a fault on one of the IEEE1149.1 Local Scan Ports (LSPs) does not render the PCB untestable, faster flash programming on the PCBs, and removal of IEEE1149.1 signal loading issues. All of the protocols required for addressing the AS91L1006BU device via the Multi-Drop capability and the protocols for configuring which of the six IEEE1149.1 LSPs on the AS91L1006BU are to be used, is handled via 3rd party ATPG tools from vendors like AssetIntertech and JTAG Technologies. In a Multi-Drop environment it is also possible to perform interconnect tests between multiple PCBs within a system thus extending the interconnect tests to the back plane itself. Key Features Device Multi-Drop addressable via the IEEE 1149.1 protocol Support for 6 local scan chains addressable via the IEEE 1149.1 interface Support for Pass-Through™ Support for the IEEE 1149.1 USERCODE instruction Support for Status instruction enabling nonintrusive monitoring of the system card Local Scan Port (LSP) enable signal provides the ability to use non IEEE 1149.1 compliant devices that require JTAG enable signal Provides the ability to initiate Self-Test on a remote PCB via a standard IEEE 1149.1 command Support for JTAG Technologies AutoWR™ feature Pinout and feature set compatible (complete second source) with the Firecron JTS06BU device Available in a 100-pin LQFP or a 100-pin FPBGA lead free package Device Block Diagram P a s s T h r o u g h E n a b le P r im a r y 1 1 4 9 . 1 J T A G In te rfa c e LSP1 S ta tu s D a ta LSP2 U s e rc o d e D a ta D e v ic e a d d re s s 1 1 4 9 . 1 T A P C o n t r o lle r and B o u n d a r y R e g is t e r S e le c t io n L o g ic D e v ic e S e le c t io n L o g ic P a s s T h ro u g h L o g ic & L o c a l S c a n P o rt C o n n e c t io n / C o n f ig lo g ic L o c a l S c a n P o rt P a r k /U n -p a rk S y n c L o g ic LSP3 LSP4 LSP5 LSP6 Figure 1 - AS91L1006BU Device Block Diagram Alliance Semiconductor 2575 Augustine Drive • Santa Clara, CA 95054 • T: 408-855-4900 • F: 408-855-4999 • www.alsc.com July 2004 AS91L1006BU AS91L1006BU Gateway Functional Description The basic structure of the AS91L1006BU device is shown in Figure-1. The core of the device is the 16-state IEEE1149.1 TAP controller state machine. All accesses to the internal registers of the AS91L1006BU device are controlled via this state machine during normal operation as per the IEEE1149.1 standard. The address selection logic enables the AS91L1006BU to operate in a MultiDrop environment within system backplane. The address selection logic compares the scanned address to the slot address value presented on the I/O of the AS91L1006BU device. The LSP park/unpark logic provides control through instructions scanned in under the IEEE1149.1 protocol, to select, which LSP will be placed into the active, scan chain. The passthrough and LSP connection logic selects the signal paths for the LSP IEEE1149.1 signals. The Selected Single Device Figure-2 shows the device selection state machine. The AS91L1006BU will perform an address compare on the slot address presented at its I/O and the value scanned in via the IEEE1149.1. If the value matches then the AS91L1006BU becomes selected and is ready for normal access via IEEE1149.1 commands. If the address does not match then the device will proceed to the unselected mode, where it will remain until the AS91L1006BU is issued a GOTOWAIT instruction or a reset occurs via TRST or the LSP_RESET pin. Device Unselected Parked-RTI Parked-TLR Wait for Selection Select Group of Devices device also supports a Pass-Through mode which enables the primary IEEE1149.1 signals to be routed to any of the LSPs. This signal routing is selectable via I/O pins on the AS91L1006BU device. Select All Devices Figure 2 - AS91L1006BU Selection Logic State machine ParkedPauseDR UnParked ParkedPauseIR Figure 3 - The LSP Park/Unpark State Machine The LSP Park/Unpark State Machine controls the insertion of the LSPs into the current active scan chain. The ability to park the LSP in certain IEEE1149.1 states, enable the AS91L1006BU to perform several functions including backplane interconnect testing and IC BIST. www.alsc.com Alliance Semiconductor 2003, 2004 © Copyright Alliance Semiconductor Corporation. All Rights reserved. 2 July 2004 AS91L1006BU AS91L1006BU Detailed Mode of Operation Addressing the AS91L1006BU device After a Test-Logic-Reset or power-up, the AS91L1006BU device will be in its Wait-forSelection state with its TDO pin tri-stated, thus avoiding contention in a Multi-Drop environment. The AS91L1006BU device will respond to a device-select sequence for a particular address that is auto generated by third party test tools with respect to the address that is pre-loaded on its S(5..0). Once this sequence has been completed, the AS91L1006BU device will respond to normal IEEE 1149.1 instructions. Note that addresses 6063 have been reserved and the AS91L1006BU device will not respond if the user selects these addresses. The AS91L1006BU device should be in the Wait-for-Selection mode, which can be entered into by issuing an asynchronous reset (through the deassertion of TRST) or by issuing a synchronous reset (through the assertion of TMS for five cycles of TCK). After the device has been selected, it can be issued a GOTOWAIT instruction. The internal IEEE1149.1 state machine of the AS91L1006BU device is taken to the Shift-IR phase and the required Device-ID is shifted into the Instruction register. As the IEEE1149.1 state machine passes through the Update-IR phase, the address is matched to the value on the S(5-0) pins on the AS91L1006BU device; if the values match, then the AS91L1006BU device is selected and is ready to receive any normal IEEE1149.1 command. S(5-0) value IR (7 – 0) value < 3A hex or 60 decimal XXVVVVVV Table 1 - AS91L1006BU www.alsc.com Device Selection Table Alliance Semiconductor 2003, 2004 © Copyright Alliance Semiconductor Corporation. All Rights reserved. 3 July 2004 AS91L1006BU Table 2 - AS91L1006BU Multi Cast Group Selection Table Selection Mode Single Address Mode Binary Function Address XX000000 to Single AS91L1006BU XX111010 selected the TDO of the device will be active Broad XX111011 Cast Mode Multi-Cast XX111100 Group 0 Multi-Cast XX111101 Group 1 Multi-Cast XX111110 Group 2 Multi-Cast XX111111 Group 3 www.alsc.com All accessible AS91L1006BU devices are selected for operation. TDO on all devices will be in HighZ Access all AS91L1006BU devices that have been placed in GRP0 by their MCGR contents Access all AS91L1006BU devices that have been placed in GRP1 by their MCGR contents Access all AS91L1006BU devices that have been placed in GRP2 by their MCGR contents Access all AS91L1006BU devices that have been placed in GRP3 by their MCGR contents Table 3 - AS91L1006BU Device Register Description Register Name Instruction Register BoundaryScan Register Bypass Register Device Identification Register User Code Register Status Register Description AS91L1006BU device addressing and instructiondecode IEEE Std. 1149.1 required register IEEE Std. 1149.1 required register IEEE Std. 1149.1 required register IEEE Std. 1149.1 optional register IEEE Std. 1149.1 optional register AS91L1006BU device non intrusive 8-bit register pre load able from the I/O pins Self Test Register AS91L1006BU device specific single bit register for initiating self testing on a PCB Mode Register AS91L1006BU device local-port configuration and control bits Auto Write Register AS91L1006BU device Auto Write feature enable register LSP Async Reset Register AS91L1006BU device Async reset register for the LSPs Alliance Semiconductor 2003, 2004 © Copyright Alliance Semiconductor Corporation. All Rights reserved. 4 July 2004 AS91L1006BU Instructions BYPASS Hex OpCode FF EXTEST 00 00000000 Boundary-Scan Register SAMPLE/PRELOAD 81 10000001 Boundary-Scan Register IDCODE AA 10101010 Device Identification Register UNPARK E7 11100111 Device Identification Register PARKTLR C5 11000101 Device Identification Register PARKRTI 84 10000100 Device Identification Register PARKPAUSE C6 11000110 Device Identification Register GOTOWAIT* C3 11000011 Device Identification Register MODESELECT 8E 10001110 Mode Register MCGRSELECT 03 00000011 Multi-Cast Group Register. SOFTRESET 88 10001000 Device Identification Register USERCODE 97 10010111 User Programmable 32 Bit Identification Register AUTOWR 98 10011000 Auto Write Feature Enable Register STEST_PCB 99 10011001 Single bit low pulse, used to initiate function on PCB (SELF_TEST pin) STATUS_BYTE 9A 10011010 LSP_ASYNC_RESET 9B 10011011 User programmable status byte (USER_STATUS_DATA pins) Toggles LSP TRST while maintaining the AS91L1006BU in the selected state. TBD TBD Other Undefined Binary Op- Data Register Code 11111111 Bypass Register Device Identification Register Table 4 - AS91L1006BU Device Instruction Register OpCodes Note: All instructions act on a single selected AS91L1006BU device only. * This instruction causes the AS91L1006BU to become unselected and revert to the Wait-forSelection state. www.alsc.com Alliance Semiconductor 2003, 2004 © Copyright Alliance Semiconductor Corporation. All Rights reserved. 5 July 2004 AS91L1006BU AS91L1006BU device Register descriptions Bypass Register Multi-Cast Group Register It is a mandatory single bit register that can be connected between PRIM_TDI and PRIM_TDO of the AS91L1006BU device. This 2-bit data register enables the host system to place the AS91L1006BU into one of four distinct addressable groups. MCGR Register Bits [1..0] 00 Binary Selection Address MCGR GROUP XX111100 GRP0 01 XX111101 GRP1 10 XX111110 GRP2 11 XX111111 GRP3 Table 5 - Multicast Group Register Mapping Note: The MCGR is reset to 00 upon receiving TRST or the entering of the Test-Logic-Reset state. IDCODE Register It is an optional 32-bit register that can be connected between PRIM_TDI and PRIM_TDO of the AS91L1006BU device. The contents of the IDCODE register will be loaded with the following data when the AS91L1006BU enters Test-LogicReset or passes through Capture-IR: "00000000000000001000001101101111" Bits 0 to 11 indicate ALSC Jedec ID value of: “001101101111” Bits 12 to 27 indicate the part number of the device: “0000000000010000” Bits 28 to 31 indicate the revision of the device: “0000” USERCODE Register The USERCODE is an 8-bit register that can be addressed via standard IEEE1149.1 commands, which are automatically generated by third party test tools. AS91L1006BU returns all zeroes if read from this registerUSERUSER and does have the ability to write into this register. * The AS91L1006BU is a complete second source and pin for pin replacement of the Firecron JTS06BU device. www.alsc.com Alliance Semiconductor 2003, 2004 © Copyright Alliance Semiconductor Corporation. All Rights reserved. 6 July 2004 AS91L1006BU SELF_TEST Register The AS91L1006BU device supports a single output pin that can be controlled via the IEEE1149.1 interface. When the instruction is loaded into the AS91L1006BU instruction register, a single bit data register is connected which is always reset to logic zero when the TAP state machine enters Capture-DR. This will cause the SELF_TEST pin to pulse low for one cycle of TCK, during the Update-DR phase. This low going pulse can be used to initiate self-tests on PCB’s in a rack via the JTAG interface. internal registers to be reset. In order to enable async reset tests on LSPs, the test tool should instruct the device to toggle the LSP reset pins while maintaining the set up information in the AS91L1006BU. When the instruction is loaded into the AS91L1006BU instruction register, a single bit data register is connected as the data register which is always reset to logic zero when the TAP state machine enters Capture-DR. This will cause the LSP TRST pins to pulse low for one TCK cycle, during the Update-DR phase. AUTOWR Register LSP_ASYNC_RST Register The AS91L1006BU device supports async reset tests on the devices connected to the LSPs. The standard method of performing these tests by utilizing the primary TRST pin cannot be used as it will cause the AS91L1006BU to deselect and its This is a 6-bit register that controls the passthrough of the JTAG Technologies AutoWR™ signal to any LSP. The register is reset to all zeros when entering the Test-Logic-Reset state. Note: The MCGR is reset to 00 upon receiving TRST or the entering of the Test-Logic-Reset state AutoWr Register (Bit 2 – Bit 0) 000 LSP 3 AutoWr Signal LSP 2 AutoWr Signal LSP 1 AutoWr Signal LSP 6 AutoWr Signal LSP 5 AutoWr Signal LSP 4 AutoWr Signal High Z AutoWr Register (Bit 5 – Bit 3) 000 High Z High Z High Z High Z High Z 001 High Z High Z Active 001 High Z High Z Active 011 High Z Active Active 011 High Z Active Active 100 Active High Z High Z 100 Active High Z High Z 101 Active High Z Active 101 Active High Z Active 110 Active Active High Z 110 Active Active High Z 111 Active Active Active 111 Active Active Active Table 6 - AUTOWR Register Mapping www.alsc.com Alliance Semiconductor 2003, 2004 © Copyright Alliance Semiconductor Corporation. All Rights reserved. 7 July 2004 AS91L1006BU MODE_SELECT Register The Mode_Select register allows the LSP of the AS91L1006BU to be connected in various different configurations. A LSP is selected for connection within the scan chain by the contents of the Mode_Select register. Mode_Select Register (Bit 15 -> Bit 8) XXX0X000 LSP Configuration (If Port Unparked) TDI ->Register->LSP_Data If the LSP is not parked in a stable state, i.e.: Pause-DR, Pause-IR, Run-Test-Idle or TestLogic-Reset, it will be connected into the active scan chain. If all LSPs are parked in a stable state, then the AS91L1006BU will perform a bypass of the 6-LSP chain section. In this way if both sections are in the bypass mode then the AS91L1006BU is performing a loopback of TDI>Register->TDO to the host device. Mode_Select Register (Bit 7 -> Bit 0) XXX0X000 LSP Configuration (If Port Unparked) LSP_Data ->TDO XXX0X001 TDI ->Register->LSP1->PAD-> LSP_Data XXX0X001 LSP_Data ->LSP4->PAD>TDO XXX0X010 TDI ->Register->LSP2->PAD-> LSP_Data XXX0X010 LSP_Data ->LSP5->PAD>TDO XXX0X011 TDI ->Register->LSP1->PAD>LSP2->PAD-> LSP_Data XXX0X011 LSP_Data ->LSP4->PAD>LSP5->PAD->TDO XXX0X100 TDI ->Register->LSP3->PAD-> LSP_Data XXX0X100 LSP_Data ->LSP6->PAD>TDO XXX0X101 TDI ->Register->LSP1->PAD>LSP3->PAD-> LSP_Data XXX0X101 LSP_Data ->LSP4->PAD>LSP6->PAD->TDO XXX0X110 TDI ->Register->LSP2->PAD>LSP3->PAD-> LSP_Data XXX0X110 LSP_Data ->LSP5->PAD>LSP6->PAD->TDO XXX0X111 TDI ->Register->LSP1->PAD>LSP2->PAD->LSP3->PAD-> LSP_Data XXX0X111 LSP_Data ->LSP4->PAD>LSP5->PAD->LSP6->PAD>TDO Table 7 - Mode Select Register Mapping X = Don’t care Register = AS91L1006BU device instruction register or any of the AS91L1006BU device test data registers. PAD = Insertion of a 1-bit register for data synchronization. Upon entering Test-Logic-Reset, the register bits will be loaded with “0000000”. www.alsc.com Alliance Semiconductor 2003, 2004 © Copyright Alliance Semiconductor Corporation. All Rights reserved. 8 July 2004 AS91L1006BU Pass Through Support within the AS91L1006BU Device The AS91L1006BU device supports a Pass-Through mode where the primary or master IEEE1149.1 JTAG signals can be routed to any one of the LSPs. When this mode is activated, the “Debug Enable” signal for that LSP will go active, which can be used to place a processor such as the MPC8260 into BDM (Background Debug mode), if required. If no processors are present in the LSP, the Pass-Through mode can be used to assist in the generation of the test vectors or memory tests for the devices that are linked into the selected LSP. The pass-through feature has the effect of simplifying the test vector generation for the LSP, as it also has the effect of removing the AS91L1006BU device from the test vector generation process. PASS_THRU_Enable PASS_THRU_SEL(2) PASS_THRU_SEL(1) PASS_THRU_SEL(0) Active LSP High X X X Low Low Low Low Normal Operation LSP1 Low Low Low High LSP2 Low Low High Low LSP3 Low Low High High LSP4 Low High Low Low LSP5 Low High Low High LSP6 Table 8 - Pass through mode in AS91L1006BU Note: When PASS_THRU_ENABLE is deasserted (logic “1”), then the LSPs are under control of the AS91L1006BU device logic. When PASS_THRU_ENABLE is asserted (logic “0”) and if an invalid combination is presented on the PASS_THRU_SEL lines, then all LSPs are tri-stated. www.alsc.com Alliance Semiconductor 2003, 2004 © Copyright Alliance Semiconductor Corporation. All Rights reserved. 9 July 2004 AS91L1006BU Signal Description PIN NAME LSP1_TCK LSP1_TMS LSP1_TDO LSP1_TDI LSP1_TRST PIN TYPE OUT OUT OUT IN OUT PIN NUMBER LQFP 31 32 35 33 29 PIN DESCRIPTION NUMBER FPBGA H4 IEEE1149.1 Test Clock on LSP 1 when PASS_THRU_ENABLE is HIGH. J4 H5 K4 K3 Stable state after port/reset Buffered version of signal present on primary TCK Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 000. This pin is tri-stated for all other combinations. IEEE1149.1 Test Mode Select on Logic '1' LSP 1 when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 000. This pin is tri-stated for all other combinations. IEEE1149.1 Test Data Out on LSP 1 Logic '1' when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 000. This pin is tri-stated for all other combinations. IEEE1149.1 Test Data In on LSP 1 when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 000. IEEE1149.1 Test Reset on LSP 1 when PASS_THRU_ENABLE is HIGH. Buffered version of signal present on primary TRST Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 000. This pin is tri-stated for all other combinations. www.alsc.com Alliance Semiconductor 2003, 2004 © Copyright Alliance Semiconductor Corporation. All Rights reserved. 10 July 2004 PIN NAME LSP1_AutoWR LSP1_DE LSP2_TCK LSP2_TMS LSP2_TDO AS91L1006BU PIN TYPE OUT OUT OUT OUT OUT PIN NUMBER LQFP 30 28 41 42 45 PIN Stable state DESCRIPTION NUMBER after port/reset FPBGA J3 Flash, Memory Auto-Write on LSP 1 Logic '1' when PASS_THRU_ENABLE is HIGH. J2 J6 H6 J7 Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 000; PRIM_AutoWR is routed to output. This pin is tri-stated for all other combinations. Pass-Through Debug Enable Output Logic '1' on Local Scan Port 1. Active low output when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 000. This pin is high for all other combinations. IEEE1149.1 Test Clock on LSP 2 when PASS_THRU_ENABLE is HIGH. Buffered version of signal present on primary TCK Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 001. This pin is tri-stated for all other combinations. IEEE1149.1 Test Mode Select on Logic '1' LSP 2 when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 001. This pin is tri-stated for all other combinations. IEEE1149.1 Test Data Out on LSP 2 Logic '1' when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 001. This pin is tri-stated for all other combinations. www.alsc.com Alliance Semiconductor 2003, 2004 © Copyright Alliance Semiconductor Corporation. All Rights reserved. 11 July 2004 PIN NAME LSP2_TDI LSP2_TRST LSP2_AutoWR LSP2_DE LSP3_TCK AS91L1006BU PIN TYPE IN OUT OUT OUT OUT PIN NUMBER LQFP 44 37 40 36 49 PIN DESCRIPTION NUMBER FPBGA K7 IEEE1149.1 Test Data In on LSP 2 when PASS_THRU_ENABLE is HIGH. K5 K6 J5 K9 Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 001. IEEE1149.1 Test Reset on LSP 2 when PASS_THRU_ENABLE is HIGH. Stable state after port/reset Buffered version of signal present on primary TRST Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 001. This pin is tri-stated for all other combinations. Flash, Memory Auto-Write on LSP 2 Logic '1' when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 001; PRIM_AutoWR is routed to output. This pin is tri-stated for all other combinations. PASS_THRU Debug Enable Output Logic '1' on LSP 2. Active low output when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 001. This pin is high for all other combinations. IEEE1149.1 Test Clock on LSP 3 when PASS_THRU_ENABLE is HIGH. Buffered version of signal present on primary TCK Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 010. This pin is tri-stated for all other combinations. www.alsc.com Alliance Semiconductor 2003, 2004 © Copyright Alliance Semiconductor Corporation. All Rights reserved. 12 July 2004 PIN NAME LSP3_TMS LSP3_TDO LSP3_TDI LSP3_TRST LSP3_LSP_ AutoWR AS91L1006BU PIN TYPE OUT OUT IN OUT OUT PIN NUMBER LQFP 50 53 52 47 48 PIN Stable state DESCRIPTION NUMBER after port/reset FPBGA K10 IEEE1149.1 Test Mode Select on Logic '1' LSP 3 when PASS_THRU_ENABLE is HIGH. H10 J10 J8 K8 Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 010. This pin is tri-stated for all other combinations. IEEE1149.1 Test Data Out on LSP 3 Logic '1' when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 010. This pin is tri-stated for all other combinations. IEEE1149.1 Test Data In on LSP 3 when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 010. IEEE1149.1 Test Reset on LSP 3 when PASS_THRU_ENABLE is HIGH. Buffered version of signal present on primary TRST Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 010. This pin is tri-stated for all other combinations. Flash, Memory Auto-Write on LSP 3 Logic '1' when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 010; PRIM_AutoWR is routed to output. This pin is tri-stated for all other combinations. www.alsc.com Alliance Semiconductor 2003, 2004 © Copyright Alliance Semiconductor Corporation. All Rights reserved. 13 July 2004 PIN NAME LSP3_DE LSP4_TCK LSP4_TMS LSP4_TDO LSP4_TDI AS91L1006BU PIN TYPE OUT OUT OUT OUT IN PIN NUMBER LQFP 46 79 78 76 77 PIN Stable state DESCRIPTION NUMBER after port/reset FPBGA H7 PASS_THRU Debug Enable Output Logic '1' on LSP 3. A8 A9 B10 B9 Active low output when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 010. This pin is high for all other combinations. IEEE1149.1 Test Clock on LSP 4 when PASS_THRU_ENABLE is HIGH. Buffered version of signal present on primary TCK Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 011. This pin is tri-stated for all other combinations. IEEE1149.1 Test Mode Select on Logic '1' LSP 4 when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 011. This pin is tri-stated for all other combinations. IEEE1149.1 Test Data Out on LSP 4 Logic '1' when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 011. This pin is tri-stated for all other combinations. IEEE1149.1 Test Data In on LSP 4 when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 011. www.alsc.com Alliance Semiconductor 2003, 2004 © Copyright Alliance Semiconductor Corporation. All Rights reserved. 14 July 2004 PIN NAME LSP4_TRST LSP4_AutoWR LSP4_DE LSP5_TCK LSP5_TMS AS91L1006BU PIN TYPE OUT OUT OUT OUT OUT PIN NUMBER LQFP 81 80 83 70 69 PIN DESCRIPTION NUMBER FPBGA A7 IEEE1149.1 Test Reset on LSP 4 when PASS_THRU_ENABLE is HIGH. B8 B7 D10 D9 Stable state after port/reset Buffered version of signal present on primary TRST Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 011. This pin is tri-stated for all other combinations. Flash, Memory Auto-Write on LSP 4 Logic '1' when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 011; PRIM_AutoWR is routed to output. This pin is tri-stated for all other combinations. PASS_THRU Debug Enable Output Logic '1' on LSP 4. Active low output when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 011. This pin is high for all other combinations. IEEE1149.1 Test Clock on LSP 5 when PASS_THRU_ENABLE is HIGH. Buffered version of signal present on primary TCK Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 100. This pin is tri-stated for all other combinations. IEEE1149.1 Test Mode Select on Logic '1' LSP 5 when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 100. This pin is tri-stated for all other combinations. www.alsc.com Alliance Semiconductor 2003, 2004 © Copyright Alliance Semiconductor Corporation. All Rights reserved. 15 July 2004 PIN NAME LSP5_TDO LSP5_TDI LSP5_TRST LSP5_AutoWR LSP5_DE AS91L1006BU PIN TYPE OUT IN OUT OUT PIN NUMBER LQFP 67 68 72 71 75 PIN Stable state DESCRIPTION NUMBER after port/reset FPBGA E8 IEEE1149.1 Test Data Out on LSP 5 Logic '1' when PASS_THRU_ENABLE is HIGH. E7 C9 D8 C10 Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 100. This pin is tri-stated for all other combinations. IEEE1149.1 Test Data In on LSP 5 when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 100. IEEE1149.1 Test Reset on LSP 5 when PASS_THRU_ENABLE is HIGH. Buffered version of signal present on primary TRST Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 100. This pin is tri-stated for all other combinations. Flash, Memory Auto-Write on LSP 5 Logic '1' when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 100; PRIM_AutoWR is routed to output. This pin is tri-stated for all other combinations. PASS_THRU Debug Enable Output Logic '1' on LSP 5. Active low output when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 100. This pin is high for all other combinations. www.alsc.com Alliance Semiconductor 2003, 2004 © Copyright Alliance Semiconductor Corporation. All Rights reserved. 16 July 2004 PIN NAME LSP6_TCK LSP6_TMS LSP6_TDO LSP6_TDI LSP6_TRST AS91L1006BU PIN TYPE OUT OUT OUT IN OUT PIN NUMBER LQFP 61 60 57 58 64 PIN DESCRIPTION NUMBER FPBGA F10 IEEE1149.1 Test Clock on LSP 6 when PASS_THRU_ENABLE is HIGH. F9 G10 G8 E9 Stable state after port/reset Buffered version of signal present on primary TCK Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 101. This pin is tri-stated for all other combinations. IEEE1149.1 Test Mode Select on Logic '1' LSP 6 when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 101. This pin is tri-stated for all other combinations. IEEE1149.1 Test Data Out on LSP 6 Logic '1' when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 101. This pin is tri-stated for all other combinations. IEEE1149.1 Test Data In on LSP 6 when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 101. IEEE1149.1 Test Reset on LSP 5 when PASS_THRU_ENABLE is HIGH. Buffered version of signal present on primary TRST Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 101. This pin is tri-stated for all other combinations. www.alsc.com Alliance Semiconductor 2003, 2004 © Copyright Alliance Semiconductor Corporation. All Rights reserved. 17 July 2004 PIN NAME LSP6_AutoWR LSP6_DE AS91L1006BU PIN TYPE OUT OUT PIN NUMBER LQFP 63 65 PIN Stable state DESCRIPTION NUMBER after port/reset FPBGA F7 Flash, Memory Auto-Write on LSP 6 Logic '1' when PASS_THRU_ENABLE is HIGH. E10 Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 101; PRIM_AutoWR is routed to output. This pin is tri-stated for all other combinations. PASS_THRU Debug Enable Output Logic '1' on LSP 6. Active low output when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 101. This pin is high for all other combinations. IEEE1149.1 Primary Test Clock Input. IEEE1149.1 Primary Test Mode Select Input. IEEE1149.1 Primary Test Data Output. This pin is tri-stated when AS91L1006BUis not selected. PRIM_TCK IN 87 A6 PRIM_TMS IN 21 G2 PRIM_TDO OUT 20 G1 PRIM_TDI IN 19 G3 IEEE1149.1 Primary Test Data Input PRIM_TRST IN 22 H2 IEEE1149.1 Primary Test Reset Input. PRIM_AutoWR IN S[5:0] IN *TOE IN HighZ This active low asynchronous reset input signal places AS91L1006U in Wait-for-Selection state. 16 F1 Primary Auto-Write Input controlled by test equipment to shorten Flash memory programming. 8,7,6,5,100, D2,D1,D3,C AS91L1006BU Slot Address[5:0] 99 2,B2,A2 Inputs. 88 B6 Used to set address at which AS91L1006BU will respond; typically set by hardwired connection on the backplane. Test Output Enable Input. Tri-states all LSPs, when asserted low. www.alsc.com Alliance Semiconductor 2003, 2004 © Copyright Alliance Semiconductor Corporation. All Rights reserved. 18 July 2004 AS91L1006BU PIN NAME PIN TYPE LSP_RESET_n IN AS91L1006BU_ SELECTED LSP_ENABLE USER_STATUS _BYTE[7:0] SELF_TEST PASS_THRU_ ENABLE PASS_THRU_ SEL12:0] OUT OUT IN OUT IN IN PIN NUMBER LQFP 14 25 24 PIN DESCRIPTION NUMBER FPBGA F4 LSP Reset Input. Stable state after port/reset K1 Active low resets AS91L1006BU to “Wait-for-Selection” state and pulses all LSP TRST output pins to low. This resets all devices with TRST function; typically this signal would be connected to a power-on-reset function. AS91L1006BU_Selected Output. Logic '1' J1 Active low when AS91L1006BU is selected; typically used to control off board buffering. LSP Enabled Output. Logic '1' Active low when AS91L1006BU is selected; typically used to set IEEE1149.1 compliance enable pins on devices. 84, 85, 92, C7,C6,C5,C AS91L1006BU Status_Byte Inputs. 93, 94, 96, 4,B4,A4,B3, 97, 98 A3(MSB- Used to provide status information of (MSB-LSB) LSB) the PCB under test back to the test master via the IEEE1149.1 bus. Eight signals levels can be monitored and then reported via the IEEE1149.1 bus in a non intrusive manner. 27 K2 Provides a low going output pulse Logic '1' under command from the IEEE1149.1 bus, which can be used to start self-test functions on a PCB. 9 E4 PASS_THRU Enable Input. Active high disables Pass-Through mode. Active low enables Pass-Through mode. 13,12,10 E2,E1,E3 PASS_THRU Select Inputs. (MSB-LSB) (MSB-LSB) Used to select active routing of PassThrough ports enabled by active low on PASS_THRU_ENABLE pin. 000 = LSP1 001 = LSP2 010 = LSP3 011 = LSP4 100 = LSP5 101 = LSP6 www.alsc.com Alliance Semiconductor 2003, 2004 © Copyright Alliance Semiconductor Corporation. All Rights reserved. 19 July 2004 AS91L1006BU PIN NAME PIN TYPE GND POWER VCC POWER ASIC_TEST_ EN IN PIN NUMBER LQFP 38, 86, 11, 26, 43, 59, 74, 95, 2, 17, 54, 55 90 PIN DESCRIPTION NUMBER FPBGA D6, G5, C3, Ground pins. D7, E5, F6, G4,H8, H9, J9,B1, A5, F2 39, 91, 3, D5, G6, C8, VCC pins. 18, 34, 51, D4, E6, F5, 66, G7, 82,23,56 H3,G9,H1 89 B5 Factory Test_Enable Input. This pin should be left unconnected. IEEE1149.1 ASIC Test Clock Input. ASIC_TCK IN 62 F8 ASIC_TMS IN 15 F3 ASIC_TDO OUT 73 A10 IEEE1149.1 ASIC Test Mode Select. Input IEEE1149.1 ASIC Test Clock Output. ASIC_TDI IN 4 A1 IEEE1149.1 ASIC Test Clock Input. 1 C1 No Connects Stable state after port/reset Table 9 - AS91L0006BU Signal Description Absolute Maximum Ratings Parameter Maximum Range Supply Voltage (Vcc) -0.3V to 5.5V DC Input Voltage (Vi) -0.5V to Vcc +0.5V Max sink current when Vi = -0.5V -20mA Max source current when Vi = Vcc + 0.5V +20mA Max Junction Temperature with power applied Tj +125 degrees C Max Storage temperature -55 to +150 degree C Table 10 - Absolute Maximum Ratings Note: Stress above the stated maximum values may cause irreparable damage to the device. Correct operation of the device at these values is not guaranteed. Recommended Operating Conditions www.alsc.com Alliance Semiconductor 2003, 2004 © Copyright Alliance Semiconductor Corporation. All Rights reserved. 20 July 2004 AS91L1006BU Parameter Operating Range Supply Voltage (Vcc) 3.0V to 3.6V Input Voltage (Vi) 0V to Vcc Output Voltage (Vo) 0V to Vcc Operating Temperature (Ta) Commercial 0 C to 70 C Industrial (Ta) -40 deg C to +85 deg C, 3.00V to 3.6V Table 11 - Recommended Operating Conditions www.alsc.com Alliance Semiconductor 2003, 2004 © Copyright Alliance Semiconductor Corporation. All Rights reserved. 21 July 2004 AS91L1006BU AC Electrical Characteristics Tch Tcl Tcw TCK Tsu Th TMS TDI Toe Tco TDO High Z High Z Tpd Lsp Signal Figure 4 - AS91L1006BU AC Timing Diagram SYMBOL Parameter MIN MAX UNITS TCK clock pulse width 100 - ns Tch TCK pulse width high 50 - ns Tcl TCK pulse width low 50 - ns Tsu TCK Setup time 30 - ns Th TCK Hold time 40 - ns Toe Neg Edge TCK to valid data enable 20 - ns Tco Neg Edge TCK to valid data 15 - ns Tpd Pass through Mode Primary/Lsp Delay - 10 ns Tcw Table 12 - AS91L1006BU AC Timing Information www.alsc.com Alliance Semiconductor 2003, 2004 © Copyright Alliance Semiconductor Corporation. All Rights reserved. 22 July 2004 AS91L1006BU DC Electrical Characteristics Symbol VIH VIL Symbol VOH VOL Parameter Minimum High Input Voltage Maximum Low Input Voltage Parameter Max 5.25 Min 2.0 0.8V -0.3V Value Condition Minimum High Output Voltage 2.4V Ioh=24mA or 8mA as defined by pin Minimum LowOutput Voltage 0.4V Iol=24mA or 8mA as defined by pin Ioz Tristate output leakage -10 or 10 mA Icc Maximum quiecennt supply current Maximum dynamic supply current Iccd Condition 2mA 80mA TCK freq equal to 10 MHz Table 13 - AS91L1006BU DC Electrical Characteristics Packaging Information The AS91L1006BU is available in a 100-pin LQFP or a 100-pin FPBGA lead free package. SYM BO L 1 LE AD S A 1 A 2 M IN M IN D M A X N O M 0 .0 5 1 .3 5 M AX 1 .4 5 B A S IC 1 8 .0 0 B A S IC 1 4 .0 0 0 .1 5 0 .6 0 L1 R EF 1 M IN b 1 .0 0 0 .1 7 M A X 0 .2 7 B A S IC 0 .5 0 ccc M AX 0 .0 8 ddd N O M e 0 .0 8 M S -0 2 6 JED EC R EF # 3 0 .1 5 1 .4 0 L D D1 Square 1 .6 0 M AX. A D Square 100 LEA D TO L. NOTES : 1. ALL LIN EAR DIM ENSIO NS ARE IN M ILLIM E TE RS . 2. PLAS TIC BO DY D IM EN SIO NS DO N O T INC LU DE FLAS H O R PR O TUSIO N . M AX ALLO W ABLE 0.25 PER SIDE. 3. LEAD C O UN T O N D RA W ING N O T RE PRESENTATIVE O F A CTUAL PACKAG E. 12 NOM A A1 0-7 TYP A A2 -C0.09/0.20 TYP e 0.25 L1 L b CCC LEAD COPLANARITY al al al M A-B S D S 12 NOM Figure 5 - LQFP-100 www.alsc.com Alliance Semiconductor 2003, 2004 © Copyright Alliance Semiconductor Corporation. All Rights reserved. 21 July 2004 AS91L1006BU D A 2 REV. A B B Revisions DESCRIPTION Initial document release. Updated ball coplanarity limits from 0.20mm to 0.15mm. ECN 91253 DATE 12-04-01 E C 0.15 C D1 K I H G F E1 E D C B A 1 2 3 4 5 b 6 7 8 SYMBOL A A1 A2 b D D1 E E1 e PACKAGE NUMBER JEDEC REF # DIMENSIONS MIN. -0.30 0.25 0.50 NOM. ---0.60 11.00 BSC 9.00 BSC 11.00 BSC 9.00 BSC 1.00 FBGA0100-11F MO-192 VAR. AAC-1 9 10 0.25 M C A B 0.25 M C Figure 6 - FPBGA-100 www.alsc.com Alliance Semiconductor 2003, 2004 © Copyright Alliance Semiconductor Corporation. All Rights reserved. 22 MAX. 1.70 -1.10 0.70 July 2004 AS91L1006BU Device Selector Guide and Ordering Information AS91L XXXX UU - CC PP - TEMP - L Aliance Semiconductor system solution Blank = leaded F = lead free G = green Device family 1001 1002 1003 1006 C = Commercial (0 to 70 degrees C) I = Industrial (-40 to 85 degrees C) Package L100 = 100 pin LQFP F100 = 100 pin FPBGA Product version S = standard U = 16-bit user code BU = 8-bit status/user code E = enhanced Clock speed 10 = 10 MHz TCK 40 = 40 MHz TCK Figure 7 - Part Numbering Guide www.alsc.com Alliance Semiconductor 2003, 2004 © Copyright Alliance Semiconductor Corporation. All Rights reserved. 23 July 2004 AS91L1006BU Part Number Description AS91L1006BU – 10L100-C JTAG 6-Port Gateway, 100-pin LQFP package, commercial AS91L1006BU – 10L100-CF JTAG 6-Port Gateway, 100-pin LQFP package, commercial, lead free AS91L1006BU – 10L100-I JTAG 6-Port Gateway, 100-pin LQFP package, industrial AS91L1006BU – 10L100-IF JTAG 6-Port Gateway, 100-pin LQFP package, industrial, lead free AS91L1006BU – 10F100-C JTAG 6-Port Gateway 100-pin FPBGA package, commercial AS91L1006BU – 10F100-CG JTAG 6-Port Gateway 100-pin FPBGA, commercial, green package AS91L1006BU – 10F100-I JTAG 6-Port Gateway 100-pin FPBGA package, industrial AS91L1006BU – 10F100-IG JTAG 6-Port Gateway 100-pin FPBGA, industrial, green package AS91L1006BU – 40L100-CF JTAG 6-Port Gateway, 100-pin LQFP package, commercial, lead free, 40 MHz TCK AS91L1006BU – 40L100-IF JTAG 6-Port Gateway, 100-pin LQFP package, industrial, lead free, 40 MHz TCK AS91L1006BU – 40F100-CG JTAG 6-Port Gateway 100-pin FPBGA, commercial, green package, 40 MHz TCK AS91L1006BU – 40F100-IG JTAG 6-Port Gateway 100-pin FPBGA, industrial, green package, 40 MHz TCK Table 14 - Valid Part Number Combinations www.alsc.com Alliance Semiconductor 2003, 2004 © Copyright Alliance Semiconductor Corporation. All Rights reserved. 24 July 2004 Device Master AS91L1006BU Package Options Description FPBGA-100 (1mm pitch) LQFP-100 AS91L1001 JTAG Test Controller x x AS91L1002 JTAG Test Sequencer x x AS91L1003U 3-Port Gateway x x AS91L1006BU 6-Port Gateway x x Table 15 - JTAG Controller Product Family www.alsc.com Alliance Semiconductor 2003, 2004 © Copyright Alliance Semiconductor Corporation. All Rights reserved. 25 July 2004 www.alsc.com AS91L1006BU Alliance Semiconductor 2003, 2004 © Copyright Alliance Semiconductor Corporation. All Rights reserved. 26