RF3334 0 IF LOW NOISE AMPLIFIER/MIXER Typical Applications • Cable Set Top Box • Commercial and Consumer Systems • General Purpose Downconverter Product Description The RF3334 is an IF LNA/Mixer suitable for downconversion of forward channel control data in a set-top box application. It consists of a single-ended 75Ω terminated LNA, followed by a differential gain control stage with 30dB of analog gain control and a double-balanced mixer. The mixer load is available via pins 10 and 11 should an external filter be required. The mixer output is connected to an IF amplifier that can be configured from 10dB to 40dB gain with an external resistor. The amplifier is capable of 6V pk-pk output into a 1kΩ load. 2 PLCS 0.10 C A -A- 0.05 C 0.90 0.85 4.00 SQ. 0.70 0.65 2.00 TYP 0.05 0.00 0.10 C B 2 PLCS 12° MAX 0.10 C B 2 PLCS -B- -C- 1.87 TYP 3.75 SQ SEATING PLANE Shaded lead is pin 1. 0.10 C A 2 PLCS Dimensions in mm. 0.10 M C A B 0.60 0.24 TYP 0.35 0.23 Pin 1 ID 0.20 R 2.25 SQ. 1.95 0.75 TYP 0.50 0.65 Optimum Technology Matching® Applied Si BJT 9Si Bi-CMOS InGaP/HBT GaAs HBT GaAs MESFET SiGe HBT Si CMOS GaN HEMT SiGe Bi-CMOS Package Style: QFN, 16-Pin, 4x4 Features • 30dB RF Gain Control RFVCC GND LOB LO • 40dB IF Gain Control 16 15 14 13 • 5dB Max. Noise Figure SSB • LNA Input Internally Matched to 75Ω 12 RFAGC RFDEC 1 11 MIXLOAD RFIN 2 GND 3 10 MIXLOADB Ordering Information IF AMP 5 6 7 8 IFSETB IFOUT IFOUTB 9 GND IFSET IFVCC 4 Functional Block Diagram Rev A5 031020 • Single 5V Supply RF3334 RF3334 PCBA LNA Mixer Fully Assembled Evaluation Board RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com 8-457 RF3334 Absolute Maximum Ratings Parameter Supply Voltage IF Input Level Operating Ambient Temperature Storage Temperature Parameter Rating Unit -0.5 to 7.0 500 -40 to +85 -40 to +150 VDC mVpp °C °C Specification Min. Typ. Max. Caution! ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s). Unit Condition DC Specifications Supply Voltage Supply Current RFAGC Control Voltage 4.75 20 0.5 RFAGC Input Impedance 5 24 5.25 4.5 V mA V 300 kΩ 0 to 700 MHz RF Input 3dB Bandwidth 700 MHz RF Input Impedance RF Input VSWR Mixer Output 3dB Bandwidth Mixer Output Impedance Mixer Output VSWR Maximum Gain Minimum Gain Output 1dB Compression Input IP3, Maximum Gain Input IP3, Minimum Gain Noise Figure 75 1.4 100 300 1.2 30 -2 90 78 79 Ω 0.5V=Minimum Gain 4.5V=Maximum Gain AC Specifications LNA+AGC+Mixer RF Frequency Range 27 MHz Ω 5 dB dB dBµV(rms) dBµV(rms) dBµV(rms) dB On-chip signal path is DC-coupled, minimum frequency depends on external AC coupling components. On-chip signal path is DC-coupled, minimum frequency depends on external AC coupling components. At 100MHz Defined by on-chip first-order low-pass filter Differential At 100MHz RFAGC=4.5V RFAGC=0.5V Maximum Gain LNA Input to Mixer Output LNA Input to Mixer Output SSB, Cascaded LNA, AGC & Mixer LO LO Frequency Range LO Input Impedance LO Input VSWR LO Input Level LO Bandwidth LO Rejection to RF Input LO Rejection to Input of IF Amplifier 0 to 800 75 1.6:1 MHz Ω 80 800 50 65 dBuV MHz dB dB 0 to 120 4000 10 MHz Ω Ω 10 31 40 dB dB dB MHz µVrms VP-P dBµV(rms) dBµV(rms) Differential IF Amplifier IF Frequency Range Input Impedance Output Impedance Differential Voltage Gain Gain Set Resistor=2500Ω Gain Set Resistor=140Ω Gain Set Resistor=5Ω IF 3dB Bandwidth Equivalent Input Noise Output Swing Output 1dB Compression Output IP3 8-458 140 1.5 6 127 137 8 Differential Differential R1=1kΩ R1=1kΩ R1=1kΩ Gain Set=5Ω Gain Set=140Ω Into 1kΩ load, at 50MHz Into 1kΩ load, at 50MHz Into 1kΩ load, at 50MHz Rev A5 031020 RF3334 Parameter Specification Min. Typ. Max. Unit VCC =5.25V, VRFAGC=4.5V, ICC =29mA, PDISS =154mW Thermal ThetaJC Maximum Measured Junction Temperature at DC Bias Conditions Rev A5 031020 Condition 65 95 °C/W °C TAMB =+85°C 8-459 RF3334 Pin 1 Function RFDEC Description Interface Schematic External decoupling capacitor for RF single-ended to differential converter. VCC 100 Ω RFDEC 2 RF LNA Input, Internally matched to 75Ω. Should be AC-coupled. VBIAS RF 3 4 5 6 7 GND IFVCC IFSET IFSETB IFOUT Ground. 5V supply for IF section. IF Gain select. The resistance between this pin and pin 6 (IFSETB) determines the gain of the IF amplifier. Maximum gain is achieved by placing a short circuit between the pins. Larger values of resistance will reduce the IF gain according to the following equation where R is the value of resistance between pins 5 and 6. IFGain=20log(1600/(R=75))15. IFSET IFSETB IFSET IFSETB Complementary IF Gain select. IF Amplifier Output. Differential output of the IF amplifier. The differential load across this pin and pin 8 (IFOUTB) should be 1kΩ or greater for optimal performance. The differential output impedance across this pin and pin 8 in 10Ω. VCC VBIAS 8 IFOUTB Complementary IF Amplifier Output. VCC VBIAS 9 10 GND MIXLOADB 11 MIXLOAD 8-460 IF OUT IF OUTB Ground. Complementary Mixer load. MIXLOAD MIXLOADB Differential output of the RF mixer. A resonant load should be applied to this pin and pin 10 (MIXLOADB) that will act as a bandpass filter at the desired IF frequency. VCC should be supplied to this pin via an inductor or a resistor. Use of a resistor will degrade intermodulation performance. MIXLOAD MIXLOADB Rev A5 031020 RF3334 Pin 12 13 Function RFAGC LO Description RF Gain select voltage input. The voltage applied to this pin sets the gain of the RF amplifier. The voltage applied to this pin should be between 0.5V and 4.5V. The RF gain characteristic is such that 0.5V yields a gain of -2dB and 4.5V yields a gain of +30dB as measured from the input of the LNA to the output of the mixer stage. Differential LO Input. This pin and pin 14 (LOB) are the differential LO inputs. This input should be AC-coupled. The differential input impedance across pins 13 and 14 is 75Ω. The LO may be driven single ended but will require a higher drive level. If a single ended LO is applied, pin 14 should be AC-coupled to ground. Interface Schematic 100 kΩ 10 kΩ RFAGC VREF LOB 300 Ω VBIAS 75 Ω 300 Ω LO 14 LOB Complementary LO Input. Should be AC-coupled. LOB 300 Ω VBIAS 75 Ω 300 Ω LO 15 16 GND GND RFVCC Paddle Rev A5 031020 Ground. 5V supply for RF section. Backside of package should be connected to ground. 8-461 RF3334 RFVCC GND LOB LO Pin-Out 16 15 14 13 12 RFAGC RFDEC 1 RFIN 2 11 MIXLOAD GND 3 10 MIXLOADB 8-462 5 6 7 8 IFSETB IFOUT IFOUTB 9 GND IFSET IFVCC 4 Rev A5 031020 RF3334 Application Schematic LOB LO 10 nF VCC 10 nF 1 kΩ RFAGC + 1 uF 1 nF 10 nF 10 pF 16 15 14 13 C 10 nF 1 12 L RFIN 2 11 10 nF R L 3 VCC 10 VCC IF AMP 4 9 10 n 5 6 7 C 8 IFOUT IFOUTB R* Rev A5 031020 8-463 RF3334 Evaluation Board Schematic (Download Bill of Materials from www.rfmd.com.) T1 50 Ω µstrip TTWB-1-A R1 1 kΩ RFAGC VCC + C1 1 uF C10 1 nF C4 10 nF C11 10 pF 16 C2 10 nF 15 14 C5 82 pF 13 1 12 2 11 L1 120 nH 50 Ω µstrip J3 RF IN R6 750 Ω C3 10 nF 3 VCC 4 C6 10 nF J1-3 1 VCC 2 GND 3 RF AGC 5 6 7 8 CON3 R3 475 Ω R2 140 Ω VCC C8 82 pF 9 J1 J1-1 L2 120 nH 10 IF AMP 8-464 J2 LO R4 475 Ω R5 100 Ω C7 10 n C9 10 n J4 IFOUT J5 IFOUTB Rev A5 031020 RF3334 Evaluation Board Layout Board Size 2.0” x 2.0” Board Thickness 0.032”, Board Material FR-4, Multi-layer Rev A5 031020 8-465 RF3334 4 4.0 5.0 0.8 2.0 0 3. 4.0 5. 0 0.2 0. 0.2 10.0 4.0 5.0 3.0 2.0 1.0 0.8 0.6 0.4 0.2 10.0 0 10.0 3.0 4.0 5.0 2.0 1.0 0.8 0.6 0.4 0.2 10.0 -10.0 .0 -2 -1.0 6 Swp Min 0.05GHz -0.8 -1.0 -0.8 .4 -0. 0 .0 -2 -3 . 6 -0 -3 .0 -4 . 0 -5.0 -0. -0.2 -4. 0 -5.0 .4 -0 -10.0 0 Swp Max 0.2GHz 0.6 2. 0 3.0 -0.2 8-466 1.0 1.0 0.8 LO Input, Temp = +25°C Swp Max 0.2GHz 0. 4 0.6 RF Input, Temp = +25°C Swp Min 0.05GHz Rev A5 031020 RF3334 35.0 LNA + AGC + Mixer Gain versus Control Voltage over Temperature (Freq = 100 MHz, VCC = 5.0 V) 90.0 LNA + AGC + Mixer + IF AMP - IIP3 versus Gain over Temperature (Freq = 100 MHz, VCC = 5.0 V) 88.0 30.0 86.0 25.0 84.0 IIP3 (dBµV) Gain (dB) 20.0 15.0 10.0 82.0 80.0 78.0 76.0 5.0 74.0 -40°C 0.0 +25°C -40°C +25°C 72.0 +85°C +85°C -5.0 70.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 30.0 35.0 40.0 45.0 RFAGC (V) 35.0 50.0 55.0 60.0 65.0 Gain (dB) SSB, Cascaded Noise Figure versus Gain over Temperature (Freq = 100 MHz, VCC = 5.0 V) RF Input VSWR versus Frequency Across Temperature (VCC = 5.0 V) 1.40 -40°C 1.38 +25°C 30.0 +85°C 1.36 1.34 RF Input VSWR Noise Figure (dB) 25.0 20.0 15.0 1.32 1.30 1.28 1.26 10.0 1.24 -40°C 5.0 +25°C 1.22 +85°C 0.0 25.0 1.20 30.0 35.0 40.0 45.0 50.0 55.0 60.0 65.0 Gain (dB) 1.75 70.00 80.00 90.00 100.00 110.00 120.00 130.00 Frequency (MHz) LO Input VSWR versus Temperature Across Temperature (VCC = 5.0 V) LO Input VSWR 1.70 1.65 1.60 -40°C 1.55 +25°C +85°C 1.50 118.00 128.00 138.00 148.00 158.00 168.00 178.00 Frequency (MHz) Rev A5 031020 8-467 RF3334 PCB Design Requirements PCB Surface Finish The PCB surface finish used for RFMD’s qualification process is electroless nickel, immersion gold. Typical thickness is 3µinch to 8µinch gold over 180µinch nickel. PCB Land Pattern Recommendation PCB land patterns are based on IPC-SM-782 standards when possible. The pad pattern shown has been developed and tested for optimized assembly at RFMD; however, it may require some modifications to address company specific assembly processes. The PCB land pattern has been developed to accommodate lead and package tolerances. PCB Metal Land Pattern A = 0.69 x 0.28 (mm) Typ. B = 0.28 x 0.69 (mm) Typ. C = 2.40 (mm) Sq. Dimensions in mm. 1.95 Typ. 0.65 Typ. Pin 16 B B B B Pin 12 Pin 1 A A 0.65 Typ. A A 0.98 1.95 Typ. C A A A A 0.81 Typ. B B B B Pin 8 0.81 Typ. 0.98 Figure 1. PCB Metal Land Pattern (Top View) 8-468 Rev A5 031020 RF3334 PCB Solder Mask Pattern Liquid Photo-Imageable (LPI) solder mask is recommended. The solder mask footprint will match what is shown for the PCB metal land pattern with a 2mil to 3mil expansion to accommodate solder mask registration clearance around all pads. The center-grounding pad shall also have a solder mask clearance. Expansion of the pads to create solder mask clearance can be provided in the master data or requested from the PCB fabrication supplier. A = 0.79 x 0.38 (mm) Typ. B = 0.38 x 0.79 (mm) Typ. C = 2.50 (mm) Sq. Dimensions in mm. 1.95 Typ. 0.65 Typ. Pin 16 B B B B Pin 1 Pin 12 A A 0.65 Typ. A A 0.98 1.95 Typ. C A A A A 0.81 Typ. B B B B Pin 8 0.81 Typ. 0.98 Figure 2. PCB Solder Mask Pattern (Top View) Thermal Pad and Via Design The PCB land pattern has been designed with a thermal pad that matches the die paddle size on the bottom of the device. Thermal vias are required in the PCB layout to effectively conduct heat away from the package. The via pattern has been designed to address thermal, power dissipation and electrical requirements of the device as well as accommodating routing strategies. The via pattern used for the RFMD qualification is based on thru-hole vias with 0.203mm to 0.330mm finished hole size on a 0.5mm to 1.2mm grid pattern with 0.025mm plating on via walls. If micro vias are used in a design, it is suggested that the quantity of vias be increased by a 4:1 ratio to achieve similar results. Rev A5 031020 8-469 RF3334 8-470 Rev A5 031020