LTC4260 Positive High Voltage Hot Swap Controller with 2 I C Compatible Monitoring U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO The LTC®4260 Hot SwapTM controller allows a board to be safely inserted and removed from a live backplane. Using an external N-channel pass transistor, the board supply voltage can be ramped up at an adjustable rate. An I2C interface and onboard ADC allow monitoring of board current, voltage and fault status. Allows Safe Insertion into Live Backplane 8-Bit ADC Monitors Current and Voltage I2CTM/SMBus Interface Wide Operating Voltage Range: 8.5V to 80V High Side Drive for External N-Channel MOSFET Input Overvoltage/Undervoltage Protection Optional Latchoff or Autoretry After Faults Alerts Host After Faults Foldback Current Limiting Available in 24-Lead SO, 24-Lead Narrow SSOP and 32-Lead (5mm × 5mm) QFN Packages The device features adjustable analog foldback current limit with latch off or automatic restart after the LTC4260 remains in current limit beyond an adjustable time-out delay. The controller has additional features to interrupt the host when a fault has occurred, notify when output power is good, detect insertion of a load card and power-up in either the on or off state. U APPLICATIO S ■ ■ ■ Electronic Circuit Breakers Live Board Insertion Computers, Servers , LTC and LT are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. I2C is a trademark of Philips Electronics N.V. U TYPICAL APPLICATIO 3A, 48V Card Resident Application 0.010Ω 48V Power Up Waveforms FDB3632 VOUT 48V + CL 49.9k 10Ω CONNECTOR 1 CONNECTOR 2 0.1µF SDA SCL ALERT * 2.67k 3.57k 6.8nF 1.74k 43.5k 100k UV VDD SENSE GATE OV SDAO SDAI LTC4260 SCL ALERT ON INTVCC TIMER SOURCE FB CL = 1000µF VIN 50V/DIV IIN 2A/DIV VOUT 50V/DIV BD_PRST ADIN GND GPIO 24k GPIO 5V/DIV 4260 TA01 0.1µF GND 68nF 25ms/DIV 4260 TA02 BACKPLANE PLUG-IN CARD *DIODES INC. SMBT70A 4260f 1 LTC4260 W W W AXI U U ABSOLUTE RATI GS (Notes 1, 2) Supply Voltages (VDD) ............................ – 0.3V to 100V Input Voltages SENSE ............................ VDD – 10V or – 0.3V to VDD SOURCE .......................... GATE – 5V to GATE + 0.3V BD_PRST, FB, ON, OV, UV ................... –0.3V to 12V ADR0-ADR2, TIMER, ADIN ..... –0.3V to INTVCC + 0.3V SCL, SDAI ........................................... –0.3V to 6.5V Output Voltages GPIO ................................................... –0.3V to 100V GATE (Note 3) ..................................... –0.3V to 100V ALERT, SDAO ........................................... –0.3V to 6.5V Supply Voltage (INTVCC) ......................... –0.3V to 6.2V Operating Temperature Range LTC4260C ............................................... 0°C to 70°C LTC4260I ............................................. –40°C to 85°C Storage Temperature Range GN, SW Packages ............................. – 65°C to 150°C UH Package ...................................... – 65°C to 125°C Lead Temperature (Soldering, 10 sec) GN, SW Packages Only..................................... 300°C 2 23 SOURCE NC 3 22 NC NC 3 22 NC UV 4 21 NC NC 4 21 NC OV 5 20 GPIO UV 5 20 GPIO GND 6 19 INTVCC ON 7 18 FB SCL 8 17 ADR2 SCL 8 17 ADR2 ON 7 SDAI 9 16 ADR1 SDAI 9 16 ADR1 SCL 8 15 ADR0 SDAO 10 15 ADR0 ALERT 11 14 BD_PRST ALERT 11 14 BD_PRST TIMER 12 13 ADIN TIMER 12 13 ADIN GN PACKAGE 24-LEAD PLASTIC SSOP SW PACKAGE 24-LEAD PLASTIC SO TJMAX = 125°C, θJA = 85°C/W TJMAX = 125°C, θJA = 75°C/W ORDER PART NUMBER ORDER PART NUMBER LTC4260CGN LTC4260IGN LTC4260CSW LTC4260ISW GATE NC NC 22 NC UV 4 21 NC 33 OV 5 20 GPIO GND 6 19 INTVCC 18 FB 17 ADR2 9 10 11 12 13 14 15 16 ADR1 18 FB 23 NC NC 3 ADR0 ON 7 24 NC NC 2 BD_PRST 19 INTVCC NC 1 SDAI SDAO 10 GND 6 NC 32 31 30 29 28 27 26 25 VDD ADIN 23 SOURCE SENSE 24 GATE VDD 2 TIMER SENSE 1 ALERT 24 GATE VDD 1 SDAO SENSE VDDK TOP VIEW TOP VIEW TOP VIEW SOURCE U U W PACKAGE/ORDER I FOR ATIO UH PACKAGE 32-LEAD (5mm × 5mm) PLASTIC QFN TJMAX = 125°C, θJA = 34°C/W EXPOSED PAD (PIN 33) PCB ELECTRICAL CONNECTION OPTIONAL ORDER PART NUMBER LTC4260CUH LTC4260IUH UH PART MARKING 4260 Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 48V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS General VDD Input Supply Range IDD Input Supply Current VDD(UVL) VDD Supply Undervoltage Lockout ● 8.5 ● VDD Falling ● 7 80 V 2 5 mA 7.45 7.9 V 4260f 2 LTC4260 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 48V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS INTVCC(UVL) VCC Supply Undervoltage Lockout INTVCC Falling INTVCC Internal Regulator Voltage MIN TYP MAX ● 3.4 3.8 4.2 UNITS V ● 5 5.5 6 V Gate Drive tD Turn-On Delay ● 50 100 150 ms ∆VGATE External N-Channel Gate Drive (VGATE – VSOURCE) VDD = 20V to 80V VDD = 8.5V to 20V ● ● 10 4.5 14 6 18 18 V V IGATE(UP) External N-Channel Pull-Up Current Gate Drive On, VGATE = 0V ● –14 –18 –22 µA IGATE(FST) External N-Channel Fast Pull-Down Fast Turn Off, VGATE = 48V, VSOURCE = 38V ● 400 600 1000 mA IGATE(DN) External N-Channel Pull-Down Current Gate Drive Off, VGATE = 58V, VSOURCE = 48V ● 0.7 1 1.4 mA ISOURCE SOURCE Pin Input Current SOURCE = 48V ● 200 400 600 µA VON(TH) ON Pin Threshold Voltage VON Rising ● 1.19 1.235 1.27 V ∆VON(HYST) ON Pin Hysteresis ● 60 130 200 mV ION(IN) ON Pin Input Current VON = 1.2V ● 0 ±1 µA VOV(TH) OV Pin Threshold Voltage VOV Rising ● 3.43 3.5 3.56 V ∆VOV(HYST) OV Pin Hysteresis ● 70 90 120 mV IOV(IN) OV Pin Input Current VOV = 3.5V ● 0 ±1 µA VUV(TH) UV Pin Threshold Voltage VUV Rising ● 3.43 3.5 3.56 V ∆VUV(HYST) UV Pin Hysteresis ● 310 380 440 mV IUV(IN) UV Pin Input Current VUV = 3.5V ● 0 ±2 µA VUV(RTH) UV Pin Reset Threshold Voltage VUV Falling ● 1.18 1.235 1.27 V ∆VUV(RHYST) UV Pin Reset Threshold Hysteresis ● 80 160 250 mV ∆VSENSE(TH) Current Limit Sense Voltage Threshold (VDD – VSENSE) VFB = 3.5V VFB = 0V ● ● 40 10 50 20 60 30 mV mV ISENSE(IN) SENSE Pin Input Current VSENSE = 48V ● 70 100 130 µA VFB Foldback Pin Power Good Threshold FB Rising ● 3.43 3.5 3.56 V ∆VFB(HYST) FB Pin Power Good Hysteresis ● 80 100 120 mV IFB Foldback Pin Input Current FB = 3.5V ● 0 ±2 µA VBD_PRST(TH) BD_PRST Input Threshold VBD_PRST Rising ● 1.2 1.235 1.27 V Input Pins ● 70 130 190 mV IBD_PRST BD_PRST Pullup Current BD_PRST = 0V ● –7 –10 –16 µA VGPIO(TH) GPIO Pin Input Threshold VGPIO Rising ● 1.6 1.8 2 ∆VGPIO(HYST) GPIO Pin Hysteresis VGPIO(OL) GPIO Pin Output Low Voltage IGPIO = 2mA ● 0.25 0.5 V IGPIO(IN) GPIO Pin Input Leakage Current VGPIO = 80V ● 0 ±10 µA RADIN ADIN Pin Input Resistance VADIN = 1.28V ● IADIN ADIN Pin Input Current VADIN = 2.56V ● VTIMER(H) TIMER Pin High Threshold VTIMER Rising ● VTIMER(L) TIMER Pin Low Threshold VTIMER Falling ● ITIMER(UP) TIMER Pin Pull-Up Current VTIMER = 0V ITIMER(DN) TIMER Pin Pull-Down Current VTIMER = 1.3V ITIMER(RATIO) TIMER Pin Current Ratio ITIMER(DN)/ITIMER(UP) ∆VBD_PRST(HYST) BD_PRST Hysteresis 80 2 V mV 10 MΩ 0 ±1 µA 1.2 1.235 1.28 V 0.1 0.2 0.3 V ● –80 –100 –120 µA ● 1.4 2 2.6 µA ● 1.6 2 2.7 % Timer 4260f 3 LTC4260 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 48V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS tPLH(GATE) Input High (ON) to GATE High Propagation Delay CGATE = 1pF tPHL(GATE) Input High (OV, BD_PRST), Input Low (ON, UV) to GATE Low Propagation Delay tPHL(SENSE) MIN TYP MAX UNITS ● 1 3 µs CGATE = 1pF ● 0.5 3 µs (VDD – SENSE) High to GATE Low VDD – SENSE = 200mV, CGATE = 10nF ● 0.4 1 µs Resolution (No Missing Codes) (Note 4) ● 8 Integral Nonlinearity VDD – SENSE (Note 5) SOURCE ADIN ● ● ● –2 –1.25 –1.25 0.5 0.2 0.2 2 1.25 1.25 LSB LSB LSB Offset Error VDD – SENSE SOURCE ADIN ● ● ● –1.5 –1 –1 1.5 1 1 LSB LSB LSB 1LSB Step Size VDD – SENSE (Note 6) SOURCE ADIN ● ● ● 292 392 9.8 300 400 10 308 408 10.2 µV mV mV Full-Scale Voltage VDD – SENSE (Note 7) SOURCE ADIN ● ● ● 74.9 100.4 2.51 76.8 102.4 2.560 78.7 104.4 2.61 mV V V AC Parameters ADC Conversion Rate Bits 10 Hz I2C Interface ● INTVCC – 0.6 INTVCC – 0.45 INTVCC – 0.25 ● 0.25 0.45 0.65 V ● –80 80 µA ● 1.6 VADR(H) ADR0 to ADR2 Input High Voltage Threshold VADR(L) ADR0 to ADR2 Input Low Voltage Threshold IADR(IN) ADR0 to ADR2 Input Current VSDAI,SCL(TH) SDAI, SCL Input Threshold 1.8 2 V ISDAI,SCL(IN) SDAI, SCL Input Current SCL, SDAI = 5V ● 0 ±1 µA VSDAO(OL) SDAO Output Low Voltage ISDAO = 5mA ● 0.2 0.4 V VALERT(OL) ALERT Output Low Voltage IALERT = 5mA ● 0.2 0.4 V SDAO, ALERT = 5V ● 0 ±1 µA 0.12 1.3 µs ISDAO,ALERT(IN) SDAO, ALERT Input Current ADR0 to ADR2 = 0V, 5.5V V I2C Interface Timing (Note 4) fSCL(MAX) Maximum SCL Clock Frequency tBUF(MIN) Minimum Bus Free Time Between Stop/Start Condition Operates with fSCL ≤ fSCL(MAX) tSU,STA(MIN) Minimum Repeated Start Condition Set-Up Time 30 600 ns tHD,STA(MIN) Minimum Hold Time After (Repeated) Start Condition 140 600 ns tSU,STO(MIN) Minimum Stop Condition Set-Up Time 30 600 ns tSU,DAT(MIN) Minimum Data Set-Up Time Input 30 100 ns tHD,DATI(MIN) Minimum Data Hold Time Input tHD,DATO(MIN) Minimum Data Hold Time Output tSP(MAX) Maximum Suppressed Spike Pulse Width CX SCL, SDA Input Capacitance SDAI Tied to SDAO Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. 400 kHz –100 0 ns 300 500 900 ns 50 110 250 ns 5 10 pF Note 2: All currents into pins are positive, all voltages are referenced to GND unless otherwise specified. 4260f 4 LTC4260 ELECTRICAL CHARACTERISTICS Note 3: Limits on maximum rating is defined as whichever limit occurs first. An internal clamp limits the GATE pin to a minimum of 10V above source. Driving this pin to voltages beyond the clamp may damage the device. Note 4: Guaranteed by design and not subject to test. Note 5: Integral nonlinearity is defined as the deviation of a code from a precise analog input voltage. Maximum specifications are limited by the LSB step size and the single shot measurement. Typical specificatons are measured from the 1/4, 1/2 and 3/4 areas of the quantization band. Note 6: 1LSB step size specification is guaranteed by full-scale voltage measurement and by design. Note 7: Full-scale current sense specification corresponds to code 200. Codes above 200 may be discarded by offset cancellation. U W TYPICAL PERFOR A CE CHARACTERISTICS IDD vs VDD TA = 25°C, VDD = 48V unless otherwise noted. UV Low-High Threshold vs Temperature INT VCC vs ILOAD 3.0 3.54 6 5 2.5 2.0 VDD = 12V 4 25°C INTVCC (V) IDD (mA) 85°C –40°C 3 2 1.5 1 1.0 CAUTION: DRAWING CURRENT FROM INTVCC INCREASES POWER DISSIPATION AND TJ 0 0 20 60 40 VDD (V) 80 0 100 –2 –4 –6 ILOAD (mA) –8 0.37 0.36 100 4260 G03 75 1.240 1.235 1.230 1.220 –50 100 0.16 1.225 0.35 0 25 50 TEMPERATURE (°C) ON, BD_PRST Hysteresis vs Temperature ON, BD_PRST HYSTERESIS (V) ON, BD_PRST LOW-HIGH THRESHOLD (V) UV HYSTERESIS (V) 0.38 –25 4260 G02 1.245 75 3.48 ON, BD_PRST Low-High Threshold vs Temperature 0.39 0 25 50 TEMPERATURE (°C) 3.50 4260 G18 UV Hysteresis vs Temperature –25 3.52 3.46 –50 –10 4260 G01 0.34 –50 UV LOW-HIGH THRESHOLD (V) VDD = 48V –25 0 25 50 TEMPERATURE (°C) 75 100 4260 G04 0.15 0.14 0.13 0.12 0.11 0.10 –50 –25 0 25 50 TEMPERATURE (°C) 75 100 4260 G05 4260f 5 LTC4260 U W TIMER PULL-UP CURRENT (µA) –110 –105 –100 –95 –90 –50 –25 0 25 50 TEMPERATURE (°C) 75 100 TA = 25°C, VDD = 48V unless otherwise noted. Current Limit Propagation Delay vs Sense Voltage Current Limit Sense Voltage vs FB Voltage 1000 60 CURRENT LIMIT PROPAGATION DELAY (µs) TIMER Pull-Up Current vs Temperature CURRENT LIMIT SENSE VOLTAGE (VDD – VSENSE) (mV) TYPICAL PERFOR A CE CHARACTERISTICS 50 40 30 20 10 0 0 0.5 1 2.5 1.5 2 FB VOLTAGE (V) 3 IGATE Pull Up vs Temperature 4260 G08 Gate Drive vs VDD 16 –15 75 14 VDD = 80V 12 VDD = 48V 10 8 6 VDD = 12V 4 2 0 100 GATE DRIVE (VGATE – VSOURCE) (V) GATE DRIVE (VGATE – VSOURCE) (V) IGATE PULL UP (µA) 0 50 100 150 200 250 300 350 CURRENT LIMIT SENSE VOLTAGE (VDD – VSENSE) (mV) Gate Drive vs IGATE –20 –10 –5 10 8 6 5 –20 –15 10 15 ADC TOTAL UNADJUSTED ERROR (LSB) 12 GPIO VOUT LOW (V) 12 10 8 6 4 2 0 75 100 4260 G12 35 40 2 15 13 30 ADC Total Unadjusted Error vs Code (ADIN Pin) GPIO VOUT Low vs ILOAD 14 25 20 VDD (V) 4260 G11 14 0 25 50 TEMPERATURE (°C) 12 4260 G10 16 –25 25°C –40°C IGATE (µA) Gate Drive vs Temperature 11 –50 85°C 14 4 0 4260 G09 GATE DRIVE (VGATE – VSOURCE) (V) 4 16 0 25 50 TEMPERATURE (°C) 1 4260 G07 –25 –25 10 0.1 3.5 4260 G06 –10 –50 100 1 0 –1 –2 0 10 20 40 30 ILOAD (mA) 50 60 0 64 128 192 256 CODE 4260 G13 4260 G14 4260f 6 LTC4260 U W TYPICAL PERFOR A CE CHARACTERISTICS ADC INL vs Code (ADIN Pin) ADC DNL vs Code (ADIN Pin) 0.50 0.50 1 0.25 0.25 0 –1 –2 –50 ADC DNL (LSB) 2 ADC INL (LSB) ADC FULL-SCALE ERROR (LSB) ADC Full-Scale Error vs Temperature (ADIN Pin) TA = 25°C, VDD = 48V unless otherwise noted. 0 –0.25 –0.25 –25 0 25 50 TEMPERATURE (°C) 75 100 –0.50 0 –0.50 0 64 128 192 256 3708 G15 0 64 128 192 256 CODE CODE 4260 G16 4260 G17 U U U PI FU CTIO S ADIN: ADC Input. A voltage between 0V and 2.56V applied to this pin can be measured by the onboard ADC. Tie to ground if unused. ADR0 to ADR2: Serial Bus Address Inputs. Tying these pins to ground, open or INTVCC configures one of 27 possible addresses. See Table 1 in Applications Information. ALERT: Fault Alert Output. Open-drain logic output that can be pulled to ground when a fault occurs to alert the host controller. A fault alert is enabled by the ALERT register. This device is compatible with SMBus alert protocol. See Applications Information. Tie to ground if unused. BD_PRST: Board Present Input. Ground this pin to enable the N-channel FET to turn on after 100ms debounce delay. When this pin is high, the FET is off. An internal 10µA current source pulls up this pin. Transitions on this pin will be recorded in the FAULT register. A high-to-low transition activates the logic to read the state of the ON pin and clear Faults. See Applications Information. Exposed Pad (Pin 33, UH Package): Exposed Pad may be left open or connected to device ground. FB: Foldback and Power Good Input. A resistive divider from the output voltage is tied to this pin. When the voltage at this pin drops below 3.41V, the output power is considered bad and the current limit is reduced. The power bad condition can be indicated with the GPIO pin and a power bad fault can be logged in this condition. See Applications Information. GATE: Gate Drive for External N-Channel FET. An internal 18µA current source charges the gate of the external N-channel MOSFET. A resistor and capacitor network from this pin to ground sets the turn-on rate and compensates the active current limit. During turn-off there is a 1mA pull-down current. During a short circuit or undervoltage lockout (VDD or INTVCC), a 600mA pull-down current source between GATE and SOURCE is activated. GND: Device Ground. 4260f 7 LTC4260 U U U PI FU CTIO S GPIO: General Purpose Input/Output. Open-drain logic output and logic input. Defaults to pull low to indicate power is bad. Configure according to Table 3. NC: No Connect. Unconnected pins. These pins provide extra distance between high and low voltage pins. ON: On Control Input. A rising edge turns on the external N-channel FET and a falling edge turns it off. This pin is also used to configure the state of the FET ON bit (and hence the external FET) at power up. For example if the ON pin is tied high, then the FET ON control bit (A3) will go high 100ms after power-up. Likewise if the ON pin is tied low then the part will remain off after power-up until the FET ON control bit is set high using the I2C bus. A high-to-low transition on this pin will clear faults. OV (GN/UH Packages): Overvoltage Comparator Input. Connect this pin to an external resistive divider from VDD. If the voltage at this pin rises above 3.5V, an overvoltage fault is detected and the switch turns off. Tie to GND if unused. SCL: Serial Bus Clock Input. Data at the SDA pin is shifted in or out on rising edges of SCL. This is a high impedance pin that is generally driven by an open-collector output from a master controller. An external pull-up resistor or current source is required. SDAI: Serial Bus Data Input. A high impedance input used for shifting in address, command or data bits. Normally tied to SDAO to form the SDA line. SDAO: Serial Bus Data Output. Open-drain output used for sending data back to the master controller or acknowledging a write operation. Normally tied to SDAI to form the SDA line. An external pull-up resistor or current source is required. SENSE: Current Sense Input. Connect this pin to the output of the current sense resistor. The current limit circuit controls the GATE pin to limit the sense voltage between the VDD and SENSE pins to 50mV or less depending on the voltage at the FB pin. This pin is used as an input to the 8-bit ADC. SOURCE: N-Channel MOSFET Source Connection and ADC Input. Connect this pin to the source of the external N-channel MOSFET switch. This pin also serves as the ADC input to monitor output voltage. The pin provides a return for the gate pull-down circuit and as a supply for the charge pump circuit. TIMER: Timer Input. Connect a capacitor between this pin and ground to set a 12ms/µF duration for current limit before the switch is turned off. The duration of the off time is 518ms/µF when autoretry during current limit is enabled. A minimum value of 0.1nF must be connected to this pin. UV: Undervoltage Comparator Input. Connect this pin to an external resistive divider from VDD. If the voltage at this pin falls below 3.12V, an undervoltage fault is detected and the switch turns off. Pulling this pin below 1.2V resets all faults and allows the switch to turn back on. Tie to INTVCC if unused. VDD: Supply Voltage and Current Sense Input. This pin has an undervoltage lockout threshold of 7.45V. INTVCC: Internal Low Voltage Supply Decoupling Output. Connect a 0.1µF capacitor from this pin to ground. This pin can be used to drive the other pins to logic high and has an undervoltage lockout threshold of 3.8V. VDDK (UH Package): Same as VDD. Connect this pin to VDD. VDDK tied to VDD internally with 18Ω. 4260f 8 LTC4260 W FU CTIO AL DIAGRA U U UH ONLY VDDK VDD FB SENSE 18Ω 3.5V INTERNAL POWER + 20mV TO 50mV UVS UV UV – +– + CHARGE PUMP AND GATE DRIVER – CS + GATE SOURCE FOLDBACK OV 2V + GN/UH ONLY OVS OV 3.5V + – PWRGD FET ON PG – 3.5V 1.235V – + RST RESET – INTVCC 10µA GP LOGIC 1.235V GPIO + + – BOARD PRESENT 1.8V BP BD_PRST – + 0.2V INTVCC TM1 – ON + TIMER ON 1.235V 100µA ONS 2µA + – VDD TM2 – 1.235V VDD – UVLO1 7.45V INTVCC 5.5V GEN VDD UVLO + + UVLO2 VCC UVLO – 3.8V VDD – SENSE SDAI 8 SDAO ADIN A/D CONVERTER SOURCE I2C SCL ALERT I2C ADDR 5 1 OF 27 ADR0 ADR1 ADR2 GND EXPOSED PAD 4260 BD UH ONLY 4260f 9 LTC4260 WU W TI I G DIAGRA SDAI/SDAO tSU, DAT tSU, STA tHD, DATO, tHD, DATI tSP tHD, STA tSP tBUF tSU, STO 4260 TD01 SCL tHD, STA START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION U OPERATIO The Functional Diagram displays the main functional areas of this device. The LTC4260 is designed to turn a board’s supply voltage on and off in a controlled manner, allowing the board to be safely inserted or removed from a live backplane. During normal operation, the charge pump and gate driver turn on the external N-channel pass FET’s gate to pass power to the load. The gate driver uses a charge pump that derives its power from the SOURCE pin. When the SOURCE pin is at ground, the charge pump is powered from an internal 12V supply derived from VDD. This results in a 200µA current load on the SOURCE pin when the gate is up. Also included in the gate driver is an internal 15V gate-to-source clamp. The current sense (CS) amplifier monitors the load current using the difference between the VDD and SENSE pin voltage. The CS amplifier limits the current in the load by reducing the GATE-to-SOURCE voltage in an active control loop. The CS amplifier requires 100µA input bias current from both the VDD and the SENSE pins. A short circuit on the output to ground causes significant power dissipation during active current limiting. To limit this power, the foldback amplifier reduces the current limit value from 50mV to 20mV (referred to the VDD minus SENSE voltage) in a linear manner as the FB pin drops below 2V (see Typical Performance curves). If an overcurrent condition persists, the TIMER pin ramps up with a 100µA current source until the pin voltage exceeds 1.2V (comparator TM2). This indicates to the logic that it is time to turn off the pass FET to prevent overheating. At this point the TIMER pin ramps down using the 2µA current source until the voltage drops below 0.2V (comparator TM1) which tells the logic that the pass transistor has cooled and it is safe to turn it on again. The output voltage is monitored using the FB pin and the PG comparator to determine if the power is available for the load. The power good condition is signalled by the GPIO pin using an open-drain pull-down transistor. The GPIO pin can also be used as a general purpose input (GP comparator) or output pin. The Functional Diagram shows the monitoring blocks of the LTC4260. The group of comparators on the left side includes the UV, OV, RST, BP and ON comparators. These comparators are used to determine if the external conditions are valid prior to turning on the FET. But first the two undervoltage lockout circuits UVLO1 and UVLO2 must validate the input supply and the internally generated 5.5V supply (INTVCC) and generate the power up initialization to the logic circuits. Included in the LTC4260 is an 8-bit A/D converter. The converter has a 3-input mux to select between the ADIN pin, the SOURCE pin and the VDD – SENSE voltage. An I2C interface is provided to read the A/D registers. It also allows the host to poll the device and determine if faults have occurred. If the ALERT line is used as an interrupt, the host can respond to a fault in real time. The typical SDA line is divided into an SDAI (input) and SDAO (output). This simplifies applications using an optoisolator driven directly from the SDAO output. The I2C device address is decoded using the ADR0, ADR1 and ADR2 pins. These inputs have three states each that decode into a total of 27 device addresses. 4260f 10 LTC4260 U W U U APPLICATIO S I FOR ATIO The typical LTC4260 application is in a high availability system that uses a positive voltage supply to distribute power to individual cards. The device measures card voltages and currents and records past and present fault conditions. The system queries each LTC4260 over the I2C periodically and reads the stored information. The basic LTC4260 application circuit is shown in Figure 1. External component selection is discussed in detail in the Design Example section. Turn-On Sequence The power supply on a board is controlled by placing an external N-channel pass transistor (Q1) in the power path. Note that sense resistor (RS) detects current and capacitor C1 controls the GATE slew rate. Resistor R6 compensates the current control loop while R5 prevents high frequency oscillations in Q1. Resistors R1, R2 and R3 provide undervoltage and overvoltage sensing. Several conditions must be present before the external switch can be turned on. First the external supply VDD must exceed its undervoltage lockout level. Next the internally generated supply INTVCC must cross its 4.5V undervoltage threshold. This generates a 60µs to 120µs power-on-reset pulse. During reset the fault registers are cleared and the control registers are set or cleared as described in the register section. After the power-on-reset pulse, the LTC4260 will go through the following turn-on sequence. First, the UV and OV pins must indicate that the input power is within the acceptable range and the BD_PRST pin must be pulled low. All of these conditions must be satisfied for duration of 100ms to ensure that any contact bounce during insertion has ended. When these initial conditions are satisfied, the ON pin is checked. If it is high, the external switch turns on. If it is low, the external switch turns on when the ON pin is brought high or if a serial bus turn-on command is received. The switch is turned on by charging up the GATE with a 18µA current source (Figure 2). The voltage at the GATE pin rises with a slope equal to 18µA/C1 and the supply inrush current is set at: IINRUSH = When the GATE voltage reaches the FET threshold voltage, the switch begins to turn on and the SOURCE voltage follows the GATE voltage as it increases. RS 0.010Ω VIN 48V CONNECTOR 1 CONNECTOR 2 Z1* SMBT70A CF 0.1µF R1 49.9k 1% R3 2.67k 1% SDA SCL ALERT 5 7 9 10 8 11 BACKPLANE PLUG-IN CARD *DIODES, INC R7 43.5k 1% R6 100k R8 3.57k 1% C1 6.8nF 1 24 SENSE GATE 4 2 23 UV VDD SOURCE FB OV ON ADIN SDAI GPIO LTC4260GN SDA0 BD_PRST SCL TIMER ALERT INTVCC ADR0 ADR1 ADR2 GND 19 GND Q1 FDB3632 R5 10Ω R2 1.74k 1% CL • 18 µA C1 15 C3 0.1µF 16 17 6 + VOUT 48V CL 330µF R4 100k 18 13 20 14 12 CT 68nF 4260 F01 NC Figure 1. 5A, 48V Card Resident Application 4260f 11 LTC4260 U W U U APPLICATIO S I FOR ATIO VDD + 13V GATE SLOPE = 18µA/C1 VOUT VDD t1 t2 4260 F02 Figure 2. Supply Turn-On As the SOURCE voltage rises, so will the FB pin which is monitoring it. If the voltage across the current sense resistor RS gets too high, the inrush current will then be limited by the internal current limit circuitry. Once the FB pin crosses its 3.5V threshold, the GPIO pin, in its default configuration, will cease to pull low and indicate that the power is now good. Turn-Off Sequence The switch can be turned off by a variety of conditions. A normal turn-off is initiated by the ON pin going low or a serial bus turn-off command. Additionally, several fault conditions will turn off the switch. These include an input overvoltage (OV pin), input undervoltage (UV pin), overcurrent circuit breaker (SENSE pin) or BD_PRST going high. Writing a logic one into the UV, OV or overcurrent fault bits will also turn off the switch if their autoretry bits are set to false. Normally the switch is turned off with a 1mA current pulling down the GATE pin to ground. With the switch turned off, the SOURCE voltage drops and when the FB pin crosses below its threshold, GPIO pulls low to indicate that the output power is no longer good. If the VDD pin falls below 7.5V for greater than 5µs or INTVCC drops below 3.8V for greater than 1µs, a fast shutdown of the switch is initiated. The GATE pin is pulled down with a 600mA current to the SOURCE pin. Overcurrent Fault The LTC4260 features an adjustable current limit with foldback that protects against short circuits or excessive load current. To protect against excessive power dissipation in the switch during active current limit, the available current is reduced as a function of the output voltage sensed by the FB pin. The device also features a variable overcurrent response time. A graph in the Typical Performance curves shows the delay from a voltage step at the SENSE pin until the GATE voltage starts falling, as a function of overdrive. An overcurrent fault occurs when the current limit circuitry has been engaged for longer than the time-out delay set by the TIMER pin. Current limiting begins when the current sense voltage between the VDD and SENSE pins reaches 20mV to 50mV (depending on the foldback). The GATE pin is then brought down with a 600mA GATE-to-SOURCE current. The voltage on the GATE is regulated in order to limit the current sense voltage to less than 50mV. At this point, a circuit breaker time delay starts by charging the external timing capacitor from the TIMER pin with a 100µA pull-up current. If the TIMER pin reaches its 1.2V threshold, the external switch turns off (with a 1mA current from GATE to ground). The overcurrent present bit, C2, and the overcurrent fault bit, D2, are set at this time. The circuit breaker time delay is given by: tCB = CT • 12 [ms/µF] After the switch is turned off, the TIMER pin begins discharging the timing capacitor with a 2µA pull-down current. When the TIMER pin reaches its 0.2V threshold, the overcurrent present bit, C2, is cleared, and the switch will be allowed to turn on again if the overcurrent fault has been cleared. However, if the overcurrent autoretry bit, A2, has been set then the switch turns on again automatically (without resetting the overcurrent fault). Use a minimum value of 0.1nF for CT. The waveform in Figure 3 shows how the output latches off following a short circuit. The drop across the sense resistor is held at 20mV as the timer ramps up. 4260f 12 LTC4260 U W U U APPLICATIO S I FOR ATIO undervoltage autoretry has been disabled by clearing bit A1. When power is applied to the device, if UV is below its 3.12V threshold after INTVCC crosses its 4.5V undervoltage lockout threshold, an undervoltage fault will be logged in the fault register. VOUT 50V/DIV IOUT 5A/DIV ∆VGATE 10V/DIV Board Present Change of State TIMER 2V/DIV 100µs/DIV 4260 F03 Figure 3. Short-Circuit Waveforms During a short circuit, if the current limit sense voltage exceeds 150mV, the active current limit enters a high current protection mode that immediately turns off the output transistor by pulling the GATE-to-SOURCE voltage to zero. Current in the output transistor drops from tens of amps to zero in a few hundred nanoseconds. The input voltage will drop during the high current and then spike upwards due to parasitic inductances when the FET shuts off (see Supply Transients). Following this event, the part may turn on again after a delay (typically the 100ms normal turn-on delay if the input voltage drops below the UVLO threshold) and enters active current limit before shutting off. Overvoltage Fault An overvoltage fault occurs when the OV pin rises above its 3.5V threshold. This shuts off the switch immediately (with a 1mA current from GATE to ground) and sets the overvoltage present bit, C0, and the overvoltage fault bit D0. If the OV pin subsequently falls back below the threshold for 100ms, the switch will be allowed to turn on again unless the overvoltage autoretry has been disabled by clearing bit A0. Undervoltage Fault An undervoltage fault occurs when the UV pin falls below its 3.12V threshold. This turns off the switch immediately (with a 1mA current from GATE to ground) and sets the undervoltage present bit, C1, and the undervoltage fault bit D1. If the UV pin subsequently rises above the threshold for 100ms, the switch will turn on again unless the Whenever the BD_PRST pin toggles, bit D4 is set to indicate a change of state. When the BD_PRST pin goes high, indicating board removal, the switch turns off immediately (with a 1mA current from GATE to ground) and clears the board present bit, C4. If the BD_PRST pin is pulled low, indicating a board insertion, all fault bits except D4 will be cleared and the board present bit, C4, is set. If the BD_PRST pin remains low for 100ms the state of the ON pin will be captured in the FET On Control bit A3. This turns the switch on if the ON pin is tied high. There is an internal 10µA pull-up current source on the BD_PRST pin. If the system shuts down due to a fault, it may be desirable to restart the system simply by removing and reinserting a load card. In cases where the LTC4260 and the switch reside on a backplane or midplane and the load resides on a plug-in card, the BD_PRST pin can be used to detect when the plug-in card is removed (see Figure 4). Once the plug-in card is reinserted the fault register is cleared (except for D4). After 100ms the state of the ON pin is latched into bit A3 of the control register. At this point the system will start up again. If a connection sense on the plug-in card is driving the BD_PRST pin, the insertion or removal of the card may cause the pin voltage to bounce. This will result in clearing the fault register when the card is removed. The pin can be debounced using a filter capacitor, CBD_PRST, on the BD_PRST pin as shown in Figure 4. The filter time is given by: tFILTER = CBD_PRST • 123 [ms/µF] FET Short Fault A FET short fault will be reported if the data converter measures a current sense voltage greater than or equal to 2mV while the FET is turned off. This condition sets the FET short present bit, C5, and the FET short fault bit D5. 4260f 13 LTC4260 U W U U APPLICATIO S I FOR ATIO OUT 23 LTC4260 SOURCE 10µA BD_PRST 14 + LOAD CBD_PRST – 1.235V Resetting Faults GND 6 4260 F04 MOTHERBOARD Once the ALERT signal has been released for one fault, it will not be pulled low again until the FAULT register indicates a different fault has occurred or the original fault is cleared and it occurs again. Note that this means repeated or continuing faults will not generate alerts until the associated FAULT register bit has been cleared. CONNECTOR PLUG-IN CARD Figure 4. Plug-In Card Insertion/Removal Power Bad Fault A power bad fault will be reported if the FB pin drops below its 3.41V threshold while the FET is on. This pulls the GPIO pin low immediately, when configured as PWRGD, and sets the power bad present bit, C3, and the power bad fault bit D3. A circuit will prevent a power bad fault if the GATEto-SOURCE voltage is low, eliminating false power bad faults during power-up or power-down. If the FB pin subsequently rises back above the threshold, the GPIO pin will return to a high impedance state and bit C3 will be cleared. Fault Alerts When any of the fault bits in FAULT register D are set, an optional I2C bus alert can be generated by setting the appropriate bit in the ALERT register B. This allows only selected faults to generate alerts. At power-up the default state is to not alert on faults. If an alert is enabled, the corresponding fault will cause the ALERT pin to pull low. After the bus master controller broadcasts the Alert Response Address, the LTC4260 responds with its address on the SDA line and releases ALERT as shown in Figure 11. If there is a collision between two LTC4260s responding with their addresses simultaneously, then the device with the lower address wins arbitration and responds first. The ALERT line will also be released if the device is addressed by the bus master. Faults are reset with any of the following conditions. First, a serial bus command writing zeros to the FAULT register D will clear the associated faults. Second, the entire FAULT register is cleared when the switch is turned off by either the ON pin or bit A3 going from high to low, or if the UV pin is brought below its 1.23V reset threshold, or if INTVCC falls below its 3.8V undervoltage lockout threshold. Finally, when BD_PRST is brought from high to low, only FAULT bits D0-D3 and D5 are cleared, the bit D4 that indicates a BD_PRST change of state will be set. Faults that are still present (as indicated in the STATUS Register C) cannot be cleared. The FAULT register will not be cleared when autoretrying. When autoretry is disabled the existence of a D0, D1 or D2 fault keeps the switch off. As soon as the fault is cleared, the switch will turn on. If autoretry is enabled, then a high value in C0, C1 or C2 will hold the switch off and the FAULT register is ignored. Subsequently, when the C0, C1 and C2 bits are cleared, the switch is allowed to turn on again Data Converter The LTC4260 incorporates an 8-bit data converter that continuously monitors three different voltages. The SOURCE pin uses a 1/40 resistive divider to monitor a fullscale voltage of 102.4V with 0.4V resolution (divider converts 102.4V to 2.56V). The ADIN pin is monitored with a 2.56V full scale and 10mV resolution, and the voltage between the VDD and SENSE pins is monitored with a 76.8mV full scale and 300µV resolution. The results from each conversion are stored in registers E, F and G and are updated 10 times per second. Setting CONTROL register bit A5 invokes a test mode that halts the data converter updates so that registers E, F and G can be written to and read from for software testing. 4260f 14 LTC4260 U W U U APPLICATIO S I FOR ATIO Gate Pin Voltage Supply Transient Protection A curve of gate drive vs VDD is shown in the Typical Performance curves. At the minimum input supply voltage of 8.5V, the minimum gate drive voltage is 4.5V. When the input supply voltage is higher than 20V, the gate drive is at least 10V and a regular N-FET can be used. In applications over a 8.5V to 20V range, a logic level N-FET must be used to maintain adequate gate enhancement. The GATE pin is clamped at a typical value of 15V above the SOURCE pin. The LTC4260 is 100% tested and guaranteed to be safe from damage with supply voltages up to 100V. However, spikes above 100V may damage the part. During a shortcircuit condition, the large change in currents flowing through the power supply traces can cause inductive voltage spikes which could exceed 100V. To minimize the spikes, the power trace inductance should be minimized by using wider traces or heavier trace plating. Adding a snubber circuit will dampen the voltage spikes. It is built using a 100Ω resistor in series with a 0.1µF capacitor between VDD and GND. A surge suppressor, Z1 in Figure 1, at the input will clamp the voltage spikes. Configuring the GPIO Pin Table 3 describes the possible states of the GPIO pin using the control register bits A6 and A7. At power-up, the default state is for the GPIO pin to go high impedance when power is good (FB pin greater than 3.5V). Other uses for the GPIO pin are to pull down when power is good, a general purpose output and a general purpose input. Compensating the Active Current Loop The active current limit circuit is compensated using the resistor R6 and the slew rate capacitor C1. The value for C1 is calculated to limit the inrush current. The suggested value for R6 is 100k. This value should work for most pass FETs (Q1). If the gate capacitance of Q1 is very small then the best method to compensate the loop is to add a ≈10nF capacitor between the GATE and SOURCE terminals. Supply Transients The LTC4260 is designed to ride through supply transients caused by load steps. If there is a shorted load and the parasitic inductance back to the supply is greater than 0.5µH, there is a chance that the supply could collapse before the active current limit circuit brings down the GATE pin. In this case the undervoltage monitors turn off the pass FET. The undervoltage lockout circuit has a 5µs filter time after VDD drops below 7.5V. The UV pin reacts in 2µs to shut the GATE off, but it is recommended to add a filter capacitor CF to prevent unwanted shutdown caused by short transient. Eventually either the UV pin or the undervoltage lockout responds to bring the current under control before the supply completely collapses. Design Example As a design example, take the following specifications: VIN = 48V, IMAX = 5A, IINRUSH = 1A, CL= 330µF, VUVON = 43V, VUVOFF = 38.5V, VOVOFF = 70V, VPWRGDUP = 46V, VPWRGDDN = 45V and I2CADDRESS = 1010011. The selection of the sense resistor, RS, is set by the overcurrent threshold of 50mV: RS = 50mV 50mV = = 0.010Ω IMAX 5A The FET should be sized to handle the power dissipation during the inrush charging of the output capacitor COUT. The method used to determine the power is the principle: EC = Energy in CL= Energy in Q1 Thus: EC = 1/2 CV2 = 1/2(0.33mF)(48V)2 = 0.38J Calculate the time it takes to charge up COUT: tCHARGUP = CL • VIN 330µF • 48 V = = 16ms IINRUSH 1A The average power dissipated in the FET: PDISS = EC tCHARGUP = 0.38J ≅ 24W 16ms 4260f 15 LTC4260 U W U U APPLICATIO S I FOR ATIO The SOA (safe operating area) curves of candidate FETs must be evaluated to ensure that the heat capacity of the package can stand 24W for 16ms. The SOA curves of the Fairchild FDB3632 provide for 1A at 50V (50W) for 10ms, satisfying the requirement. The inrush current is set to 1A using C1: C1 = CL IGATE(UP) 18µA = 0.33mF = 5.9nF IINRUSH 1A Default values of R5 = 10Ω and R6 = 100k are chosen as discussed previously. The power dissipated in the FET during overcurrent must be limited. The active current limit uses a timer to prevent excessive energy dissipation in the FET. The worst-case power occurs when the voltage versus current profile of the foldback current limit is at the maximum. This occurs when the current is 5A and the voltage is 1/2 of the 48V or 24V. See the Current Limit Sense Voltage vs FB Voltage in the Typical Performance curves to view this profile. In order to survive 120W, the FET SOA curve dictates the maximum time at this power level. This particular FET allows 300W at 1ms or less. Therefore, it is acceptable to set the current limit timeout using CT to be 0.81ms: Layout Considerations To achieve accurate current sensing, a Kelvin connection is recommended. The minimum trace width for 1oz copper foil is 0.02" per amp to make sure the trace stays at a reasonable temperature. Using 0.03" per amp or wider is recommended. Note that 1oz copper exhibits a sheet resistance of about 530µΩ/. Small resistances add up quickly in high current applications. To improve noise immunity, put the resistive divider to the UV, OV and FB pins close to the device and keep traces to VDD and GND short. It is also important to put C3, the bypass capacitor for the INTVCC pin, as close as possible between INTVCC and GND. A 0.1µF capacitor from the UV pin (and OV pin through resistor R2) to GND also helps reject supply noise. Figure 5 shows a layout that addresses these issues. Note that a surge suppressor, Z1, is placed between supply and ground using wide traces. VIN SENSE RESISTOR RS ILOAD SENSE R1 VDD LTC4260 CF R2 Z1 0.81ms CT = = 68nF 12 [ms/µF ] UV OV R3 GND C3 INTVCC FB R8 Note the minimum value for CT is 0.1nF. Choose R1, R2, R3, R7 and R8 for the UV, OV and PG threshold voltages: VOVRISING = 71.2V, VOVFALLING = 69.44V (using VOV(TH) = 3.5V rising and 3.41V falling) VUVRISING = 43V, VUVFALLING = 38.5V, (using VUV(TH) = 3.5V rising and 3.12V falling) VPGRISING = 46.14V, VPGFALLING = 45V, (using VFB = 3.5V rising and 3.411V falling) 4260 F05 GND ILOAD Figure 5. Recommended Layout for R1, R2, R3, R8, CF, C3, Z1 and RS In addition a 0.1µF ceramic bypass capacitor is placed on the INTVCC pin. The complete circuit is shown in Figure 1. 4260f 16 LTC4260 U W U U APPLICATIO S I FOR ATIO Digital Interface Acknowledge The LTC4260 communicates with a bus master using a 2-wire interface compatible with the I2C bus and the SMBus, an I2C extension for low power devices. The acknowledge signal is used for handshaking between the transmitter and the receiver to indicate that the last byte of data was received. The transmitter always releases the SDA line during the acknowledge clock pulse. When the slave is the receiver, it must pull down the SDA line so that it remains LOW during this pulse to acknowledge receipt of the data. If the slave fails to acknowledge by leaving SDA HIGH, then the master can abort the transmission by generating a STOP condition. When the master is receiving data from the slave, the master must pull down the SDA line during the clock pulse to indicate receipt of the data. After the last byte has been received the master will leave the SDA line HIGH (not acknowledge) and issue a STOP condition to terminate the transmission. The LTC4260 is a read-write slave device and supports SMBus bus Read Byte, Write Byte, Read Word and Write Word commands. The second word in a Read Word command will be identical to the first word. The second word in a Write Word command is ignored. The data formats for these commands are shown in Figures 7 to10. Using Optoisolators with SDA The LTC4260 separates the SDA line into SDAI and SDAO. If optoisolators are not used then tie SDAI and SDAO together to construct a normal SDA line. When using optoisolators connect the SDAI to the output of the incoming opto and connect the SDAO to the input of the outgoing opto (see Figure 13). START and STOP Conditions When the bus is idle, both SCL and SDA must be high. A bus master signals the beginning of a transmission with a START condition by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission. I2C Device Addressing Twenty-seven distinct bus address are configurable using the three-state ADR0-ADR2 pins. Table 1 shows the correspondence between pin states and addresses. Note that address bits B7 and B6 are internally configured to 10. In addition, the LTC4260 will respond to two special addresses. Address (1011 111)b is a mass write used to write to all LTC4260, regardless of their individual address settings. The mass write can be masked by setting register bit A4 to zero. Address (0001 100)b is the SMBus Alert Response Address. If the LTC4260 is pulling low on the ALERT pin, it will acknowledge this address using the SMBus Alert Response Protocol. Write Protocol The master begins communication with a START condition followed by the seven bit slave address and the R/W bit set to zero. The addressed LTC4260 acknowledges this and then the master sends a command byte which indicates which internal register the master wishes to write. The LTC4260 acknowledges this and then latches the lower three bits of the command byte into its internal Register Address pointer. The master then delivers the data byte and the LTC4260 acknowledges once more and latches the data into its internal register. The transmission is ended when the master sends a STOP condition. If the master continues sending a second data byte, as in a Write Word command, the second data byte will be acknowledged by the LTC4260 but ignored. Read Protocol The master begins a read operation with a START condition followed by the seven bit slave address and the R/W bit set to zero. The addressed LTC4260 acknowledges this and then the master sends a command byte that indicates which internal register the master wishes to read. The LTC4260 acknowledges this and then latches the lower three bits of the command byte into its internal Register Address pointer. The master then sends a repeated START condition followed by the same seven bit address with the 4260f 17 LTC4260 U W U U APPLICATIO S I FOR ATIO R/W bit now set to one. The LTC4260 acknowledges and sends the contents of the requested register. The transmission is ended when the master sends a STOP condition. If the master acknowledges the transmitted data byte, as in a Read Word command, the LTC4260 will repeat the requested register as the second data byte. Note that the Register Address pointer is not cleared at the end of the transaction. Thus the Receive Byte protocol can be used to repeatedly read a specific register. Alert Response Protocol The LTC4260 implements the SMBus Alert Response Protocol as shown in Figure 11. If enabled to do so through the ALERT register B, the LTC4260 will respond to faults by pulling the ALERT pin low. Multiple LTC4260s can share a common ALERT line and the protocol allows a master to determine which LTC4260s are pulling the line low. The master begins by sending a START bit followed SDA a6 - a0 SCL 1-7 by the special Alert Response Address (0001 100)b with the R/W bit set to one. Any LTC4260 that is pulling its ALERT pin low will acknowledge and begin sending back its individual slave address. An arbitration scheme ensures that the LTC4260 with the lowest address will have priority; all others will abort their response. The successful responder will then release its ALERT pin while any others will continue to hold their ALERT pins low. Polling may also be used to search for any LTC4260 that have detected faults. Any LTC4260 pulling its ALERT pin low will also release it if it is individually addressed during a read or write transaction. The ALERT signal will not be pulled low again until the FAULT register indicates a different fault has occurred or the original fault is cleared and it occurs again. Note that this means repeated or continuing faults will not generate alerts until the associated FAULT register bit has been cleared. b7 - b0 8 9 1-7 b7 - b0 8 9 1-7 8 9 S START CONDITION P ADDRESS R/W ACK DATA ACK DATA ACK STOP CONDITION 4260 F06 Figure 6. Data Transfer Over I2C or SMBus 4260f 18 LTC4260 U W U U APPLICATIO S I FOR ATIO S ADDRESS W A 1 0 a4:a0 0 0 COMMAND X X X X X b2:b0 FROM MASTER TO SLAVE A DATA A P 0 b7:b0 0 A: ACKNOWLEDGE (LOW) A: NOT ACKNOWLEDGE (HIGH) R: READ BIT (HIGH) W: WRITE BIT (LOW) S: START CONDITION P: STOP CONDITION FROM SLAVE TO MASTER 4260 F07 Figure 7. LTC4260 Serial Bus SDA Write Byte Protocol S ADDRESS W A 1 0 a4:a0 0 0 COMMAND A DATA A DATA X X X X X b2:b0 0 b7:b0 0 XXXXXXXX A P 0 4260 F08 Figure 8. LTC4260 Serial Bus SDA Write Word Protocol S ADDRESS W A 1 0 a4:a0 0 0 COMMAND X X X X X b2:b0 A S ADDRESS R A DATA A P 0 1 0 a4:a0 1 0 b7:b0 1 4260 F09 Figure 9. LTC4260 Serial Bus SDA Read Byte Protocol S ADDRESS W A 1 0 a4:a0 0 0 COMMAND X X X X X b2:b0 A S ADDRESS R A DATA A DATA A P 0 1 0 a4:a0 1 0 b7:b0 0 b7:b0 1 4260 F10 Figure 10. LTC4260 Serial Bus SDA Read Word Protocol ALERT S RESPONSE R A ADDRESS DEVICE ADDRESS A P 0001100 1 0 1 0 a4:a0 1 4260 F11 Figure 11. LTC4260 Serial Bus SDA Alert Response Protocol 4260f 19 LTC4260 U W U U APPLICATIO S I FOR ATIO Table 1. LTC4260 I2C Device Addressing DESCRIPTION HEX DEVICE ADDRESS h LTC4260 ADDRESS PINS BINARY DEVICE ADDRESS 6 5 4 3 2 1 0 R/W ADR2 ADR1 ADR0 Mass Write BE 1 0 1 1 1 1 1 0 X X X Alert Response 19 0 0 0 1 1 0 0 1 X X X 0 80 1 0 0 0 0 0 0 X L NC L 1 82 1 0 0 0 0 0 1 X L H NC 2 84 1 0 0 0 0 1 0 X L NC NC 3 86 1 0 0 0 0 1 1 X L NC H 4 88 1 0 0 0 1 0 0 X L L L 5 8A 1 0 0 0 1 0 1 X L H H 6 8C 1 0 0 0 1 1 0 X L L NC 7 8E 1 0 0 0 1 1 1 X L L H 8 90 1 0 0 1 0 0 0 X NC NC L 9 92 1 0 0 1 0 0 1 X NC H NC 10 94 1 0 0 1 0 1 0 X NC NC NC 11 96 1 0 0 1 0 1 1 X NC NC H 12 98 1 0 0 1 1 0 0 X NC L L 13 9A 1 0 0 1 1 0 1 X NC H H 14 9C 1 0 0 1 1 1 0 X NC L NC 15 9E 1 0 0 1 1 1 1 X NC L H 16 A0 1 0 1 0 0 0 0 X H NC L 17 A2 1 0 1 0 0 0 1 X H H NC 18 A4 1 0 1 0 0 1 0 X H NC NC 19 A6 1 0 1 0 0 1 1 X H NC H 20 A8 1 0 1 0 1 0 0 X H L L 21 AA 1 0 1 0 1 0 1 X H H H 22 AC 1 0 1 0 1 1 0 X H L NC 23 AE 1 0 1 0 1 1 1 X H L H 24 B0 1 0 1 1 0 0 0 X L H L 25 B2 1 0 1 1 0 0 1 X NC H L 26 B4 1 0 1 1 0 1 0 X H H L 4260f 20 LTC4260 U W U U APPLICATIO S I FOR ATIO Table 2. LTC4260 Register Addresses and Contents REGISTER ADDRESS* REGISTER NAME 00h CONTROL (A) R/W Controls Whether the Part Retries After Faults, Set the Switch State 01h ALERT (B) R/W Controls Whether the ALERT Pin is Pulled Low After a Fault is Logged in the Fault Register READ/WRITE 02h STATUS (C) R 03h FAULT (D) R/W 04h SENSE (E) R/W** DESCRIPTION System Status Information Fault Log ADC Current Sense Voltage Data 05h SOURCE (F) R/W** ADC SOURCE Voltage Data 06h, 07h ADIN (G) R/W** ADC ADIN Voltage Data *Register address MSBs b7-b3 are ignored. **Writable if bit A5 set. Table 3. CONTROL Register A (00h)—Read/Write BIT NAME OPERATION A7:6 GPIO Configure Configures Behavior of GPIO Pin FUNCTION A6 A7 GPIO PIN Power Good (Default) 0 0 GPIO = C3 Power Bad 0 1 GPIO = C3 General Purpose Output 1 0 GPIO = B6 General Purpose Input 1 1 GPIO = Hi-Z A5 Test Mode Enable Test Mode Halts ADC Operation and Enables Writes to ADC Registers 1 = Enable Test Mode, 0 = Disable Test Mode (Default) A4 Mass Write Enable Enables Mass Write Using Address (1011 111)b 1 = Enable Mass Write (Default), 0 = Disable Mass Write A3 FET On Control Turns FET On and Off 1 = Turn FET On, 0 = Turn FET Off. Defaults to ON Pin State at End of Debounce Delay A2 Overcurrent Autoretry Enables Autoretry After an Overcurrent Fault 1 = Retry Enabled, 0 = Retry Disabled (Default) A1 Undervoltage Autoretry Enables Autoretry After an Undervoltage Fault 1 = Retry Enabled (Default), 0 = Retry Disabled A0 Overvoltage Autoretry Enables Autoretry After an Overvoltage Fault 1 = Retry Enabled (Default), 0 = Retry Disabled 4260f 21 LTC4260 U W U U APPLICATIO S I FOR ATIO Table 4. ALERT Register B (01h)—Read/Write BIT NAME OPERATION B7 Reserved Not Used B6 GPIO Output Output Data Bit to GPIO Pin When Configured as Output. Defaults to 0 B5 FET Short Alert Enables Alert for FET Short Condition 1 = Enable Alert, 0 = Disable Alert (Default) B4 BD_PRST State Change Alert Enables Alert When BD_PRST Changes State 1 = Enable Alert, 0 = Disable Alert (Default) B3 Power Bad Alert Enables Alert when Output Power is Bad 1 = Enable Alert, 0 = Disable Alert (Default) B2 Overcurrent Alert Enables Alert for Overcurrent Condition 1 = Enable Alert, 0 = Disable Alert (Default) B1 Undervoltage Alert Enables Alert for Undervoltage Condition 1 = Enable Alert, 0 = Disable Alert (Default) B0 Overvoltage Alert Enables Alert for Overvoltage Condition 1 = Enable Alert, 0 = Disable Alert (Default) Table 5. STATUS Register C (02h)—Read Only BIT NAME OPERATION C7 FET On Indicates State of FET 1 = FET On, 0 = FET Off C6 GPIO Input State of the GPIO Pin 1 = GPIO High, 0 = GPIO Low C5 FET Short Present Indicates Potential FET Short if Current Sense Voltage Exceeds 2mV While FET is Off 1 = FET is Shorted, 0 = FET is Not Shorted C4 Board Present Indicates if a Board is Present When BD_PRST is Low 1 = BD_PRST Pin Low, 0 = BD_PRST Pin High C3 Power Bad Indicates Power is Bad When FB is Low 1 = FB Low, 0 = FB High C2 Overcurrent Indicates Overcurrent Condition During Cool Down Cycle 1 = Overcurrent, 0 = Not Overcurrent C1 Undervoltage Indicates Input Undervoltage When UV is Low 1 = UV Low, 0 = UV High C0 Overvoltage Indicates Input Overvoltage When OV is High 1 = OV High, 0 = OV Low 4260f 22 LTC4260 U W U U APPLICATIO S I FOR ATIO Table 6. FAULT Register D (03h)—Read/Write BIT NAME D7:6 Reserved OPERATION D5 FET Short Fault Occurred Indicates Potential FET Short was Detected When Measured Current Sense Voltage Exceeded 2mV While FET was Off 1 = FET was Shorted, 0 = FET is Good D4 Board Present Changes State Indicates that a Board was Inserted or Extracted When BD_PRST Changed State 1 = BD_PRST Changed State, 0 = BD_PRST Unchanged D3 Power Bad Fault Occurred Indicates Power was Bad When FB Went Low 1 = FB was Low, 0 = FB was High D2 Overcurrent Fault Occurred Indicates Overcurrent Fault Occurred 1 = Overcurrent Fault Occurred, 0 = No Overcurrent Faults D1 Undervoltage Fault Occurred Indicates Input Undervoltage Fault Occurred When UV Went Low 1 = UV was Low, 0 = UV was High D0 Overvoltage Fault Occurred Indicates Input Overvoltage Fault Occurred When OV Went High 1 = OV was High, 0 = OV was Low Table 7. SENSE Register E (04h)—Read/Write BIT NAME OPERATION E7:0 SENSE Voltage Data VDD-SENSE Current Sense Voltage Data. 8-Bit Data with 300µV LSB and 76.8mV Full Scale Table 8. SOURCE Register F (05h)—Read/Write BIT NAME OPERATION F7:0 SOURCE Voltage Data SOURCE Pin Voltage Data. 8-Bit Data with 400mV LSB and 102.4V Full Scale Table 9. ADIN Register G (06h)—Read/Write BIT NAME OPERATION G7:0 ADIN Voltage Data ADIN Pin Voltage Data. 8-Bit Data with 10mV LSB and 2.56V Full Scale 4260f 23 LTC4260 U W U U APPLICATIO S I FOR ATIO RS 0.003Ω VIN 12V Q1 Si7880DP R1 5.76k 1% CF 0.1µF 25V R5 10Ω R6 100k 4 2 1 24 16 15 17 R4 100k 18 13 20 14 12 CT 0.68µF 6 NC C3 0.1µF GND CL 1000µF 23 UV VDD SENSE GATE SOURCE FB OV SDAO ADIN SDAI LTC4260GN GPIO SCL BD_PRST ALERT ON TIMER INTVCC ADR0 ADR1 ADR2 GND 19 + R8 2.94k 1% C1 22nF R2 1k 1% R3 2.05k 5 1% 10 9 8 11 7 SDA SCL ALERT R7 6.65k 1% 4260 F12 BACKPLANE PLUG-IN CARD Figure 12. 12A, 12V Card Resident Application RS 0.01Ω Q1 FDB3632 GND OUTPUT R1 49.9k 1% INTVCC R10 3.4k R9 10k 3.3V CF 0.1µF MOC207 –48V INTVCC SDA SCL MOC207 –48V VIN –48V INTVCC R12 10k R13 3.4k R2 1.74k 1% R3 2.67k 1% 4 5 9 10 8 7 R4 5.1k MOC207 R5 10Ω 2 C1 R6 6.8nF 100k 1 24 23 SOURCE 18 FB 13 ADIN 20 SDAI LTC4260GN GPIO 14 SDA0 BD_PRST 12 SCL TIMER ON INTVCC ADR0 ADR1 ADR2 GND UV VDD OV 19 SENSE GATE 15 16 17 NC C3 0.1µF 6 R7 43.7k 1% R8 3.57k 1% CL 330µF 100V CT 68nF R14 R15 1k 100Ω Q2 CMPTA42 OPTIONAL 5V C2 0.1µF –48V 4260 F13 BACKPLANE PLUG-IN CARD Figure 13. 3A, –48V Card Resident Application 4260f 24 LTC4260 U PACKAGE DESCRIPTIO GN Package 24-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .337 – .344* (8.560 – 8.738) 24 23 22 21 20 19 18 17 16 15 1413 .033 (0.838) REF .045 ±.005 .229 – .244 (5.817 – 6.198) .254 MIN .150 – .157** (3.810 – 3.988) .150 – .165 1 .0165 ± .0015 2 3 4 5 6 7 8 9 10 11 12 .0250 BSC RECOMMENDED SOLDER PAD LAYOUT .015 ± .004 × 45° (0.38 ± 0.10) .0075 – .0098 (0.19 – 0.25) .0532 – .0688 (1.35 – 1.75) .004 – .0098 (0.102 – 0.249) 0° – 8° TYP .016 – .050 (0.406 – 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) .008 – .012 (0.203 – 0.305) TYP .0250 (0.635) BSC GN24 (SSOP) 0204 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 4260f 25 LTC4260 U PACKAGE DESCRIPTIO SW Package 24-Lead Plastic Small Outline (Wide .300 Inch) (Reference LTC DWG # 05-08-1620) .050 BSC .045 ±.005 .030 ±.005 TYP N 24 23 22 21 .598 – .614 (15.190 – 15.600) NOTE 4 20 19 18 17 16 15 14 13 N .325 ±.005 .420 MIN .394 – .419 (10.007 – 10.643) NOTE 3 1 2 3 N/2 N/2 RECOMMENDED SOLDER PAD LAYOUT .005 (0.127) RAD MIN .009 – .013 (0.229 – 0.330) .291 – .299 (7.391 – 7.595) NOTE 4 .010 – .029 × 45° (0.254 – 0.737) 2 3 4 5 6 .093 – .104 (2.362 – 2.642) 7 8 9 10 11 12 .037 – .045 (0.940 – 1.143) 0° – 8° TYP NOTE 3 .016 – .050 (0.406 – 1.270) NOTE: 1. DIMENSIONS IN 1 .050 (1.270) BSC .004 – .012 (0.102 – 0.305) .014 – .019 (0.356 – 0.482) TYP INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS 4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) S24 (WIDE) 0502 4260f 26 LTC4260 U PACKAGE DESCRIPTIO UH Package 32-Lead Plastic QFN (5mm × 5mm) (Reference LTC DWG # 05-08-1693) 0.70 ±0.05 5.50 ±0.05 4.10 ±0.05 3.45 ±0.05 (4 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC RECOMMENDED SOLDER PAD LAYOUT 5.00 ± 0.10 (4 SIDES) BOTTOM VIEW—EXPOSED PAD 0.23 TYP (4 SIDES) R = 0.115 TYP 0.75 ± 0.05 0.00 – 0.05 31 32 0.40 ± 0.10 PIN 1 TOP MARK (NOTE 6) 1 2 3.45 ± 0.10 (4-SIDES) (UH) QFN 0603 0.200 REF NOTE: 1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE M0-220 VARIATION WHHD-(X) (TO BE APPROVED) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.25 ± 0.05 0.50 BSC 4260f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 27 LTC4260 U TYPICAL APPLICATIO 3A, 48V Backplane Resident Application with Insertion Activated Turn-On 0.01Ω VIN 48V FDB3632 VOUT 48V SMAT70B 43.5k 49.9k 10Ω 100k 0.1µF 3.57k 6.8nF 100k 1.74k 2.67k UV VDD SENSE GATE SOURCE FB OV ON GPIO SDAI BD_PRST LTC4260 SDA0 ADIN SCL TIMER ALERT INTVCC ADR0 ADR1 ADR2 GND LOAD 1µF 68nF NC 4260 TA03 0.1µF BACKPLANE PLUG-IN CARD RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT 1641-1/LT1641-2 Positive High Voltage Hot Swap Controllers Active Current Limiting, Supplies from 9V to 80V LTC1921 Dual –48V Supply and Fuse Monitor Withstands ±200V, Monitors Under-/Overvoltage and External Fuses LTC2436 16-Bit, 2-Channel Delta-Sigma ADC 800nVRMS Noise, Two Differential Channels with Automatic Channel Selection LTC4240 CompactPCITM Hot Swap Controller with I2C I/O 3.3V, 5V and ±12V Supplies, Control and Status over I2C LT4250 –48V Hot Swap Controller in SO-8 Active Current Limiting, Supplies from –20V to –80V LTC4252 –48V Hot Swap Controller in MSOP Fast Active Current Limiting with Drain Accelerated Response, Supplies from –15V LT4256 Positive 48V Hot Swap Controller with Open-Circuit Detect Foldback Current Limiting, Open-Circuit and Overcurrent Fault Output, Up to 80V Supply LTC4300A Hot Swappable 2-Wire Bus Buffer Provides Capacitive Buffering, SDA and SCL Precharge and Level Shifting LTC4301 Supply Independent Hot Swappable 2-Wire Bus Buffer Provides Capacitive Buffering, SDA and SCL Precharge and Level Shifting LTC4302 Addressable 2-Wire Bus Buffer Provides Capacitive Buffering, SDA and SCL Precharge and Level Shifting, Enabled by 2-Wire Bus Commands LTC4350 Hot Swappable Load Share Controller Output Voltage: 1.2V to 12V, Equal Load Sharing LT4351 Ideal MOSFET ORing Diode External N-Channel MOSFETs Replace ORing Diodes, 1.2V to 20V LTC4354 Negative Voltage Diode-OR Controller 8-Pin DFN and SO Package ® CompactPCI is a trademark of the PCI Industrial Computer Manufacturers Group 4260f 28 Linear Technology Corporation LT/TP 0904 1K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2004