IRF IRFP23N50LPBF

PD - 94999
IRFP23N50LPbF
SMPS MOSFET
Applications
HEXFET® Power MOSFET
• Zero Voltage Switching SMPS
VDSS RDS(on) typ. Trr typ. ID
• Telecom and Server Power Supplies
• Uninterruptible Power Supplies
0.190Ω
500V
170ns 23A
• Motor Control applications
• Lead-Free
Features and Benefits
• SuperFast body diode eliminates the need for external
diodes in ZVS applications.
• Lower Gate charge results in simpler drive requirements.
• Enhanced dv/dt capabilities offer improved ruggedness.
• Higher Gate voltage threshold offers improved noise
TO-247AC
immunity.
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V
Max.
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V
15
IDM
92
Pulsed Drain Current
PD @TC = 25°C Power Dissipation
c
VGS
Linear Derating Factor
Gate-to-Source Voltage
dv/dt
TJ
Peak Diode Recovery dv/dt
Operating Junction and
TSTG
Storage Temperature Range
e
370
W
2.9
± 30
W/°C
V
14
-55 to + 150
V/ns
300 (1.6mm from case )
10lb in (1.1N m)
x
Mounting torque, 6-32 or M3 screw
Diode Characteristics
Parameter
x
Min. Typ. Max. Units
IS
Continuous Source Current
–––
–––
23
ISM
(Body Diode)
Pulsed Source Current
–––
–––
92
c
A
°C
Soldering Temperature, for 10 seconds
Symbol
Units
23
Conditions
MOSFET symbol
A
(Body Diode)
showing the
integral reverse
VSD
Diode Forward Voltage
–––
–––
1.5
V
p-n junction diode.
TJ = 25°C, IS = 14A, VGS = 0V
trr
Reverse Recovery Time
–––
170
250
ns
TJ = 25°C, IF = 23A
–––
220
330
840
Qrr
Reverse Recovery Charge
IRRM
Reverse Recovery Current
ton
Forward Turn-On Time
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–––
560
–––
980 1500
–––
7.6
11
TJ = 125°C, di/dt = 100A/µs
nC
TJ = 25°C, IS = 23A, VGS = 0V
TJ = 125°C, di/dt = 100A/µs
A
f
f
f
f
TJ = 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
1
02/11/04
IRFP23N50LPbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max. Units
V(BR)DSS
Drain-to-Source Breakdown Voltage
∆V(BR)DSS/∆TJ
Breakdown Voltage Temp. Coefficient
–––
RDS(on)
Static Drain-to-Source On-Resistance
–––
VGS(th)
Gate Threshold Voltage
3.0
IDSS
Drain-to-Source Leakage Current
IGSS
RG
500
–––
–––
0.27
–––
0.190 0.235
–––
5.0
V
Conditions
VGS = 0V, ID = 250µA
V/°C Reference to 25°C, ID = 1mA
Ω
V
VGS = 10V, ID = 14A
f
VDS = VGS, ID = 250µA
–––
–––
50
µA
VDS = 500V, VGS = 0V
–––
–––
2.0
mA
VDS = 400V, VGS = 0V, TJ = 125°C
Gate-to-Source Forward Leakage
–––
–––
100
nA
VGS = 30V
Gate-to-Source Reverse Leakage
–––
–––
-100
Internal Gate Resistance
–––
1.2
–––
Ω
f = 1MHz, open drain
VGS = -30V
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
gfs
Qg
Forward Transconductance
Qgs
Min. Typ. Max. Units
S
Conditions
12
–––
–––
VDS = 50V, ID = 14A
Total Gate Charge
–––
–––
150
Gate-to-Source Charge
–––
–––
44
Qgd
Gate-to-Drain ("Miller") Charge
–––
–––
72
VGS = 10V, See Fig. 7 & 15
td(on)
Turn-On Delay Time
–––
26
–––
VDD = 250V
tr
Rise Time
–––
94
–––
td(off)
Turn-Off Delay Time
–––
53
–––
tf
Fall Time
–––
45
–––
VGS = 10V, See Fig. 11a & 11b
Ciss
Input Capacitance
–––
3600
–––
VGS = 0V
Coss
Output Capacitance
–––
380
–––
VDS = 25V
Crss
Reverse Transfer Capacitance
–––
37
–––
Coss
Output Capacitance
–––
4800
–––
ID = 23A
nC
ns
VDS = 400V
f
ID = 23A
RG = 6.0Ω
pF
f
ƒ = 1.0MHz, See Fig. 5
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Coss
Output Capacitance
–––
100
–––
VGS = 0V, VDS = 400V, ƒ = 1.0MHz
Coss eff.
Effective Output Capacitance
–––
220
–––
VGS = 0V,VDS = 0V to 400V
Coss eff. (ER)
Effective Output Capacitance
–––
160
–––
g
(Energy Related)
Avalanche Characteristics
Symbol
EAS
Parameter
Single Pulse Avalanche Energy
Typ.
–––
Max.
410
IAR
Avalanche Current
–––
23
A
EAR
Repetitive Avalanche Energy
–––
37
mJ
Units
c
d
c
Units
mJ
Thermal Resistance
Typ.
Max.
RθJC
Symbol
Junction-to-Case
Parameter
–––
0.34
RθCS
Case-to-Sink, Flat, Greased Surface
0.24
–––
RθJA
Junction-to-Ambient
–––
40
°C/W
Notes:
 Repetitive rating; pulse width limited by
max. junction temperature. (See Fig. 11).
‚ Starting TJ = 25°C, L = 1.5mH, RG = 25Ω,
IAS = 23A, dv/dt = 14V/ns. (See Figure 12).
ƒ ISD ≤ 23A, di/dt ≤ 430A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 150°C.
2
„ Pulse width ≤ 300µs; duty cycle ≤ 2%.
… Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
Coss eff.(ER) is a fixed capacitance that stores the same energy
as Coss while VDS is rising from 0 to 80% VDSS .
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IRFP23N50LPbF
100
100
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
TOP
10
1
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
0.1
4.5V
0.01
20µs PULSE WIDTH
Tj = 25°C
0.001
10
1
4.5V
20µs PULSE WIDTH
Tj = 150°C
0.1
0.1
1
10
100
1
10
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000.00
3.0
I D = 23A
2.5
T J = 150°C
10.00
VDS = 15V
20µs PULSE WIDTH
1.00
1.0
6.0
11.0
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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16.0
2.0
(Normalized)
T J = 25°C
100.00
R DS(on) , Drain-to-Source On Resistance
ID, Drain-to-Source Current (Α)
100
1.5
1.0
0.5
V GS = 10V
0.0
-60
-40
-20
0
20
40
60
TJ , Junction Temperature
80
100
120
140
160
( °C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRFP23N50LPbF
100000
20
Coss = Cds + Cgd
10000
Ciss
Energy (µJ)
C, Capacitance(pF)
25
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
1000
15
10
Coss
100
5
Crss
0
10
1
10
100
0
1000
VDS , Drain-to-Source Voltage (V)
400
500
600
100.00
VDS = 400V
VDS = 250V
VDS = 100V
ISD, Reverse Drain Current (A)
VGS , Gate-to-Source Voltage (V)
300
Fig 6. Typ. Output Capacitance
Stored Energy vs. VDS
ID = 23
10
7
5
2
T J = 150°C
10.00
T J = 25°C
1.00
VGS = 0V
0.10
0
0
24
48
72
96
QG, Total Gate Charge (nC)
Fig 7. Typical Gate Charge vs.
Gate-to-Source Voltage
4
200
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
12
100
120
0.0
0.5
1.0
1.5
2.0
VSD, Source-toDrain Voltage (V)
Fig 8. Typical Source-Drain Diode
Forward Voltage
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IRFP23N50LPbF
1000
25
OPERATION IN THIS AREA LIMITED
BY RDS(on)
100
10us
ID , Drain Current (A)
ID , Drain Current (A)
20
100us
10
1ms
1
10
5
TC = 25 ° C
TJ = 150 ° C
Single Pulse
10
15
10ms
100
1000
10000
0
25
VDS , Drain-to-Source Voltage (V)
V GS
RG
100
125
150
( °C)
Fig 10. Maximum Drain Current vs.
Case Temperature
RD
VDS
90%
D.U.T.
+
- VDD
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 11a. Switching Time Test Circuit
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75
TC , Case Temperature
Fig 9. Maximum Safe Operating Area
VDS
50
10%
VGS
td(on)
tr
t d(off)
tf
Fig 11b. Switching Time Waveforms
5
IRFP23N50LPbF
(Z thJC)
10
1
Thermal Response
D = 0.50
0.1
0.20
0.10
P DM
0.05
0.01
0.02
0.01
t1
SINGLE PULSE
(THERMAL RESPONSE)
t2
Notes:
1. Duty factor D =
2. Peak T
0.001
0.00001
0.0001
0.001
t1/ t 2
J = P DM x Z thJC
0.01
+TC
0.1
1
t 1, Rectangular Pulse Duration (sec)
Fig 12. Maximum Effective Transient Thermal Impedance, Junction-to-Case
VGS(th) Gate threshold Voltage (V)
5.0
4.5
4.0
ID = 250µA
3.5
3.0
2.5
2.0
1.5
1.0
-75
-50
-25
0
25
50
75
100
125
150
T J , Temperature ( °C )
Fig 13. Threshold Voltage vs. Temperature
6
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IRFP23N50LPbF
750
ID
EAS , Single Pulse Avalanche Energy (mJ)
600
TOP
10A
BOTTOM
15A
23A
450
300
150
0
25
50
75
100
125
150
( °C)
Starting T , Junction
Temperature
J
Fig 14. Maximum Avalanche Energy
Vs. Drain Current
15V
V(BR)DSS
DRIVER
L
VDS
D.U.T
RG
+
- VDD
IAS
20V
tp
tp
A
0.01Ω
I AS
Fig 15a. Unclamped Inductive Test Circuit
Fig 15b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
QG
50KΩ
12V
VGS V
.2µF
.3µF
D.U.T.
+
V
- DS
QGS
QGD
VG
VGS
3mA
IG
ID
Current Sampling Resistors
Fig 16a. Gate Charge Test Circuit
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Charge
Fig 16b. Basic Gate Charge Waveform
7
IRFP23N50LPbF
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
ƒ
+
‚
-
-
„
+

RG
•
•
•
•
Driver Gate Drive
P.W.
+
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Period
D=
-
VDD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 17. For N-Channel HEXFET® Power MOSFETs
8
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IRFP23N50LPbF
TO-247AC Package Outline
Dimensions are shown in millimeters (inches)
-D-
3.65 (.143)
3.55 (.140)
15.90 (.626)
15.30 (.602)
-B-
-A-
0.25 (.010) M D B M
2.50 (.089)
1.50 (.059)
4
5.50 (.217)
20.30 (.800)
19.70 (.775)
2X
1
2
5.30 (.209)
4.70 (.185)
NOTES:
5.50 (.217)
4.50 (.177)
1 DIMENSIONING & TOLERANCING
PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSION : INCH.
3 CONFORMS TO JEDEC OUTLINE
TO-247-AC.
3
-C-
14.80 (.583)
14.20 (.559)
2.40 (.094)
2.00 (.079)
2X
5.45 (.215)
2X
4.30 (.170)
3.70 (.145)
0.80 (.031)
3X 0.40 (.016)
1.40 (.056)
3X 1.00 (.039)
0.25 (.010) M
2.60 (.102)
2.20 (.087)
C A S
3.40 (.133)
3.00 (.118)
LEAD ASSIGNMENTS
Hexfet
IGBT
1 -LEAD
GateASSIGNMENTS
1 - Gate
1 - GATE2 - Collector
2 - Drain
2 - DRAIN
3 - Source
3 - Emitter
3 - SOURCE
4 - Drain
4 - DRAIN4 - Collector
TO-247AC Part Marking Information
EXAMPLE: T HIS IS AN IRFPE30
WIT H ASSEMBLY
LOT CODE 5657
ASSEMBLED ON WW 35, 2000
IN THE AS SEMBLY LINE "H"
Note: "P" in assembly line
position indicates "Lead-Free"
INT ERNATIONAL
RECT IFIER
LOGO
PART NUMBER
IRFPE30
56
035H
57
ASSEMBLY
LOT CODE
DAT E CODE
YEAR 0 = 2000
WEEK 35
LINE H
TO-247AC package is not recommended for Surface Mount Application.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.02/04
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9