PACE1753 SINGLE CHIP, 40MHz CMOS MMU/COMBO FEATURES Implements the MIL-STD-1750A Instruction Set Architecture for Memory Management and Protection of up to 1 Megaword. All mapping memory (10,240 bits) for both the MMU and BPU functions are included on the chip. — Illegal address error detection— programmable — Multi-Master arbitration Designed to interface memory to the PACE1750A/AE 16-bit, 40 MHz processor. Systems can be designed where no WAIT states are required up to 40 MHz clock rates when using these PACE products. Information bus and EDAC transceivers on chip System performance and device count are optimized when used with the PACE1754 Processor Interface Circuit (PIC). Power Dissipation over Military Temperature Range (PD Outputs Open) < 0.20 watts at 20 MHz < 0.30 watts at 30 MHz < 0.40 watts at 40 MHz Provides the following additional functions: — EDAC, Error Detection and Correction—or parity generation and detection — Correct data register—for diagnostics — First memory failing address register 8-bit extended address latches and drivers on chip 20, 30 and 40 MHz operation over the Military Temperature Range Single 5V ± 10% Power Supply Available in: — 64-Pin DIP or Gull Wing (50 Mil Pin centers) — 68-Pin Pin Grid Array (PGA) (100 Mil centers) — 68-Lead Quad Pack (Leaded Chip Carrier) MEMORY MANAGEMENT UNIT AND BLOCK PROTECT UNIT “COMBO” — FUNCTIONAL DESCRIPTION The PACE1753 (COMBO) is a support chip for the PACE1750A/AE microprocessor family. It provides the following supporting functions to the system: 1. Memory management and access protection for up to 1M words. 2 Physical memory write protection for up to 1M words memory in pages of 1K words each. Separate protection is provided for the CPU and for DMA in systems which include DMA. 3. Detection of illegal l/O accesses (as defined by MILSTD-1750A) or access to an unimplemented block of memory. In each case an error flag is generated to the processor. 4 Detection of double errors on the data bus and correction of single errors. An error signal is generated to the processor when a multiple error is detected. 5. RDYA generation. Up to three wait states can be inserted in the address phase of the bus by generating a not-ready, RDYA low signal. The number of wait states required can be programmed in an internal register in the COMBO. 6. Bus arbitration for up to 4 masters. Arbitration is done on a fixed priority basis (i.e. by interconnection of hardware). (In 68 pin package only). Document # MICRO-4 REV D Revised November 2005 PACE1753 ABSOLUTE MAXIMUM RATINGS1 RECOMMENDED OPERATING CONDITIONS Supply Voltage Range 0.5V to +7.0V Input Voltage Range 0.5V to VCC + 0.5V Supply Voltage Range 4.5V to +5.5V Storage Temperature Range –65°C to +150°C –55°C to +125°C Input Current Range –30mA to +5mA Case Operating Temperature Range Current applied to any output3 150mA Maximum Power Dissipation2 1.5W Lead Temperature Range (soldering 10 seconds) 300°C Thermal resistance Cases X and T Cases Y and U Case Z Operating Maximum Power Dissipation (Outputs Open) Device Type 20MHz Device Type 30MHz Device Type 40MHz 0.20W 0.30W 0.40W (θJC):4 8°C/W 5°C/W 6°C/W Notes 1. Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2. Must withstand the added power dissipation due to short circuit test e.g., IOS. 3. Duration 1 second or less. 4. Device Type Definitions from 5962-89505 SMD: Case X: Dual In-Line Case T: Dual In-Line with Gull-Wing Leads Case Y: Leaded Chip Carrier with Gull-Wing Leads Case U: Leaded Chip Carrier with Unformed Leads Case Z: Pin Grid Array Document # MICRO-4 REV D Page 2 of 21 PACE1753 DC ELECTRICAL SPECIFICATIONS (Over recommended operating conditions) Symbol Parameter Min Max Unit Conditions1 VIH Input HIGH Voltage 2.0 VCC + 0.5 V VIL Input LOW Voltage2 –0.5 0.8 V VCD Input Clamp Diode Voltage –1.2 V VCC = 4.5V, IIN = –18mA VOH Output HIGH Voltage 2.4 V VCC = 4.5V, IOH = –8.0mA VCC – 0.2 V VIN = 0.8V, 2.0V IOH = –300µA VOL VOL IIH IIH IIL Output LOW Voltage, 0.5 V VCC = 4.5V, IOL = 8.0mA except EXT ADR0 – EXT ADR7 0.2 V VIN = 0.8V, 2.0V IOL = 300µA Output LOW Voltage, 0.5 V VCC = 4.5V, IOL = 20.0mA EXT ADR0 – EXT ADR7 0.2 V VIN = 0.8V, 2.0V IOL = 300µA 10 µA VIN = VCC, VCC = 5.5V 50 µA –10 µA Input HIGH Current, except IB0 – IB15, EDC0 – EDC5, EXT ADR0 – EXT ADR7 Input HIGH Current, IB0 – IB15, EDC0 – EDC5, EXT ADR0 – EXT ADR7 Input LOW Current, except IB0 – IB15, EDC0 – EDC5, EXT ADR0 – EXT ADR7 VIN = VCC, VCC = 5.5V VIN = GND, VCC = 5.5V IIL Input LOW Current, IB0 – IB15, EDC0 – EDC5, EXT ADR0 – EXT ADR7 –50 µA VIN = GND, VCC = 5.5V IOZH Output Three-State Current 50 µA VOUT = 2.4V, VCC = 5.5V IOZL Output Three-State Current –50 µA VOUT = 0.5V, VCC = 5.5V ICCQC Quiescent Power Supply Current (CMOS Input Levels, Active) 60 mA VIN < 0.2V or < VCC – 0.2V f = 0MHz, Outputs Open, VCC = 5.5V ICCQT Quiescent Power Supply Current (TTL Input Levels, Active) 110 mA VIN = 3.4V, f = 0MHz, All Inputs, Outputs Open, VCC = 5.5V Dynamic Power Supply 40 mA Current 50 mA 60 mA VCC = 0V to VCC, tr = tf = 2.5 ns, Outputs Open, VCC = 5.5V mA VOUT = GND, VCC = 5.5V ICCD Current3 –25 F = 20MHz F = 30MHz F = 40MHz IOS Output Short Circuit CIN Input Capacitance 10 pF Inputs Only COUT Output/Bi-directional Capacitance 15 pF Outputs Only (Including I/O Buffers) Notes 1. 4.5V ≤ VCC ≤ 5.5V, –55°C ≤ TC ≤ +125°C. Unless otherwise specified, testing shall be conducted at worst-case conditions. 2. VIL = –3.0V for pulse widths less than or equal to 20ns. 3. Duration of the short should not exceed one second; only one output may be shorted at a time. Document # MICRO-4 REV D Page 3 of 21 PACE1753 AC ELECTRICAL CHARACTERISTICS (VCC = 4.5V) 20 MHz Symbol TD/I (EXT ADR)V Parameter MMU Cache Hit Min Max 30MHz Min Max 40 MHz Min Max Unit 25 23 23 ns TSTRBD (EXT ADR ERR)L External Address Error 25 20 16 ns TC (IBD CORR) Error Correction Read Cycle 25 20 19 ns IBDV (SING ERR)H Error Correction Read Cycle 35 30 25 ns TC (SING ERR)L Error Correction Read Cycle 25 20 12 ns TIBDV (EDC GEN)V EDAC or Parity Write Cycle 30 25 23 ns TSTRBD (EX RDY)L MMU Cache Miss 25 20 12 ns TC (EX RDY)H MMU Cache Miss 25 20 12 ns TC (WR PROT)L MMU Cache Miss 25 22 18 ns TSTRBDH (WR PROT)H MMU Cache Miss 25 20 16 ns TC (GNT1)H Arbiter LOW to HIGH Priority 35 25 18 ns TC (GNT0)L Arbiter LOW to HIGH Priority 35 25 18 ns TC (GNT0)H Arbiter HIGH to LOW Priority 35 25 18 ns TC (GNT1)L Arbiter HIGH to LOW Priority 35 25 18 ns TC (RDYA) Address Ready 30 25 17 ns TFC (IB OUT)V Clock to IB Out Valid (I/O Read) 30 28 25 ns TIBDIN (MEM PAR ERR) Parity Mode 34 30 25 ns TC (MEM PRT ERR) Memory Protect Error 50 45 40 ns TSTRBD (WR PROT) Write Protect Cache Hit 25 20 16 ns TC (WR PROT)L Write Protect Cache Miss 25 22 18 ns TSTRBDH (WR PROT)H Write Protect Cache Miss 25 22 18 ns TD/I (PROT FLAG) Cache Hit (BPU Protection Error) 50 45 40 ns TD/I (PROT FLAG) Cache Hit (MMU Key-Lock Error) 40 35 30 ns TC (PROT FLAG) Cache Miss (BPU Protection Error) 45 35 30 ns TC (PROT FLAG) Cache Hit (MMU Key-Lock Error) 25 20 20 ns TC (EXT ADR) Clock to EXT ADR Valid (Miss) 32 30 23 ns Notes: 1. 4.5V ≤ VCC ≤ 5.5V, –55°C ≤ TC ≤ +125°C. Unless otherwise specified, testing shall be conducted at worst-case conditions. 2. VIL = –3.0V for pulse widths less than or equal to 20ns. 3. Duration of the short should not exceed one second; only one output may be shorted at a time. 4. Pulse width of WR PROT/PROT FLAG shall be ≥ 80% of STRBD pulse width. Document # MICRO-4 REV D Page 4 of 21 PACE1753 TERMINAL CONNECTIONS Case Outlines: Dual-In-Line (Case X) and Dual-In-Line with Gull-Wing Leads (Case T) Terminal Number Terminal Symbol Terminal Number Terminal Symbol Terminal Number Terminal Symbol 1 GND 23 IB13 44 AS1 2 EDC0 24 IB14 45 AS0 3 EDC1 25 IB15 46 GND 4 EDC2 26 MEM PRT ER 47 AK3 5 RESET 27 MEM PAR ER 48 AK2 6 EDC3 28 EXT ADR ER 49 AK1 7 EDC4 29 RAM DIS 50 AK0 8 EDC5 30 SING ERR 51 CLK 9 IB0 31 DMA ACK 52 STRBA 10 IB1 32 GND 53 STRBD 11 IB2 33 EXT ADR0 54 GND 12 IB3 34 EXT ADR1 55 EX RDY 13 IB4 35 EXT ADR2 56 WR PROT/PROT FLAG 14 IB5 36 EXT ADR3 57 R/W 15 IB6 37 EXT ADR4 58 D/I 16 IB7 38 EXT ADR5 59 M/IO 17 IB8 39 EXT ADR6 60 RDYA 18 IB9 40 EXT ADR7 61 NC 19 VCC 41 VCC 62 NC 20 IB10 42 AS3 63 NC 21 IB11 43 AS2 64 VCC 22 IB12 Document # MICRO-4 REV D Page 5 of 21 PACE1753 TERMINAL CONNECTIONS Case Outlines: Leaded Chip Carrier with unformed leads (Case U) and Leaded Chip Carrier with GullWing Leads (Case Y) Terminal Number Terminal Symbol Terminal Number Terminal Symbol Terminal Number 1 GND 24 IB12 47 AS1 2 EDC0 25 IB13 48 AS0 3 EDC1 26 IB14 49 BUS REQ 2 4 EDC2 27 IB15 50 AK3 5 RESET 28 MEM PRT ERR 51 AK2 6 EDC3 29 MEM PAR ERR 52 BUS GNT 1 7 EDC4 30 EXT ADR ERR 53 AK1 8 EDC5 31 RAM DIS 54 AK0 9 BUS GNT 2 32 SING ERR 55 CLK 10 IB0 33 DMA ACK 56 STRBA 11 IB1 34 GND 57 STRBD 12 IB2 35 VCC 58 BUS REQ 0 13 IB3 36 EXT ADR0 59 EX RDY 14 IB4 37 EXT ADR1 60 WR PROT/PROT FLAG 15 IB5 38 EXT ADR2 61 R/W 16 IB6 39 EXT ADR3 62 D/I 17 IB7 40 EXT ADR4 63 M/IO 18 BUS REQ 3 41 EXT ADR5 64 RDYA 19 IB8 42 EXT ADR6 65 BUS GNT 0 20 IB9 43 EXT ADR7 66 BUS LOCK 21 BUS GNT 3 44 GND 67 BUS REQ 1 22 IB10 45 AS3 68 VCC 23 IB11 46 AS2 Document # MICRO-4 REV D Terminal Symbol Page 6 of 21 PACE1753 TERMINAL CONNECTIONS Case Outline: Pin Grid Array (Case Z) Terminal Number Terminal Symbol Terminal Number Terminal Symbol Terminal Number Terminal Symbol B1 IB14 L5 EDC1 D11 AS0 B2 IB13 K5 EDC0 D10 AS1 C1 IB12 L6 GND C11 AS2 C2 IB11 K6 VCC C10 AS3 D1 IB10 L7 BUS REQ 1 B11 VCC D2 BUS GNT 3 K7 BUS LOCK A10 GND E1 IB9 L8 BUS GNT 0 B10 EXT ADR7 E2 IB8 K8 RDYA A9 EXT ADR6 F1 BUS REQ 3 L9 M/IO B9 EXT ADR5 F2 IB7 K9 D/I A8 EXT ADR4 G1 IB6 L10 R/W B8 EXT ADR3 G2 IB5 K11 WR PROT/PROT FLAG A7 EXT ADR2 H1 IB4 K10 EX RDY B7 EXT ADR1 H2 IB3 J11 BUS REQ 0 A6 EXT ADR0 J1 IB2 J10 STRBD B6 GND J2 IB1 H11 STRBA A5 DMA ACK K1 IB0 H10 CLK B5 SING ERR L2 BUS GNT 2 G11 AK0 A4 RAM DIS K2 EDC5 G10 AK1 B4 EXT ADR ERR L3 EDC4 F11 BUS GNT 1 A3 MEM PAR ERR K3 EDC3 F10 AK2 B3 MEM PRT ERR L4 RESET E11 AK3 A2 IB15 K4 EDC2 E10 BUS REQ 2 Document # MICRO-4 REV D Page 7 of 21 PACE1753 MMU Cache Hit External Address Error Note: All time measurements on active signals relate to 1.5V levels. Document # MICRO-4 REV D Page 8 of 21 PACE1753 Error Correction (Write Cycle) Memory Protect Error Error Correction (Read Cycle) Ready Address Memory Parity Error Note: All time measurements on active signals relate to 1.5V levels. Document # MICRO-4 REV D Page 9 of 21 PACE1753 MMU Cache Miss Cycle (WA = 0) MMU Cache Miss Cycle (WA > 0) * The WR PROT/PROT FLAG signal is programmed as WR PROT or PROT FLAG. (See BPU Description), T = 1 Clock Period. Note: All time measurements on active signals relate to 1.5V levels. Document # MICRO-4 REV D Page 10 of 21 PACE1753 Low Priority to High Priority Transition B0 B1 B2 B3 B0 B0 B1 CLK REQ1 TC (GNT1)H GNT1 REQ0 LOCK GNT0 TC (GNT0)L Bus Arbitrator High Priority to Low Priority Transition Note: All time measurements on active signals relate to 1.5V levels. Document # MICRO-4 REV D Page 11 of 21 PACE1753 SWITCHING WAVEFORMS AND TEST CIRCUIT (Continued) IB Bus Output (0:15) Standard Output (Non Three-State) Three-State Note: All time measurements on active signals relate to 1.5V levels. Document # MICRO-4 REV D Parameter VO VMEA TPLZ ≥ 3V 0.5V TPHZ 0V VCC – 0.5V TPXL VCC/2 1.5V TPXH VCC/2 1.5V Page 12 of 21 PACE1753 PIN FUNCTIONS Symbol Name Description BUS REQ0 BUS REQ3 Bus Request1 BUS LOCK Bus Lock1 BUS GNT0 BUS GNT3 Bus Grant1 Active LOW outputs indicating which master was granted the bus. It remains active during BUS LOCK unless a higher master request occurs, which resets it. However, the higher master will be granted the bus only after the present master’s BUS LOCK releases the bus. M/IO Memory or I/O An input signal that indicates whether the current bus cycle is a memory (HIGH) or l/O (LOW) cycle. D/I Data or Instruction An input signal that indicates whether the current bus cycle access is for data (HIGH) or instruction (LOW). R/W Read or Write An input signal that indicates the direction of data flow on the bus. A HIGH indicates a memory read or input operation into the master and a LOW indicates a memory write or output operation from the master. STRBA Address Strobe An active HIGH input used to latch the address at the HIGH-toLOW transition of the strobe. STRBD Data Strobe An active LOW input used to strobe data in memory and I/O cycles. CPU-CLK CPU Clock A single-phase input clock signal (0-40MHz, 40% to 60% duty cycle.) RESET Reset An active LOW input that initializes the device. AK0 - AK3 Access Key Active HIGH inputs used to match the access lock in the MMU page for memory accesses. A mismatch will cause the MEM PRT ERR signal to become active. AS0 - AS3 Address State Active HIGH inputs that select the page register group in the MMU. In the DMA physical demultiplexed mode, AS(0:1) will receive the 9th and 10th most significant bits of the physical address for use in the BPU function. EXT ADR0 EXT ADR7 Extended Addresses Bus A bi-directional active HIGH bus. In CPU cycles, it is an output bus which is used to select one of 256 pages, 4K words each, expanding the direct addressing space to 1M word. In DMA cycles, indicated by DMA-ACK being active, it is also an output bus except when programmed for the physical demultiplexed DMA mode. In this case it becomes an input to receive the 8 most significant bits of the DMA physical address for use in the BPU function. IB0 - IB15 Information Bus An active HIGH bi-directional time multiplexed address/data bus. IB0 is the most significant bit. EDC0 - EDC5 Detection/Correction Bus An active HIGH bi-directional bus used for detection of errors on the data bus (IB0 - IB15) and correction of single errors. When working in parity mode EDC0 is the parity bit. EDC0 - EDC5 are undefined in this case. Document # MICRO-4 REV D Active LOW inputs that indicate a requirement for the bus from 4 masters on the bus. The master assigned to pin BUS-REQ0 has highest priority; the master assigned to pin BUS-REQ3 has lowest priority. An active LOW input that indicates that the one master assigned the bus is using the bus. A new master will receive a bus grant only after this signal becomes inactive. Page 13 of 21 PACE1753 PIN FUNCTIONS (Continued) Symbol Name Description MEM PRT ERR Memory Protect Error An active LOW output generated by the MMU or BPU blocks to signal to the CPU a protected memory violation. The error is generated in one of the following conditions: a mismatch in the access keys in the MMU page, an access to an execution protected page during instruction cycles, an access to a write-protected page during data cycles, or an access to a page write-protected by the BPU. MEM PAR ERR Memory Parity Error An active LOW output which signals to the CPU an error on the data bus during a memory cycle. Two detection modes can be selected by programming the control register: EDAC mode (6 Hamming code parity bits) or single bit parity mode (even or odd parity). The signal is inactive when none of the above modes are selected (default after Reset). EXT ADR ERR External Address Error An active LOW output which signals to the CPU an unimplemented memory or illegal I/O access. SING ERR Single Error An active HIGH output to signal detection of a single error on the data bus in memory cycles. It is high impedance when the EDAC function is disabled by the program (default state after Reset). RAM DIS RAM-Disable An active HIGH input from the P1754 device which enables the corrected data on the data bus when the EDAC function is enabled. An internal one clock delay is generated before the data is output on the bus to allow external memory to disconnect itself from the bus. EX RDY Data Ready An active HIGH output that indicates that no wait states are requested. It becomes inactive for one clock (inserting one wait state) whenever a memory page different than the current one is accessed (causing a miss). RDYA Address Ready An active HIGH output that indicates that no wait states are requested when STRBA is active. Wait states are inserted when this signal becomes inactive during STRBA. Up to three wait states can be inserted by programming an internal register. Three wait states are inserted after Reset (default). WR PROT/ PROT FLAG Write Protected/ Protection Flag Either an active LOW output (following STRBD timing) during legal memory write cycles, when no protection error occurs, or an active HIGH level indicating a protection error in a write cycle. Each mode can be selected by programming the control register. Default mode after Reset is write-protected. DMA ACK DMA Acknowledge An active HIGH input from the DMA controller which indicates a DMA cycle. Used to select the DMA table in the BPU memory for protection. For example, this could allow the DMA channel to update the program which could be write-protected from the processor. In the physical DMA mode, it will cause the Extended Address Lines (EXT ADR0-7) to become inputs, providing BPU protection of the DMA transfers. Note: 1. Used for Bus Arbitration; only available on 68-lead devices. Document # MICRO-4 REV D Page 14 of 21 PACE1753 Standardized Military Drawing PIN Vendor CAGE Number Vendor similar PIN 5962-8950501UX 3DTT2 P1753-20QLMB 5962-8950501YX 3DTT2 P1753-20QGMB 5962-8950501ZX 3DTT2 P1753-20PGMB 5962-8950502UX 3DTT2 P1753-30QLMB 5962-8950502YX 3DTT2 P1753-30QGMB 5962-8950502ZX 3DTT2 P1753-30PGMB 5962-8950503UX 3DTT2 P1753-40QLMB 5962-8950503YX 3DTT2 P1753-40QGMB 5962-8950503ZX 3DTT2 P1753-40PGMB 5962-8950504TX 3DTT2 P1753-20GMB 5962-8950504XX 3DTT2 P1753-20CMB 5962-8950505TX 3DTT2 P1753-30GMB 5962-8950505XX 3DTT2 P1753-30CMB 5962-8950506TX 3DTT2 P1753-40GMB 5962-8950506XX 3DTT2 P1753-40CMB ORDERING INFORMATION Document # MICRO-4 REV D Page 15 of 21 PACE1753 CASE OUTLINE X: 64 Lead Top Brazed DIP Package, Straight Lead Version (Ordering Code C) Inches .002 .005 .008 .010 .015 .016 .018 .025 .040 .050 .185 .265 .470 .530 .590 .620 .645 1.550 1.563 mm 0.05 0.12 0.20 0.25 0.38 0.40 0.45 0.63 1.01 1.27 4.70 6.73 11.93 13.46 14.98 15.74 16.38 39.37 39.70 NOTES: 1) Dimensions are in inches. 2) Metric equivalents are given for general information only. 3) Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. Document # MICRO-4 REV D Page 16 of 21 PACE1753 CASE OUTLINE T: 64 Lead Top Brazed DIP Package, Gullwing Lead Version (Ordering Code G) Inches .001 .003 .005 .008 .010 .015 .016 .022 .030 .040 .050 .150 .470 .530 .590 .620 .868 1.663 mm 0.03 0.08 0.12 0.20 0.25 0.38 0.41 0.55 0.76 1.01 1.27 3.81 11.93 13.46 14.98 15.74 22.04 42.24 NOTES: 1) Dimensions are in inches. 2) Metric equivalents are given for general information only. 3) Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. 4) Case T is derived from Case X by forming the leads to the shown gullwing configuration. Document # MICRO-4 REV D Page 17 of 21 PACE1753 CASE OUTLINE U: 68 Lead Quad Pack with Straight Leads (Ordering Code QL) Inches .002 .004 .006 .010 .012 .020 .050 .100 .116 .250 .560 .570 .800 .955 1.090 mm 0.05 0.10 0.15 0.25 0.30 0.51 1.27 2.54 2.95 6.40 14.22 14.48 20.32 24.25 27.69 NOTES: 1) Dimensions are in inches. 2) Metric equivalents are given for general information only. 3) Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. 4) Pin 1 indicator can be either rectangle, dot, or triangle at specified location or referenced to the uniquely beveled corner. 5) Corners indicated as notched may be either notched or square. Document # MICRO-4 REV D Page 18 of 21 PACE1753 CASE OUTLINE Y: 68 Lead Quad Pack with Gullwing Leads (Ordering Code QG) Inches .004 .005 .008 .010 .012 .015 .016 .020 .024 .040 .050 .100 .115 .570 .800 .955 1.010 1.090 mm 0.10 0.12 0.20 0.25 0.30 0.38 0.41 0.50 0.60 1.02 1.27 2.54 2.92 14.48 20.32 24.25 25.65 27.68 NOTES: 1) Dimensions are in inches. 2) Metric equivalents are given for general information only. 3) Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. 4) Pin 1 indicator can either be rectangle, dot, or triangle at specified location or referenced to the uniquely beveled corner. 5) Corners indicated as notched my be either notched or square (with radius). 6) Case Y is derived from Case U by forming the leads to the shown gullwing configuration. Document # MICRO-4 REV D Page 19 of 21 PACE1753 CASE OUTLINE Z: 68-Pin Pin Grid Array (PGA) (Ordering Code PG) Inches .016 .020 .040 .050 .059 .060 .098 .100 .120 .150 .170 1.010 1.089 1.160 mm 0.41 0.50 1.01 1.27 1.49 1.52 2.49 2.54 3.04 3.81 4.32 25.65 27.66 29.46 NOTES: 1) Dimensions are in inches. 2) Metric equivalents are given for general information only. 3) Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. 4) Corners except pin number 1 (ref.) can be either rounded or square. 5) All pins must be on the .100" grid. Document # MICRO-4 REV D Page 20 of 21 PACE1753 REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: MICRO-4 PACE1753 CMOS MMU/COMBO REV. ISSUE DATE ORIG. OF CHANGE ORIG May-89 RKK New Data Sheet A Jul-04 JDB Added Pyramid logo B Aug-05 JDB Re-created electronic version C Oct-05 JDB Altered case outline drawing for case X and case T D 11/15/05 JDB Removed Commercial Temp Document # MICRO-4 REV D DESCRIPTION OF CHANGE Page 21 of 21