NCV7361A Voltage Regulator with Integrated LIN Transceiver The NCV7361A consists of a low drop voltage regulator, 5.0 V/50 mA and a LIN bus transceiver. The LIN transceiver is suitable for LIN bus systems compatible to “LIN−Protocol Specification” Rev. 1.3, 2.0 and SAE J2602. The combination of voltage regulator and bus transceiver make it ideal for a powerful and inexpensive cost effective slave node in a LIN Bus system. http://onsemi.com MARKING DIAGRAM Features • Operating Voltage VSUP = 5.5 to 18 V • Very Low Standby Current Consumption < 110 A in Normal Mode • • • • • • • • (< 50 A in Sleep Mode) LIN−Bus Transceiver: ♦ PNP−Bipolar Transistor Driver ♦ Slew Rate Control and Wave Shaping for Best EMC Behavior ♦ BUS Input Voltage −24 V to 30 V (Independent of VSUP) ♦ Wake−Up Via LIN Bus ♦ Baud Rate up to 20 kBaud ♦ Compatible to LIN Specification 1.3, 2.0 and SAE J2602 ♦ Compatible to ISO9141 Functions Wake−Up by LIN BUS and Startup Capable Independent of EN Voltage Level Linear Low Drop Voltage Regulator: ♦ Output Voltage 5.0 V 2% ♦ Output Current Max. 50 mA ♦ Output Current Limit ♦ Overtemperature Shutdown Reset Time 100 ms and Reset Threshold Voltage 4.65 V CMOS Compatible Interface to Microcontroller Load Dump Protected (40 V Peak) Resistant Against Transient Pulses According to ISO 7637 at Pin VSUP, BUS and EN NCV Prefix for Automotive and Other Applications Requiring Site and Change Control Semiconductor Components Industries, LLC, 2005 March, 2005 − Rev. 0 1 8 SO−8 D SUFFIX CASE 751 8 1 7361A ALYW 1 A L Y W = Assembly Location = Wafer Lot = Year = Work Week PIN CONNECTIONS VSUP 1 8 VOUT EN 2 7 RESET GND 3 6 TxD BUS 5 RxD 4 (Top View) ORDERING INFORMATION Device Package Shipping† NCV7361AD SO−8 98 Units / Rail NCV7361ADR2 SO−8 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Publication Order Number: NCV7361A/D NCV7361A VSUP VOUT Control Amplifier Aux. Supply Current Limitation + Bandgap VBG MR Reset Generator − IVAUX POR Adjustment UVR 4.65 V VSUP VOUT RESET EN Mode Control Wake−Up Control Reset Timer Wake− Filter OSC GND Thermal Protection TSHD VSUP VOUT Rec−Filter RxD Receiver 30 k VOUT Slew Rate Control BUS TSHD Driver Control Filter MR MR = Master Reset TSHD = Thermal Shutdown VBG = Bandgap Voltage Figure 1. Block Diagram PACKAGE PIN DESCRIPTION Pin Symbol 1 VSUP Description 2 EN 3 GND Ground 4 BUS LIN bus line. 5 RxD Receive output (push−pull to VOUT). 6 TxD Transmit input (pullup−input to VOUT). 7 RESET 8 VOUT Supply voltage. Enable input controls the regulator. Active high. Reset output, active low (pullup to VOUT). Regulator output 5.0 V/50 mA. http://onsemi.com 2 TxD NCV7361A ELECTRICAL SPECIFICATIONS All voltages are referenced to ground (GND). Positive currents flow into the IC. The maximum ratings (in accordance with IEC 134) given in the table below are limiting values that do not lead to a permanent damage of the device but exceeding any of these limits may do so. Long term exposure to limiting values may affect the reliability of the device. Correct operating of the device can’t be guaranteed if any of these limits are exceeded. OPERATING CONDITIONS Characteristic Supply Voltage Symbol Min Max Unit VSUP 5.25 18 V Operating Ambient Temperature TA −40 +125 °C Junction Temperature TJ − +150 °C MAXIMUM RATINGS Rating Symbol Condition Min Max Unit VSUP − −1.0 30 V T 500 ms − 40 − −24 30 T 500 ms − 40 VSUP−VOUT − −0.3 40 V VINEN − −0.3 VSUP + 0.3 V TxD, RxD, RESET VIN − −0.3 VOUT + 0.3 V EN, TxD, RxD, RESET IIN − −25 25 mA IINSH − −500 500 mA ESDBUSHB Human Body Model, 100 pF via 1.5 k −1.0 1.0 kV ESDHB Human Body Model, 100 pF via 1.5 k −2.0 2.0 kV Junction Temperature TJ − − 150 °C Storage Temperature TSTG − −55 150 °C Tsld 60 second maximum above 183°C −5°C/+0°C allowable conditions − 240 peak °C VSUP BUS VBUS Difference VSUP−VOUT EN Short Circuit of Pin VSUP and VOUT ESD Capability TxD Pin ESD Capability on All Other Pins Lead Temperature Soldering Reflow: (SMD styles only) V Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. THERMAL RATINGS Parameter SO−8 Package Test Conditions Typical Value Units Min−Pad Board (Note 1) 1.0 in Pad Board (Note 2) Junction−to−Tab (psi−JL2, JL2) (Note 3) 48 43 °C/W Junction−to−Ambient (RJA, JA) 183 120 °C/W 1. 1 oz copper, 54 mm2 copper area, 0.062” thick FR4. 2. 1 oz copper, 714 mm2 copper area, 0.062” thick FR4. 3. psi−JL2 temperature was made at foot of lead #2. http://onsemi.com 3 NCV7361A ELECTRICAL CHARACTERISTICS (5.25 V VSUP 18 V, −40°C TA 125°C unless otherwise noted) Characteristic Symbol Condition Min Typ Max Unit ISnl VEN = VSUP = 12 V, VBUS > VSUP − 0.5 V, Pins 5 to 8 Open − − 110 A Supply Current, “Sleep Mode’’ ISsleep VSUP = 12 V, VEN = 0 V, VBUS > VSUP − 0.5 V − 35 50 A Thermal Shutdown (Note 5) TJSHD − 155 − 175 °C Thermal Recovery (Note 5) TJrec − 126 − 130 °C VSUP Undervoltage Reset “OFF” VSUVR_OFF VSUP Ramp Up − 3.5 3.9 V VSUP Undervoltage Reset “ON” VSUVR_ON VSUP Ramp Down − 3.0 3.3 V VSUP Undervoltage Hysteresis VSUVR_HYS VSUVR_OFF − VSUVR_ON 0.2 − − V 5.25 12 18 V VSUP Supply Current with VOUT “No Load’’ (Note 4) Operating Voltage VSUP VOUT VOUTt 5.5 V VSUP 18 V 0 < IOUT < 50 mA 4.90 5.0 5.10 V VOUTh VSUP > 18 V 4.90 5.0 5.25 V VOUTl IVOUT = 20 mA, VSUP = 3.3 V − VSUP−VD − V IVOUT = 50 mA, VSUP = 3.3 V − VSUP−VD − V VD IVOUT = 20 mA − − 150 mV IVOUT = 50 mA − − 500 mV Output Current IVOUT 3.0 V < VSUP < 18 V VOUT = 0 V 50 − 150 mA Load Capacity Cload Reference Figure 35 4.7 − − F Input Voltage Low VENL − −0.3 − 1.6 V Input Voltage High VENH − 2.5 − VSUP +0.3 V Hysteresis (Note 5) VENHYS − 100 − − mV IpdEN VEN > VENH 1.0 4.0 7.0 A VEN < VENL 70 100 130 A IOUT = 1.0 mA, VSUP > 5.5 V − − 0.8 V 10 k RESET to VOUT VSUP = VOUT = 0.8 V − − 0.2 V Output Voltage Drop−Out Voltage (Note 6) VD = VSUP−V VOUT ENABLE (EN) Pulldown Current RESET Output Voltage Low VOL Ipu − −500 −375 −250 A RESET Threshold VRES Referred to VOUT, VSUP > 4.6 V 4.5 4.65 4.8 V Master Reset Threshold (Note 5) VMRes − 3.0 3.15 3.3 V Pullup Current 4. See Figure 6 for test setup. 5. Not production tested, guaranteed by design and qualification. 6. Measured when the output voltage has dropped 100 mV from the VSUP = 12 V nominal value. http://onsemi.com 4 NCV7361A ELECTRICAL CHARACTERISTICS (5.25 V VSUP 18 V, −40°C TA 125°C unless otherwise noted) Characteristic Symbol Condition Min Typ Max Unit 0.4 *VSUP − 0.6 *VSUP V 0.475 *VSUP 0.5 *VSUP 0.525 *VSUP 0.12 *VSUP 0.135 *VSUP 0.15 *VSUP LIN BUS INTERFACE Receive Threshold Vthr_rec, Vthr_dom Receive Center Point Vthr_cnt = (Vthr_rec + Vthr_dom)/2 Vthr_cnt Receive Hysteresis Vthr_hys = Vthr_rec − Vthr_dom Vthr_hys BUS Input Current (Recessive) (Note 7) IINBUSR 8.0 VBUS 18 V, VSUP = VBUS − 0.7 V, TxD = 4.5 V − − 20 A BUS Input Current (Recessive) −IINBUSR VSUP = 0 V, VBUS = −12 V −1.0 − − mA BUS Input Current (Recessive) −IINBUSR VSUP = Open, VBUS = −18 V −1.0 − − mA RBUSpu − 20 30 47 k BUS Output Voltage (Dominant) (Note 7) VBUSdom 7.0 VSUP 18 V, TxD = 0 V, RL = 500 − − 1.2 V BUS Output Voltage (Recessive) (Notes 7 and 8) VBUSrec 7.0 VSUP 18 V, TxD = 4.5 V 0.8 *VSUP − − V ILIM VBUS > 2.5 V, TxD = 0 V 40 − 120 mA Rpu_TxD − 9.5 15 21 k Input Low Level VIL − − − 1.25 V Input High Level VIH − 3.75 − − V Output Voltage Low VOL IOUT = 1.0 mA − − 0.8 V Output Voltage High VOH IOUT = −1.0 mA 4.2 − − V BUS Pullup Resistor BUS Current Limit 7.0 V VSUP 18 V TxD Pullup Resistance RxD 7. See Figures 7, 8, and 9 for test setup. 8. The recessive voltage on BUS should not be less than 80% direct battery. The LIN specification requires an external reverse battery diode between the battery and VSUP. VSUP = VBAT −0.7 V. http://onsemi.com 5 NCV7361A ELECTRICAL CHARACTERISTICS (7.0 V VSUP 18 V, −40°C TA 125°C unless otherwise noted) Characteristic Symbol Condition Min Typ Max Unit tRes − 70 100 140 ms trr − 3.0 7.5 15 s tdeb_BUS − 1.5 2.8 4.0 s tWake_BUS − 25 60 120 s RESET AC CHARACTERISTICS Reset Time Reset Rise Time (Note 9) BUS Debounce Time (Note 14) Wake−Up Time GENERAL LIN BUS INTERFACE AC CHARACTERISTICS Transmit Propagation Delay TxD −> BUS (Notes 10 and 11) tdr_TxD, tdf_TxD RL/CL at BUS 1.0 k/1.0 nF 660 /6.8 nF 500 /10 nF VSUPMIN = 8 V − − 4.0 s Symmetry of Propagation Delay BUS −> RxD (Note 10) tdsym_TxD tdr_TxD − tdf_TxD VSUPMIN = 8 V −2.0 − 2.0 s Receiver Propagation Delay BUS −> RxD (Notes 10 and 11) tdr_RxD tdf_RxD CL(RxD) = 50 pF VSUPMIN = 8 V − − 6.0 s Symmetry of Propagation Delay TxD −> BUS (Note 10) tdsym_RxD tdr_RxD − tdf_RxD VSUPMIN = 8 V −2.0 − 2.0 s Slew Rate BUS Rising Edge (Note 9) dV/dTrise 20% VBUS 80% CL = 1.0 nF, RL = 1.0 k VSUPMIN = 8 V 1.0 1.7 2.5 V/s Slew Rate BUS Falling Edge (Note 9) dV/dTfall 20% VBUS 80% CL = 1.0 nF, RL = 1.0 k VSUPMIN = 8 V −2.5 −1.7 −1.0 V/s LIN BUS PARAMETER ACCORDING TO LIN SPEC. REV. 1.3 Slope Time, Transition from Recessive to Dominant (Notes 11 and 12) tsdom VSUP = 8.0 V RL = 500 /CL = 10 nF − − 12 s Slope Time, Transition from Dominant to Recessive (Notes 11 and 13) tsrec VSUP = 8.0 V RL = 500 /CL = 10 nF − − 12 s Slope Time Symmetry tssym VSUP = 8.0 V RL = 500 /CL = 10 nF Tssym = tsdom − tsrec −7.0 − 1.0 s Slope Time, Transition from Recessive to Dominant (Notes 11 and 12) tsdom VSUP = 18 V RL = 500 /CL = 10 nF − − 18 s Slope Time, Transition from Dominant to Recessive (Notes 11 and 13) tsrec VSUP = 18 V RL = 500 /CL = 10 nF − − 18 s Slope Time Symmetry tssym VSUP = 18 V RL = 500 /CL = 10 nF Tssym = tsdom − tsrec −5.0 − 5.0 s 9. Not production tested, guaranteed by design and qualification. 10. See Figures 2 and 3, Timing Diagrams. 11. See Figures 5, 6, 7, 8, and 9 for test setup. 12. tsdom = (tVBUS40% − tVBUS95%) / 0.55. 13. tsdom = (tVBUS60% − tVBUS5%) / 0.55. 14. See Figure 18. http://onsemi.com 6 NCV7361A ELECTRICAL CHARACTERISTICS ( VSUP = 7.0 V to 18 V; BUS loads: 1.0 k / 1 nF; 660 / 6.8 nF; 500 / 10 nF, TxD Signal: tBit = 50 s, twH = TwL = tBit; trise = tfall < 100 ns, −40°C ≤ TA ≤ 125°C unless otherwise noted) Characteristic Symbol Condition Min Typ Max Unit − 40 50 58 s s LIN BUS PARAMETER ACCORDING TO LIN SPEC. REV. 2.0 Minimal Recessive Bit Time (Notes 15 and 16) trec(min) Maximum Recessive Bit Time (Notes 15 and 16) trec(max) − 40 50 58 Duty Cycle 1 D1 D1 = trec(min) / (2 * tBit) 0.396 − − Duty Cycle 2 D2 D2 = trec(max) / (2 * tBit) − − 0.581 15. See Timing Diagrams. 16. See Test Circuits for Dynamic and Static Characteristics. TIMING DIAGRAMS TxD 50% tdf_TxD VBUS 100% 95% BUS tdr_TxD 50% 50% 5% 0% tdf_RxD RxD tdr_RxD 50% Figure 2. Timing Diagram for Propagation Delay According to LIN 1.3 and 2.0 VBUS 100% 95% 60% BUS 40% 5% 0% Vdom tsdom tsrec Figure 3. Timing Diagram for Slope Times According to LIN 1.3 http://onsemi.com 7 NCV7361A tBIT tBIT TxD tdom(max) VSUP trec(min) 100% 74.4% tdom(min) 58.1% BUS 58.1% 42.2% 28.4% VSS 28.4% trec(max) 0% RxD Figure 4. Timing Diagram for Duty Cycle According to LIN 2.0 TEST CIRCUITS NCV7361A VSUP VSUP VOUT EN RL RESET GND TxD BUS RxD 10 F + 100 nF 50 pF CL Figure 5. Test Circuit for Delay Time, Slope Time, and Duty Cycle 12 V IS1 A NCV7361A VSUP VOUT EN + RESET GND TxD BUS RxD 10 F + Figure 6. Test Circuit for Supply Current ISnl http://onsemi.com 8 100 nF NCV7361A TEST CIRCUITS (continued) NCV7361A VBAT VSUP VOUT EN V RESET GND TxD BUS RxD 10 F + 100 nF VBUSREC Figure 7. Test Circuit for Bus Voltage “Recessive’’ (VBUSREC) NCV7361A VSUP VSUP VOUT EN RESET 10 F + 100 nF 500 V GND TxD BUS RxD VBUSD Figure 8. Test Circuit for Bus Voltage “Dominant’’ VBUSDOM NCV7361A VBAT VSUP VOUT EN IINBUSR A RESET GND TxD BUS RxD + 10 F 100 nF Figure 9. Test Circuit for Bus Current “Recessive’’ IINBUSR NCV7361A 13.5 V VSUP VOUT EN RESET GND TxD BUS RxD + CVAR 100 nF RL Figure 10. Test Circuit for VOUT Rise Time vs. Load Capacitance and Resistance http://onsemi.com 9 V VOUT NCV7361A TYPICAL OPERATING CHARACTERISTICS Figure 11. Vout Rise Time with 1 F, 10 F, 100 F, and 150 F Capacitors and 200 Load using EN to Enable the Output. Figure 12. Vout Rise Time with a 10 F Load Capacitor and 1 k, 200 , and 100 Load using EN to Enable the Output. Figure 13. Vout Rise Time with a 100 F Load Capacitor and 1 k, 200 , and 100 Load using EN to Enable the Output. Figure 14. Vout Rise Time with a 150 F Load Capacitor and 1 k, 200 , and 100 Load using EN to Enable the Output. http://onsemi.com 10 NCV7361A FUNCTIONAL DESCRIPTION Operating Modes The NCV7361A consists of a low drop voltage regulator 5.0 V/50 mA and a LIN Bus transceiver, which is a bidirectional bus interface for data transfer between the LIN bus and the LIN protocol controller. Additionally, the NCV7361A features a RESET output with a reset delay of 100 ms and a fixed threshold of 4.65 V and Enable (EN) control for the regulator. The NCV7361A provides two main operating modes “normal” and “sleep” and the intermediate states “POR”, “Ini−state” and “thermal shutdown”. The main modes are fixed states defined by basic actions (VSUP start, EN or wake−up). The intermediate states are soft states. They aren’t defined by logical actions but by changes of voltage (VSUP, VOUT) or junction temperature. VSUP POWER ON Clear All State−FF Clear RESET Timer Regulator ON VOUT Ramp Up RESET = L Wake−Up Disabled VSUP > UVR_OFF POR Ini−state VSUP < UVR_ON VOUT > VRES (4.65 V) VOUT < VRES VSUP < UVR_ON Normal Mode VSUP > UVR_OFF and (EN = L/H or Bus Wake−Up) EN = H/L Regulator ON RESET = L after 100 ms RESET = H Wake−Up Disabled LIN Transceiver ON Normal Mode and TJ < TJREC EN = L Sleep Mode EN = H Normal Mode and TJ > TJSHD Sleep Mode and TJ < TJREC Sleep Mode and TJ < TJSHD Thermal Shutdown Regulator OFF Wake−Up Enabled (LIN Receiver ON) LIN Transmitter OFF Regulator OFF Wake−Up Disabled LIN Transceiver OFF TJ < TJREC Figure 15. State Diagram of Operating Modes Normal Mode Sleep Mode The whole NCV7361A is active. Switching to normal mode can be done via the following actions: • Start of VSUP or after Undervoltage Reset • Rising Edge at EN (EN = High) (Local Wake−Up) • Activity on the LIN Bus (Remote Wake−Up) Sleep mode is most current saving. With a falling edge on EN (EN = Low) the NCV7361A is switched from normal mode into sleep mode. The voltage regulator will be switched off and the LIN transceiver is in recessive state. http://onsemi.com 11 NCV7361A VSUP VSUVR_OFF VSUVR_ON UVR POR POR EN = H/L Normal Mode Sleep Mode UVR Normal Mode VOUT Figure 16. Operating of Power On and Undervoltage RESET Switching into sleep mode can be done independently from the current transceiver state. That means if the transmitter is in dominant state this state will be cancelled and it will be switched to recessive state. independence from the rise time of VSUP. During fast VSUP edges the Power−on−Reset will be active. If the increasing of VSUP is very slow (> 1 ms/V) the undervoltage reset unit initializes the voltage regulator if VSUP > VSUVR_OFF (typical 3.5 V). The effects of both POR circuits at different VSUP slopes as shown in Figure 16. After POR the voltage regulator starts and VOUT will be output. If VOUT > VMRes the bus interface will be activated. If the VOUT voltage level is higher than VRES, the reset time tRes = 100 ms is started. After tRes the RESET output switches from low to high (Figure 16). POR−state This is the power−on−reset state of the NCV7361A, while VSUP < VSUVR_OFF. If the prior state was sleep mode, the NCV7361A switches via the Ini−state to normal mode. Ini−state This is an intermediate state, which will pass through after switch−on of VSUP or VOUT. The NCV7361A remains in this state if VOUT is below VRES (Reset Output = L) and VSUP > VSUVR_ON. Start of Linear Regulator via Wake−Up The initialization is only being done for the VOUT circuitry parts. This procedure begins with leaving the master reset state (VOUT > VMRes) and runs in the same manner as the VSUP − Power−On. Thermal Shutdown If the junction temperature TJ is higher than TJSHD (>155°C), the NCV7361A will be switched into the thermal shutdown mode. The behavior within this mode is comparable with the sleep mode except for LIN transceiver operating. The transceiver is completely disabled, no wake−up functionality is available. If TJ falls below the thermal recovery temperature TJREC (typical 140°C) the NCV7361A will be recover to the previous state (normal or sleep). Wake−Up If the regulator is put into sleep mode it can be “waked−up” with the BUS interface. Every pulse on the BUS (high pulse or low pulse) with a pulse width of minimum 60 s switches on the regulator. After the BUS has “waked−up” the regulator, it can only be switched off with a high level followed by a low level on the EN pin. Initialization VSUP Undervoltage Reset Initialization is started if the power supply is switched on as well as every rising edge on of the NCV7361A via the EN pin. The undervoltage detection unit inhibit an undefined behavior of the NCV7361A under low voltage condition. If VSUP drops below VSUVR_ON (typical 3 V) the undervoltage detection becomes active and the IC will be switched to POR state. The following increasing of VSUP above VSUVR_OFF (typical 3.5 V) cancels this POR state and the voltage regulator starts with the initialization sequence. VSUP − Power On If VSUP is switched on the NCV7361A starts to normal mode via the POR− and Ini−state. A combination of dynamic POR and undervoltage reset circuitry generates a POR signal, which switches the NCV7361A into normal mode. This power on behavior is independent from the status of the EN pin. Power−on−Reset and undervoltage reset operates independent from each other, which secures the VSUP Undervoltage in Normal Mode Supply Voltages below VSUVR_OFF do not influence the voltage regulator. The output voltage VOUT follows VSUP. http://onsemi.com 12 NCV7361A VSUP Undervoltage in Sleep Mode LIN BUS Transceiver No exit from the sleep mode will take place if the VSUP voltage drops down to VSUVR_ON (typical 3.0 V). The undervoltage reset becomes active (POR−state). As a result of this operating, the sleep mode is left to the normal mode. If VSUP rises again above VSUVR_OFF (typical 3.5 V), the IC initializes the voltage regulator and continues to work with the normal mode. The undervoltage reset unit secures stable operating in the undervoltage range of VSUP down to GND level. The dynamic Power−On−Reset secures a defined internal state independent from the duration of the VSUP drop, which secures a stable restart. The NCV7361A is a bidirectional bus interface device for data transfer between the LIN bus and the LIN protocol controller. The transceiver consists of a pnp−driver (1.2 V @ 40 mA) with slew rate control, wave shaping and current limit, and a high voltage receiver/comparator followed by a filter circuit. Transmit Mode During transmission the data at the TxD pin will be transferred to the BUS driver for generating a BUS signal. To minimize the electromagnetic emission of the bus line, the BUS driver has integrated slew rate control and wave shaping circuitry. Transmitting will be interrupted in the following cases: • Sleep Mode • Thermal Shutdown Active • Master Reset (VOUT < 3.15 V) The recessive BUS level is generated from the integrated 30 k pullup resistor in series with a diode This diode prevents reverse current on VBUS when VBUS > VSUP. No additional termination resistor is necessary to use the NCV7361A in LIN slave nodes. If this IC is used for LIN master nodes, it is necessary to terminate the bus pin with an external 1.0 k resistor in series with a diode to VBAT. Overtemperature Shutdown If the junction temperature is 155°C < TJ < 170°C the overtemperature recognition will be activated and the regulator voltage will be switched off. The VOUT voltage drops down, the reset state is entered and the bus−transceiver is switched off (recessive state). After TJ falls below 140°C the NCV7361A will be initialized again (Figure 17) independently from the voltage levels on EN and BUS. Within the thermal shutdown mode the transceiver can not be switched to the normal mode neither with local nor with remote wake−up. The operation of the NCV7361A is possible between TAmax (125°C) and the switch−off temperature, but small parameter differences can appear. After overtemperature switch−off the IC behaves as described in Figure 17. Receive Mode The data signal from the BUS pin will be transferred continuously to the pin RxD. Short spikes on the bus are suppressed by the internal filter circuit ( = 2.8 s). VSUP T>TJ T<TJ t<trr VOUT t<trr VRES tRes trr tRes tRes tRes RESET Initialization Thermal shutdown Spike VSUP Low voltage VSUP Figure 17. RESET Behavior http://onsemi.com 13 Spike VCC Current limitation active NCV7361A VSUP Vthr_max 60% BUS Vthr_hys 50% Vthr_cnt 40% Vthr_min t < tdeb_BUS t < tdeb_BUS RxD Figure 18. Receive Mode Impulse Diagram The receive threshold values Vthr_max and Vthr_min are symmetrical to 0.5*VSUP with a hysteresis of 0.135*VSUP . The LIN specific receive threshold is between 0.4*VSUP and 0.6 * VSUP . The constant slew rate principle holds appropriate voltage levels and can operate within the LIN Protocol Specification for RC oscillator systems with a matching tolerance up to 2% between 2 nodes. Data Rate TxD Input The NCV7361A is a constant slew rate transceiver. The bus driver works with a fixed slew rate range of 1.0 V/s V/T 2.5 V/s. This principle provides good symmetry of the slope times between recessive to dominant and dominant to recessive slopes within the LIN bus load range (CBUS, Rterm). The NCV7361A guarantees data rates up to 20 kb within the complete bus load range under worst case conditions. The 5.0 V input TxD directly controls the BUS level: TxD = low → BUS = low (dominant level) TxD = high → BUS = high (recessive level) The TxD pin has an internal pullup resistor connected to VOUT. This guarantees that an open TxD pin generates a recessive BUS level. MCU NCV7361A VOUT VCC RPU_TxD Typ. 15 k RC Filter (10 ns) IPU_TxD TxD Figure 19. TxD Input Circuitry http://onsemi.com 14 NCV7361A 16 RxD Output The received BUS signal will be output to the 5.0 V RxD pin: BUS < Vthr_cnt – 0.5 * Vthr_hys → RxD = low BUS > Vthr_cnt + 0.5 * Vthr_hys → RxD = high This output is a push−pull driver between VOUT and GND with an output current capability of 1.0 mA. 12 lol_RESET (mA) NCV7361A 14 MCU 10 8 6 4 VOUT 2 RxD 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VOUT (V) Figure 22. Output Current of Reset Output vs. VOUT Voltage Initialization Figure 20. RxD Output Circuitry The initialization is started if VSUP is switched on. This is independent of the EN pin. Linear Regulator VSUP Power ON The NCV7361A has an integrated low dropout linear regulator with a P−Channel MOSFET output driver whose output is 5.0 V 2% at 50 mA and 5.5 V VSUP 18 V. Figure 21 shows typical current limit based on the output voltage. The NCV7361A starts in the normal mode when VSUP is applied [>3.15 V (typical)]. The internal circuitry on VOUT as well as the internal regulator starts the initialization with power−on−reset. The voltage regulator is switched on. If VOUT > VPOR the bus−interface will be activated. If VOUT is higher than VRes, the reset time tRes = 100 ms is started. After tRes the RESET output switches from low to high (Figure 22). The initialization procedure at power on is started independent from the EN state. The regulator can only be turned off with a high level followed by a low level on the EN pin. 120 IVOUT (mA) 100 80 60 Mode Input EN 40 The NCV7361A is switched into the sleep mode when EN goes from high to low. The normal mode will be kept as long as EN = high. The regulator can be turned off by switching EN high to low independent of the state of the bus−transceiver. The EN input is internally pulled down to guarantee a low with no connection. In the high state, the pulldown current will be switched off to reduce the quiescent current. The maximum input voltage is VSUP. The threshold is typical 2.1 V and therefore CMOS levels can be used as input signals. Figure 23 shows the internal circuitry of the EN pin. The EN input is internally pulled down to secure that if this pin is not connected a low level will be generated. It will be used two different pull down current sources for high and low level to minimize the sleep mode current. 20 0 0 1 2 3 4 5 6 VOUT (V) Figure 21. Characteristic of Current Limit vs. Output Voltage RESET RESET switches from low to high if VSUP is switched on and VOUT > VRES for tRes. If VOUT drops below VRES, the RESET output goes from high to low after trr. Short transients will be filtered. The RESET output driver is driven from VOUT to guarantee proper operation. http://onsemi.com 15 NCV7361A The 4 A pulldown current source is used if the input voltage VIN > high level voltage VENH. If the input voltage drops below the low level of EN VENL, the second current source is used. The resulting pulldown current in this case is 100 A. The wide input voltage range allows different EN control possibilities. If the EN input is connected to an CMOS output of the MCU, a falling edge switches the NCV7361A into sleep mode (the regulator is also switched off). The wake−up is only possible via the bus line. 1000 VSUP RIN_HL EN 4 A Enable Voltage Limiter RIN_LH RIN (k) 100 96 A 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VIN (V) Figure 23. EN Input Circuitry Figure 24. RIN Characteristics of EN Input MCU NCV7361A VBAT VSUP + EN CIN LIN−BUS +5 V VOUT RESET GND TxD BUS RxD 200p + Cload Figure 25. EN Controlled via MCU MCU NCV7361A VBAT VSUP + EN CIN LIN−BUS +5 V VOUT RESET GND TxD BUS RxD + 200p Cload Figure 26. Permanent Normal Mode http://onsemi.com 16 NCV7361A Overtemperature Shutdown If the application does not need the wake−up capability of the NCV7361A, a direct connection EN to VSUP is possible. In this case, the NCV7361A operates in permanent normal mode. Also possible is the external (outside of the module) control of the EN line via a VBAT signal. The thermal shutdown threshold is 155°C < TJ < 175°C. When exceeded, the overtemperature shutdown will be active and the regulator voltage will be switched off. VOUT drops down, the reset state is entered and the bus−transceiver is switched off (recessive state). After TJ falls below 140°C, the NCV7361A will be initialized (see Figure 17), independent from the voltage levels on EN and BUS. Within the thermal shutdown mode, the transceiver can’t be switched to the normal mode with local or with remote wake−up. Function of the NCV7361A is possible between TAmax (125°C) and the switch−off temperature, but small parameter differences can appear. After overtemperature switch−off the IC behaves as described in the RESET chapter. Wake−Up If the regulator is in a standby (sleep) mode, it can be woken up with the BUS interface. Every pulse on the BUS (high pulse or low pulse) with a pulse width of minimum 25 s switches on the regulator. After the BUS wake−up for the regulator, it can only be turned off with a high level followed by a low level on the EN pin. http://onsemi.com 17 NCV7361A APPLICATION HINTS LIN System Parameter Bus Loading Requirements Parameter Symbol Min Typ Max Unit VBAT 8.0 − 18 V VDrop_rev 0.4 0.7 1.0 V Voltage Drop at the Series Diode in Pull Up Path VSerDiode 0.4 0.7 1.0 V Battery Shift Voltage VShift_BAT 0 − 0.1 VBAT Ground Shift Voltage VShift_GND 0 − 0.1 VBAT Master Termination Resistor Rmaster 900 1000 1100 Slave Termination Resistor Rslave 20 30 60 k Number of System Nodes N 2 − 16 − LENBUS − − 40 m Operating Voltage Range Voltage Drop of Reverse Protection Diode Total Length of Bus Line Line Capacitance CLINE − 100 150 pF/m Capacitance of Master Node CMaster − 220 − pF Capacitance of Slave Node CSlave − 220 250 pF Total Capacitance of the Bus including Slave and Master Capacitance CBUS 1.0 4.0 10 nF RNetwork 537 − 863 1.0 − 5.0 s Network Total Resistance Time Constant of Overall System than 700 . Even if the total network capacitance is below or equal to the maximum specified value of 10 nF, the network time constant is higher than 7.0 s. This problem can be solved only by adjusting the master termination resistor to the required maximum network time constant of 5.0 s (max). The LIN bus output driver of the NCV7361A provides a higher drive capability than necessary (40 mA @ 1.2 V) within the LIN standard (33.6 mA @ 1.2 V). With this driver stage the system designer can increase the maximum LIN networks with a total network capacitance of more than 10 nF. The total network resistance can be decreased to: Recommendations for System Design The goal of the LIN physical layer standard is to have a universal definition of the LIN system for plug and play solutions in LIN networks up to 20 kbd bus speeds. In case of small and medium LIN networks, it’s recommended to adjust the total network capacitance to at least 4.0 nF for good EMC and EMI behavior. This can be done by setting only the master node capacitance. The slave node capacitance should have a unit load of typically 220 pF for good EMC/EMI behavior. In large networks with long bus lines and the maximum number of nodes, some system parameters can exceed the defined limits and the LIN system designer must intervene. The whole capacitance of a slave node is not only the unit load capacitor itself. Additionally, there is the capacitance of wires and connectors, and the internal capacitance of the LIN transmitter. This internal capacitance is strongly dependent on the technology of the IC manufacturer and should be in the range of 30 pF to 150 pF. If the bus lines have a total length of nearly 40m, the total bus capacitance can exceed the LIN system limit of 10 nF. A second parameter of concern is the integrated slave termination resistor tolerance. If most of the slave nodes have a slave termination resistance near by the allowed maximum of 60 k, the total network resistance is more Rtl_min (VBat_max VBUSdom)IBUS_max (18 V 1.2 V)40 mA 420 NOTE: The NCV7361A meets the requirements for implementation in RC−based slave nodes. The LIN Protocol Specification requires the deviation of the slave node clock to the master node clock after synchronization must not differ by more than 2%. Setting the network time constant is necessary in large networks (primary resistance) and also in small networks (primary capacitance). http://onsemi.com 18 NCV7361A MIN/MAX SLOPE TIME CALCULATION VBUS 100% 95% 60% BUS 40% 5% Vdom 0% tsdom tsrec Figure 27. Slope Time Calculation 50 The slew rate of the bus voltage is measured between 40% and 60% of the output voltage swing (linear region). The output voltage swing is the difference between dominant and recessive bus voltage. 45 40 35 PD (mW) dVdt 0.2 * Vswing(t40%−t60%) The slope time is the extension of the slew rate tangent until the upper and lower voltage swing limits: tslope 5 * (t40%−t60%) 30 25 20 15 The slope time of the recessive to dominant edge is directly determined by the slew rate control of the transmitter: 10 tslope VswingdVdt 0 5 5 The dominant to recessive edge is influenced from the network time constant and the slew rate control, because it’s a passive edge. In case of low battery voltages and high bus loads the rising edge is only determined by the network. If the rising edge slew rate exceeds the value of the dominant one, the slew rate control determines the rising edge. 6 7 8 9 10 11 12 13 14 15 16 17 18 19 VSUP (V) Figure 28. Power Dissipation LIN Transceiver @ 20 kbit The permitted package power dissipation can be calculated: T TA PDmax J RJ−A Power Dissipation and Operating Range The max power dissipation depends on the thermal resistance of the package and the PCB, the temperature difference between Junction and Ambient as well as the airflow. The power dissipation can be calculated with: If we consider that PD_TX_max = f(VSUP), it can be calculated the max output current IVOUT on VOUT: TJ−TA IVOUTmax RJ−A PD (VSUP VOUT) * IVOUT PD_TX PD_TX_max @ VSUP VSUP VOUT TJ−TA is the temperature difference between junction and ambient, and Rth is the thermal resistance of the package. The thermal energy is transferred via the package and the pins to the ambient. This transfer can be improved with additional ground areas on the PCB as well as ground areas under the IC. The power dissipation of the transmitter PD_TX depends on the transceiver configuration and its parameters as well as on the bus voltage VBUS = VBAT − VD, the resulting termination resistance RL, the capacitive bus load CL and the bit rate. Figure 28 shows the dependence of power dissipation of the transmitter as function of VSUP. The conditions for calculation the power dissipation was: RL = 500 , CL = 10 nF, Bitrate = 20 kbit and duty cycle on TxD of 50%. http://onsemi.com 19 NCV7361A Table 1. SO−8 Thermal RC Network Models* 54 mm2 Copper Area (1 oz thick) (SPICE Deck Format) 714 mm2 54 mm2 Cauer Network 714 mm2 Foster Network 54 mm2 714 mm2 Units Tau Tau Units C_C1 Junction GND 1.08E−05 1.08E−05 W−s/C 1.00E−06 1.00E−06 sec C_C2 node1 GND 4.10E−05 4.10E−05 W−s/C 1.00E−05 1.00E−05 sec C_C3 node2 GND 1.13E−04 1.13E−04 W−s/C 1.00E−04 1.00E−04 sec C_C4 node3 GND 4.42E−04 4.40E−04 W−s/C 5.00E−04 5.00E−04 sec C_C5 node4 GND 1.74E−03 1.71E−03 W−s/C 1.00E−03 1.00E−03 sec C_C6 node5 GND 1.39E−03 1.34E−03 W−s/C 1.00E−02 1.00E−02 sec C_C7 node6 GND 2.08E−02 1.78E−02 W−s/C 1.00E−01 1.00E−01 sec C_C8 node7 GND 1.08E−02 9.75E−03 W−s/C 1.00E+00 1.00E+00 sec C_C9 node8 GND 1.14E−01 1.84E−01 W−s/C 1.00E+01 1.00E+01 sec C_C10 node9 GND 8.11E−01 3.00E+00 W−s/C 5.00E+01 5.00E+01 sec R’s R’s R_R1 Junction node1 0.119 0.119 C/W 0.070 0.070 C/W R_R2 node1 node2 0.286 0.286 C/W 0.152 0.152 C/W R_R3 node2 node3 0.857 0.859 C/W 0.481 0.481 C/W R_R4 node3 node4 1.181 1.189 C/W 0.690 0.690 C/W R_R5 node4 node5 1.241 1.276 C/W 0.584 0.584 C/W R_R6 node5 node6 2.574 2.690 C/W 3.223 3.223 C/W R_R7 node6 node7 18.065 21.708 C/W 0.823 0.823 C/W R_R8 node7 node8 27.965 26.035 C/W 26.801 35.166 C/W R_R9 node8 node9 80.896 49.821 C/W 63.710 52.538 C/W R_R10 node9 GND 49.468 15.252 C/W 86.119 25.510 C/W *Bold face items in the tables above represent the package without the external thermal system. The Cauer networks generally have physical significance and may be divided between nodes to separate thermal behavior due to one portion of the network from another. The Foster networks, though when sorted by time constant (as above) bear a rough correlation with the Cauer networks, are really only convenient mathematical models. Cauer networks can be easily implemented using circuit R1 Junction C1 R2 C2 simulating tools, whereas Foster networks may be more easily implemented using mathematical tools (for instance, in a spreadsheet program), according to the following formula: R(t) n −ttaui Ri 1−e i1 R3 Rn Cn C3 Time constants are not simple RC products. Amplitudes of mathematical solution are not the resistance values. Ambient (thermal ground) Figure 29. Grounded Capacitor Thermal Network (“Cauer” Ladder) Junction R1 R2 R3 Rn C1 C2 C3 Cn Each rung is exactly characterized by its RC−product time constant; Amplitudes are the resistances Figure 30. Non−Grounded Capacitor Thermal Ladder (“Foster” Ladder) http://onsemi.com 20 Ambient (thermal ground) NCV7361A 190 180 JA (°C/W) 170 160 1.0 oz. Cu 150 140 2.0 oz. Cu 130 120 110 100 0 100 200 300 400 500 600 700 800 Copper Area (mm2) Figure 31. SO−8, JA as a Function of the Pad Copper Area Including Traces, Board Material 1000 Cu Area = 53.9 mm2 1.0 oz. Cu Area = 89.7 mm2 1.0 oz. R (°C/W) 100 Cu Area = 713.9 mm21.0 oz. 10 1 0.1 0.01 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 Time (s) Figure 32. SO−8 Thermal Transient Response on Typical Test Boards R (°C/W) EFFECTIVE THERMAL RESISTANCE 1000 Cu Area = 713.9 mm21.0 oz. 100 50% Duty Cycle 10% 10 5% 2% Notes: 1 1% PDM t1 t2 0.1 t1 Duty Cycle, D = t 2 Single Pulse 0.01 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 Time (s) Figure 33. SO−8 Thermal Duty Cycle Curves on 1.0 in. Spreader Test Board http://onsemi.com 21 100 1000 NCV7361A 60 Input Capacity on VSUP CIN It is necessary to have an input capacity of CIN = 4.7 F. Higher capacity values improve the line transient response and the supply noise rejection behavior. The combination of electrolytic capacity (e.g.100 F) in parallel with a ceramic RF−capacity (e.g. 100 nF) archives good disturbance suppressing. The input capacity should be placed as close as possible (< 1 cm) to the VSUP pin. maximum current 40 SOIC8 TA = 85°C TJ = 150°C SOIC8 TA = 125°C TJ = 150°C 30 20 SOIC8 TA = 85°C TJ = 125°C 10 max. supply voltage IVCC_max (mA) 50 Load Capacity on VOUT CL The regulator is stabilized by the output capacitor CL. The NCV7361A requires a minimum of 4.7 F capacity connected to the 5.0 V output to insure stability. This capacitor should maintain its ESR in the stable region of the ESR curve (Figure 35) over the full operating temperature range of the application. The capacity value and the ESR of a capacitor changes with temperature. The minimal capacity value must be kept within the whole operating temperature range. 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 VSUP (V) Figure 34. Safe Operating Area The linear regulator of the NCV7361A operates with input voltages up to 18 V and can output a current of 50 mA. The maximum power dissipation limits the maximum output current at high input voltages and high ambient temperatures. The output current of 50 mA at an ambient temperature of TA = 125°C is only possible with small voltage differences between VSUP and VCC. See Figure 34 for safe operating areas for different ambient and junction temperatures. Example 1: The regulator is stabilized using a 47 F aluminum electrolytic capacitor load (ESR = 0.7 @ 25°C). The capacitance decreases to 42 F and the ESR increases to 8.9 at an ambient temperature of −40°C. The ESR value is located in the unstable region. The regulator will be unstable at −40°C. Regulator Circuitry Example 2: The regulator is stabilized using a 47 F tantalum capacitor load (ESR = 0.1 @ 25°C). The capacitance decreases to 45 F and the ESR increases to 0.11 at an ambient temperature of −40°C. The ESR value is located in the stable region. The regulator will be stable at −40°C. Low Dropout Regulator The voltage regulator of the NCV7361A is a low dropout regulator (LDO) with a P−MOSFET as the driving transistor. This type of regulator has a standard pole, generated from the internal frequency compensation and an additional pole, which is dependent from the load and the load capacity. This additional pole can cause an instable behavior of the regulator! It requires a zero point to compensate this additional pole. It can be realized via an additional load resistor in series with a load capacity. It is used for this compensation the Equivalent Series Resistance (ESR) of the load capacity. Every real capacity is characterized with an ESR value. With the help of this ESR value an additional zero point is implemented into the amplification loop and therefore the result of the negative phase shift is compensated. Because of this correlation the regulator has a stable operating area which is defined by the load resistance RL, the load capacity CL and the corresponding ESR value. The load resistance resp. load current is defined by the application itself and therefore the compensation of the pole can only be done via variation of the load capacity and ESR value. ESR @ 100 kHz (Ohm) 100 Unstable Region 10 1 Stable Region 0.1 Unstable Region 0.01 0 10 20 30 40 50 Load Current (mA) Figure 35. ESR Curves for 6.8 F CL 100 F and Frequency of 100 kHz The value and type of the output capacitor can be selected by using the diagram shown in Figure 35. http://onsemi.com 22 NCV7361A Capacity Value Normally the specified ESR values for a capacitor is valid at a temperature of TA = 25°C and a frequency of f = 100 kHz. The temperature coefficient is negative, which means with increasing of the temperature the ESR value decreases. In the choice of the capacity has to be taken into account that the ESR can decrease at TA = −40°C dramatically that the valid operating area can be left, which causes that the regulator will be instable. The capacity value of an electrolytic capacitor is dependence from the voltage, temperature and the frequency. The temperature coefficient of the capacity value is positive, that means that the value increases with increasing of the temperature. The capacity value decreases with increasing of the frequency. This behavior of a capacitor can cause that at TA = −40°C the capacity value falls below the minimum required capacity for the regulator. In this case the regulator becomes instable, which means the regulator starts oscillation. The nominal value of the capacitor at TA = 25°C has to be chosen with enough margin under consideration of the capacitor specification. The instable behavior will be amplified because of the decreasing of the capacity with this oscillation. Tantalum Capacitors This type of capacitor has a low dependence of the capacity and the ESR from the temperature and is therefore well suitable as VOUT load capacity. Aluminum Capacitors These capacitors show a strong influence of the capacity and the ESR from the temperature. These characteristic restrains the usability as load capacity for the low drop regulator of NCV7361A. ESR The Equivalent Serial Resistance is the resistor part of the equivalent circuit diagram of a capacitor. The ESR value is dependent from the temperature and frequency. Reverse Protection−Diode VBAT VSUP + 100 F C NCV7361A 100 nF LIN−BUS +5 V VOUT EN RESET GND TxD BUS RxD + 220 pF 10 F...100 F 100 nF or Optional 33 H 10 RC−Filter 100 p LC−Filter 82p Figure 36. Application Circuit (Slave Node) EMI Suppressing filter capacitor influences the effectiveness of the EMI suppressing in conformance to the maximum LIN bus capacity of 10 nF. LC−filters or RC−filters can also be used. The value of C, L or R, depends on the corner frequency, the maximum LIN bus capacity (10 nF) and the compliance with the DC− and AC LIN bus parameters. To minimize the influence of EMI from the bus line, a 220 pF capacitor should be directly connected to the BUS pin (see Figure 36). The value of the filter capacity can be adjusted to the size of the LIN network. 220 pF should be used for bigger networks. Values from 333 pF up to 1.0 nF should be used for middle to small LIN networks. Finally the size of the http://onsemi.com 23 NCV7361A VBAT VIN + VOUT 100nF + 100F GND 100nF +5 V 100nF NCV7380* 1k 220pF NC RxD VS NC BUS VCC GND TxD P 100nF LIN−BUS Master Node NCV7361A VSUP + 100F +5 V VOUT 1k 100nF 100nF EN RESET GND TxD BUS RxD C 220pF + 100F 100nF Slave Node *Not representative of actual pinout. Figure 37. Application Circuit for LIN Sub−Bus with NCV7361A as Slave Node http://onsemi.com 24 NCV7361A Connection to Flash−MCU diode must be used between the MCU and the RxD pin to avoid loading of the programming data. The programming of the flash is also possible via the LIN pin, if the MCU supports this kind of flash mode. During programming of a flash MCU the NCV7361A should be disconnected from the MCU. This can be done by disconnecting the supply voltage of the NCV7361A or by turning off the NCV7361A with the EN pin. A blocking Prog.−Data 10F...47F NCV7361A + VOUT C 47nF...100nF RESET TxD RxD 0.7 V Vhigh_RxD > 4.7 V at VDD = 5 V Vlow_RxD = 0.8 V Vhigh = 4 V at VDD = 5 V Figure 38. Example Circuitry for Connection of RxD to MCU for Flash Programming Operating During Disturbance Short Circuit VOUT to GND Operating Without VSUP or GND The VOUT pin is protected via a current limit. This state is comparable with the behavior in the sleep mode. The BUS pin is designed for voltages of GND − 24 V up to GND + 30 V. This prevents loss of communication between other bus nodes with the loss of VSUP or loss of GND. The BUS pin will remain at VBAT and current draw will be minimal with the loss of GND or VSUP. Overload of VOUT Thermal Switch−Off The power dissipation is increasing if the load current is between IVOUT_max and ILVOUT. If the IC exceeds the thermal shutdown threshold of > 155°C, the transceiver will be switched off. The voltage regulator will also be switched off and a reset signal is forced. Short Circuit BUS to VBAT • Recessive • Dominant LIN bus is blocked, no influence to the NCV7361A Current limit, thermal shutdown of NCV7361A if power dissipation raises TJ Overcurrent If the current limit is active the voltage on VOUT drops down. If this voltage is below the threshold VRES, a reset will be forced. Short Circuit BUS to GND The LIN bus is blocked. There is no influence to the NCV7361A. Undervoltage VSUP, VOUT The reset circuit guarantees the correct behavior of the driver during undervoltage. The BUS pin generates the recessive state if VOUT < VMRes. The inputs EN and TxD have pull−down and pull−up circuits respectively. If VMRes VOUT 4.5 V the TxD signal is transmitted to the bus. The receive mode is also active. Short Circuit TxD to GND The LIN transceiver is permanent in the dominant state as is the LIN bus. This state can only be detected from the LIN controller. In this case the controller must switch−off the LIN node via the EN input of the NCV7361A and look for a recessive state. A thermal shutdown of NCV7361A will appear if the thermal shutdown threshold is exceeded. Short Circuit RxD, RESET to GND or VOUT Both outputs are short circuit proof to VOUT and ground. TxD Open The internal pullup resistor forces the LIN node to the recessive state. The communication between the other bus−nodes will not be disturbed. http://onsemi.com 25 NCV7361A ESD/EMC Remarks ESD Test General Remarks The NCV7361A is tested according to MIL883−3015.7 (Human Body Model). Electronic semiconductor products are sensitive to Electro Static Discharge (ESD). Always observe Electro Static Discharge control procedures whenever handling semiconductor products. EMC The test on EMC impacts is done according to ISO 7637−1 for power supply pins and ISO 7637−3 for data and signal pins. POWER SUPPLY PIN VSUP Test Pulse Condition Duration 1 t1 = 5.0 s/US = −100 V/tD = 2.0 ms 5000 Pulses 2 t1 = 0.5 s/US = 100 V/tD = 0.05 ms 5000 Pulses 3a/b 5 US = −150 V/US = 100 V Burst 100 ns/10 ms/90 ms Break Ri = 0.5 , tD = 400 ms tr = 0.1 ms/UP + US = 40 V 1h 10 Pulses Every 1 Min DATA AND SIGNAL PINS EN, BUS Test Pulse Condition Duration 1 t1 = 5.0 s/US = −100 V/tD = 2.0 ms 1000 Pulses 2 t1 = 0.5 s/US = 100 V/tD = 0.05 ms 1000 Pulses 3a/b US = −150 V/US = 100 V Burst 100 ns/10 ms/90 ms Break http://onsemi.com 26 1000 Burst NCV7361A PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. −X− A 8 5 0.25 (0.010) S B 1 M Y M 4 K −Y− G C N X 45 SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S RECOMMENDED FOOTPRINT 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 http://onsemi.com 27 mm inches DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0 8 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 8 0.010 0.020 0.228 0.244 NCV7361A ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Phone: 81−3−5773−3850 Email: [email protected] http://onsemi.com 28 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. NCV7361A/D