MOTOROLA SEMICONDUCTOR TECHNICAL DATA 2.5V and 3.3V CMOS PLL Clock Generator and Driver The MPC9315 is a 2.5V and 3.3V compatible, PLL based clock generator designed for low-skew clock distribution in low-voltage mid-range to high-performance telecom, networking and computing applications. The MPC9315 offers 8 low-skew outputs and 2 selectable inputs for clock redundancy. The outputs are configurable and support 1:1, 2:1, 4:1, 1:2 and 1:4 output to input frequency ratios. In addition, a selectable output 180° phase control supports advanced clocking schemes with inverted clock signals. The MPC9315 is specified for the extended temperature range of –40 to +85°C. Order Number: MPC9315/D Rev 2, 02/2002 MPC9315 LOW VOLTAGE 2.5V AND 3.3V PLL CLOCK GENERATOR Features • Configurable 8 outputs LVCMOS PLL clock generator • Compatible to various microprocessor such as PowerQuicc I and II • Wide range output clock frequency of 18.75 to 160 MHz • 2.5V and 3.3V CMOS compatible • Designed for mid-range to high-performance telecom, networking and computer applications • Fully integrated PLL supports spread spectrum clocking • Supports applications requiring clock redundancy • Max. output skew of 120 ps (80 ps within one bank) • Selectable output configurations (1:1, 2:1, 4:1, 1:2, 1:4 frequency ratios) FA SUFFIX LQFP PACKAGE CASE 873A–02 • 2 selectable LVCMOS clock inputs • External PLL feedback path and selectable feedback configuration • Tristable outputs • 32 ld LQFP package • Ambient operating temperature range of –40 to +85°C Functional Description The MPC9315 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock. Normal operation requires a connection of one of the device outputs to the selected feedback (FB0 or FB1) input to close the PLL feedback path. The reference clock frequency and the output divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. With available output dividers of divide-by-1, divide-by-2 and divide-by-4 the internal VCO of the MPC9315 is running at either 1x, 2x or 4x of the reference clock frequency. The frequency of the QA, QB, QC output groups is either the equal, one half or one fourth of the selected VCO frequency and can be configured for each output bank using the FSELA, FSELB and FSELC pins, respectively. The available output to input frequency ratios are 4:1, 2:1, 1:1, 1:2 and 1:4. The REF_SEL pin selects one of the two available LVCMOS compatible reference input (CLK0 and CLK1) supporting clock redundant applications. The selectable feedback input pin allows the user to select different feedback configurations and input to output frequency ratios. The MPC9315 also provides a static test mode when the PLL supply pin (VCCA) is pulled to logic low state (GND). In test mode, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The test mode is intended for system diagnostics, test and debug purpose. This test mode is fully static and the minimum clock frequency specification does not apply. The outputs can be disabled by deasserting the OE pin (logic high state). In PLL mode, deasserting OE causes the PLL to lose lock due to no feedback signal presence at FB0 or FB1. Asserting OE will enable the outputs and close the phase locked loop, also enabling the PLL to recover to normal operation. The MPC9315 is fully 2.5V and 3.3V compatible and requires no external loop filter components. All inputs accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission lines. For series terminated transmission lines, each of the MPC9315 outputs can drive one or two traces giving the devices an effective fanout of 1:18. The device is packaged in a 7x7 mm2 32-lead LQFP package. The fully integrated PLL of the MPC9315 allows the low skew outputs to lock onto a clock input and distribute it with essentially zero propagation delay to multiple components on the board. In zero-delay buffer mode, the PLL minimizes phase offset between the outputs and the reference signal. Motorola, Inc. 2002 1 MPC9315 VCCA VCC 6 CLK0 CLK1 (pulldown) Bank A 0 PLL Ref (pulldown) 0 0 CLK ÷ 2 1 1 QA0 1 FB REF_SEL CLK (pulldown) QA1 75 - 160 MHz Bank B CLK ÷ 4 QB0 FB0 FB1 FB_SEL (pulldown) 0 (pulldown) 1 0 QB1 1 QB2 (pulldown) QB3 FSELA PSELA FSELB FSELC OE (pulldown) (pulldown) Bank C (pullup) 0 QC0 1 QC1 (pullup) (pulldown) GND 6 The MPC9315 requires an external RC filter for the analog power supply pin VCCA. Please see application section for details. VCC QB0 GND QB1 VCC QB2 GND QB3 Figure 1. MPC9315 Logic Diagram 24 23 22 21 20 19 18 17 GND 25 16 VCC QA1 26 15 QC0 QA0 27 14 QC1 VCC 28 13 GND MPC9315 FSELC 29 12 OE FSELB 30 11 PSELA FSELA 31 10 FBSEL GND 32 2 3 4 5 6 7 8 VCC CLK0 REF_SEL CLK1 VCCA FB0 FB1 GND 9 1 VCC Figure 2. Pinout: 32–Lead Package Pinout (Top View) MOTOROLA 2 TIMING SOLUTIONS MPC9315 PIN CONFIGURATION Pin I/O Type Function CLK0 Input LVCMOS Reference clock input CLK1 Input LVCMOS Alternative clock input FB0 Input LVCMOS PLL feedback input FB1 Input LVCMOS Alternative feedback input REF_SEL Input LVCMOS Selects clock input reference clock input, default low (pull-down) FB_SEL Input LVCMOS Selects PLL feedback clock input, default low (pull-down) FSELA Input LVCMOS Selects divider ratio of bank A outputs, default low (pull-down) FSELB Input LVCMOS Selects divider ratio of bank B outputs, default low (pull-up) FSELC Input LVCMOS Selects divider ratio of bank C outputs, default low (pull-up) PSELA Input LVCMOS Selects phase of bank A outputs QA0, QA1 Output LVCMOS Bank A outputs QB0 to QB3 Output LVCMOS Bank B outputs QC0, QC1 Output LVCMOS Bank C outputs OE Input LVCMOS Output tristate VCCA Supply Analog (PLL) positive supply voltage. Requires external RC filter VCC Supply Digital positive supply voltage GND Ground Digital negative supply voltage (ground) FUNCTION TABLE Control Default REF_SEL 0 CLK0 0 CLK1 1 FB_SEL 0 FB0 FB1 FSELA 0 QAx = VCO clock frequency QA0, QA1 = VCO clock frequency ÷ 2 FSELB 1 QBx = VCO clock frequency QB0 - QB3 = VCO clock frequency ÷ 2 FSELC 1 QCx = VCO clock frequency ÷ 2 QC0, QC1 = VCO clock frequency ÷ 4 PSELA 0 0° (QA0, QA1 non-inverted) 180° (QA0, QA1 inverted) VCCA none VCCA = GND, PLL off and bypassed for static test and diagnosis VCCA = 3.3 or 2.5V, PLL enabled MR 0 Normal operation Reset (VCO clamped to min. range) OE 0 Outputs enabled Outputs disabled (tristate), open PLL loop ABSOLUTE MAXIMUM RATINGSa Symbol Characteristics Min Max Unit VCC VIN Supply Voltage -0.3 4.6 V DC Input Voltage -0.3 -0.3 VCC+0.3 VCC+0.3 V DC Output Voltage ±20 mA ±50 mA 125 °C VOUT IIN DC Input Current IOUT TS DC Output Current Storage temperature -55 Condition V a. Absolute maximum continuos ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. GENERAL SPECIFICATIONS Symbol Characteristics Min Typ Max Unit Output Termination Voltage ESD (Machine Model) 200 HBM ESD (Human Body Model) 2000 V Latch–Up 200 mA LU CPD VCC B2 VTT MM V Power Dissipation Capacitance CIN TIMING SOLUTIONS Condition V 3 10 pF Per output 4.0 pF Inputs MOTOROLA MPC9315 DC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = –40° to 85°C) Symbol Characteristics VIH Input High Voltage VIL Input Low Voltage VOH Output High Voltage VOL Output Low Voltage ZOUT Output Impedance IIN ICCA Min Typ 2.0 Max Unit VCC + 0.3 V LVCMOS 0.8 V LVCMOS V IOH=-24 mAa IOL= 24mAa IOL= 12mA 2.4 0.55 0.30 Maximum PLL Supply Current 3.5 V V W 14 - 17 Input Currentb Condition ±200 µA VIN = VCC or GND 7.0 mA VCCA Pin ICCQ Maximum Quiescent Supply Current 1.0 mA All VCC Pins a. The MPC9315 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines. b. Inputs have pull–up or pull–down resistors affecting the input current. AC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = –40° to 85°C)a Symbol Characteristics Min ÷1 feedback ÷2 feedback ÷4 feedback fref Input Frequency fVCO VCO Lock Range fMAX Maximum Output Frequency frefDC Reference Input Duty Cycle PLL bypass mode ÷1 output ÷2 output ÷4 output tr, tf CLK0, CLK1 Input Rise/Fall Time t(∅) Propagation Delay (Static Phase Offset) tSK(∅) CLK0 or CLK1 to FB Output-to-Output Skew Max Unit 100c 37.50 18.75 160 80 40 MHz MHz MHz PLL locked PLL locked PLL locked 0 75c TBD MHz VCCA = GND 160 MHz 75 37.50 18.75 160 80 40 MHz MHz MHz 25 75 % 1.0 ns 0.8 to 2.0V –150 +150 ps PLL locked 80 120 ps ps Within one bank Any output DC Output Duty Cycle 45 tr, tf Output Rise/Fall Time 0.1 tPLZ, HZ tPZL, LZ BW tJIT(CC) tJIT(PER) tJIT(∅) Typ 55 % 1.0 ns Output Disable Time 10 ns Output Enable Time 10 ns PLL closed loop bandwidth Cycle-to-Cycle Jitter Period Jitter I/O Phase Jitter ÷1 feedback ÷2 feedback ÷4 feedback 50 TBD 2.0 – 20 0.6 – 6.0 s (1s) (1s) (1 ) 10 Condition 0.55 to 2.4V MHz MHz MHz 22 ps RMS value 8.0 15 ps RMS value 8.0 – 25b TBD ps RMS value tLOCK Maximum PLL Lock Time 1.0 ms a. AC characteristics apply for parallel output termination of 50Ω to VTT. b. I/O jitter depends on VCO frequency. Please see application section for I/O jitter versus VCO frequency characteristics. c. The VCO range in ÷1 feedback configuration (e.g. QAx connected to FBx and FSELA = 0) is limited to 100 ≤ fVCO ≤ 160 MHz. Please see next revision of the MPC9315 for improved VCO frequency range. MOTOROLA 4 TIMING SOLUTIONS MPC9315 DC CHARACTERISTICS (VCC = 2.5V ± 5%, TA = –40° to 85°C) Symbol Characteristics VIH Input High Voltage VIL Input Low Voltage VOH Output High Voltage VOL Output Low Voltage ZOUT Output Impedance IIN ICCA Min Typ 1.7 Max Unit VCC + 0.3 V LVCMOS 0.7 V LVCMOS V IOH=-15 mAa V IOL= 15 mA 1.8 0.6 W 17 - 20 Input Currentb Maximum PLL Supply Current Condition 2.0 ±200 µA VIN = VCC or GND 5.0 mA VCCA Pin ICCQ Maximum Quiescent Supply Current 1.0 mA All VCC Pins a. The MPC9315 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines per output. b. Inputs have pull–up or pull–down resistors affecting the input current. AC CHARACTERISTICS (VCC = 2.5V ± 5%, TA = –40° to 85°C)a Symbol Characteristics Min ÷2 feedback ÷4 feedback fref Input Frequencyc fVCO VCO Lock Range fMAX Maximum Output Frequency frefDC Reference Input Duty Cycle PLL bypass mode ÷1 output ÷2 output ÷4 output tr, tf CLK0, CLK1 Input Rise/Fall Time t(∅) Propagation Delay (Static Phase Offset) tSK(∅) CLK0 or CLK1 to FB Output-to-Output Skew PLL locked PLL locked VCCA = GND MHz MHz 75 37.50 18.75 160 80 50 MHz MHz MHz 25 75 % 1.0 ns 0.7 to 1.7V –150 +150 ps PLL locked 80 120 ps ps Within one bank Any output 45 0.1 55 % 1.0 ns tPLZ, HZ tPZL, LZ Output Disable Time 12 ns Output Enable Time 12 ns PLL closed loop bandwidth Condition TBD Output Rise/Fall Time tJIT(∅) MHz MHz 160c Output Duty Cycle tJIT(CC) Unit 80 40 0 DC tJIT(PER) Max 75c tr, tf BW Typ 37.50 18.75 ÷2 feedback ÷4 feedback 50 1.0 – 10 0.4 – 3.0 s s (1s) 0.55 to 2.4V MHz MHz Cycle-to-Cycle Jitter (1 ) 10 22 ps RMS value Period Jitter (1 ) 8.0 15 ps RMS value 10 – 25b TBD ps RMS value I/O Phase Jitter tLOCK Maximum PLL Lock Time 1.0 ms a. AC characteristics apply for parallel output termination of 50Ω to VTT. b. I/O jitter depends on VCO frequency. Please see application section for I/O jitter versus VCO frequency characteristics. c. ÷1 feedback is not available for VCC = 2.5V operation. Please see next revision of the MPC9315 for the ÷1 feedback option at 2.5V supply. TIMING SOLUTIONS 5 MOTOROLA MPC9315 APPLICATIONS INFORMATION ratios of the reference clock input to the outputs are 1:1, 1:2, 1:4 as well as 2:1 and 4:1, Table 1, Table 2 and Table 3 illustrate the various output configurations and frequency ratios supported by the MPC9315. PSELA controls the output phase of the QA0 and QA1 outputs, allowing the user to generate inverted clock signals synchronous to non-inverted clock signals. See also “Example Configurations for the MPC9315” on page 8 for further reference. Programming the MPC9315 The PLL of the MPC9315 supports output clock frequencies from 18.75 to 160 MHz. Different feedback and output divider configurations can be used to achieve the desired input to output frequency relationship. The feedback frequency and divider should be used to situate the VCO in the frequency range between 75 and 160 MHz for stable and optimal operation. The FSELA, FSELB, FSELC pins select the desired output clock frequencies. Possible frequency Table 1: Output Frequency Relationship for QA0 connected to FB0a Inputs Outputs FSELA FSELB FSELC QA0, QA1 QB0-QB3 QC0, QC1 0 0 0 CLK CLK CLK ÷ 2 0 0 1 CLK CLK CLK ÷ 4 0 1 0 CLK CLK ÷ 2 CLK ÷ 2 0 1 1 CLK CLK ÷ 2 CLK ÷ 4 1 0 0 CLK 2 * CLK CLK 1 0 1 CLK 2 * CLK CLK ÷ 2 1 1 0 CLK CLK CLK 1 1 1 CLK CLK CLK ÷ 2 a. Output frequency relationship with respect to input reference frequency CLK. Table 2: Output Frequency Relationship for QB0 connected to FB0a Inputs Outputs FSELA FSELB FSELC QA0, QA1 QB0-QB3 QC0, QC1 0 0 0 CLK CLK CLK ÷ 2 0 0 1 CLK CLK CLK ÷ 4 0 1 0 2 * CLK CLK CLK 0 1 1 2 * CLK CLK CLK ÷ 2 1 0 0 CLK ÷ 2 CLK CLK ÷ 2 1 0 1 CLK ÷ 2 CLK CLK ÷ 4 1 1 0 CLK CLK CLK 1 1 1 CLK CLK CLK ÷ 2 a. Output frequency relationship with respect to input reference frequency CLK. Table 3: Output Frequency Relationship for QC0 connected to FB0a Inputs Outputs FSELA FSELB FSELC QA0, QA1 QB0-QB3 QC0, QC1 0 0 0 2 * CLK 2 * CLK CLK 0 0 1 4 * CLK 4 * CLK CLK 0 1 0 2 * CLK CLK CLK 0 1 1 4 * CLK 2 * CLK CLK 1 0 0 CLK 2 * CLK CLK 1 0 1 2 * CLK 4 * CLK CLK 1 1 0 CLK CLK CLK 1 1 1 2 * CLK 2 * CLK CLK a. Output frequency relationship with respect to input reference frequency CLK. MOTOROLA 6 TIMING SOLUTIONS MPC9315 Example Configurations for the MPC9315 Figure 3. MPC9315 Default Configuration fref = 80 MHz CLK0 CLK1 REF_SEL FB0 FB1 FBSEL FSELA FSELB FSELC PSELA QA0 QA1 160 MHz QB0 QB1 QB2 QB3 80 MHz QC0 QC1 40 MHz Figure 4. MPC9315 Zero Delay Buffer Configuration fref = 75 MHz CLK0 CLK1 REF_SEL FB0 FB1 FBSEL FSELA FSELB FSELC PSELA 1 0 MPC9315 QA0 QA1 75 MHz QB0 QB1 QB2 QB3 75 MHz QC0 QC1 75 MHz MPC9315 80 MHz (Feedback) 75 MHz (Feedback) MPC9315 default configuration (feedback of QB3 = 100 MHz). All control pins are left open. MPC9315 1:1 frequency configuration (feedback of QB3 = 75 MHz). FSELA = H, FSELC = L. All other control pins are left open. Frequency range Min Max Frequency range Min Max Input 37.50 MHz 80 MHz Input 37.50 MHz 80 MHz QA outputs 75.00 MHz 160 MHz QA outputs 37.50 MHz 80 MHz QB outputs 37.50 MHz 80 MHz QB outputs 37.50 MHz 80 MHz QC outputs 18.75 MHz 40 MHz QC outputs 37.50 MHz 80 MHz Figure 5. MPC9315 180° Phase Inversion Configuration fref = 33 MHz CLK0 CLK1 REF_SEL FB0 FB1 FBSEL 1 FSELA FSELB FSELC PSELA 1 QA0 QA1 66 MHz inv, QB0 QB1 QB2 QB3 66 MHz QC0 QC1 33 MHz Figure 6. MPC9315 x4 Multiplier Configuration fref = 19 MHz CLK0 CLK1 REF_SEL FB0 FB1 FBSEL QB0 QB1 QB2 QB3 38 MHz 19 MHz MPC9315 19 MHz (Feedback) 33 MHz (Feedback) MPC9315 1:1 frequency configuration (feedback of QC1 = 33 MHz). FSELA = PSELA = H. All other control pins are left open. Frequency range 76 MHz QC0 QC1 FSELA FSELB FSELC PSELA MPC9315 QA0 QA1 Min Max MPC9315 4x, 2x, 1x frequency configuration (feedback of QC1 = 19 MHz). All control pins are left open. Frequency range Min Max Input 18.75 MHz 40 MHz Input 18.75 MHz 40 MHz QA outputs 37.50 MHz 80 MHz QA outputs 75.00 MHz 160 MHz QB outputs 37.50 MHz 80 MHz QB outputs 37.50 MHz 80 MHz QC outputs 18.75 MHz 40 MHz QC outputs 18.75 MHz 40 MHz TIMING SOLUTIONS 7 MOTOROLA MPC9315 Using the MPC9315 in zero–delay applications The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. In the following example calculation a I/O jitter confidence factor of 99.7% (± 3s) is assumed, resulting in a worst case timing uncertainty from input to any output of -300 ps to +300 ps relative to TCLK (VCC=3.3V and fVCO = 160 MHz): The external feedback option of the MPC9315 PLL allows for its use as a zero delay buffer. The PLL aligns the feedback clock output edge with the clock input reference edge and virtually eliminates the propagation delay through the device. The remaining insertion delay (skew error) of the MPC9315 in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset (SPO or t(∅)), I/O jitter (tJIT(∅), phase or long-term jitter), feedback path delay and the output-to-output skew (tSK(O) relative to the feedback output. The MPC9315 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs (TCLK or PCLK) of two or more MPC9315 are connected together, the maximum overall timing uncertainty from the common TCLK input to any output is: tSK(PP) = t( ∅) + tSK(O) + tPD, LINE(FB) + tJIT( ∅) CF This maximum timing uncertainty consists of 4 components: static phase offset, output skew, feedback board trace delay and I/O (phase) jitter: QFBDevice 1 tSK(PP) = [–300ps...300ps] + tPD, LINE(FB) tPD,LINE(FB) –t(∅) tJIT(∅) Any QDevice 1 +tSK(O) Figure 8. Max. I/O Jitter (RMS) versus frequency for VCC=2.5V +t(∅) QFBDevice2 Any QDevice 2 [–150ps...150ps] + [–150ps...150ps] + [(10ps @ –3)...(10ps @ 3)] + tPD, LINE(FB) Above equation uses the maximum I/O jitter number shown in the AC characteristic table for VCC=3.3V (10 ps RMS). I/O jitter is frequency dependant with a maximum at the lowest VCO frequency (160 MHz for the MPC9315). Applications using a higher VCO frequency exhibit less I/O jitter than the AC characteristic limit. The I/O jitter characteristics in Figure 8. and Figure 9. can be used to derive a smaller I/O jitter number at the specific VCO frequency, resulting in tighter timing limits in zero-delay mode and for part-to-part skew tSK(PP). Calculation of part-to-part skew TCLKCommon tSK(PP) = tJIT(∅) +tSK(O) Max. skew tSK(PP) Figure 7. MPC9315 max. device-to-device skew Due to the statistical nature of I/O jitter, a RMS value (1 s) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 8. Table 8: Confidence Facter CF CF Probability of clock edge within the distribution ± 1s 0.68268948 ± 2s 0.95449988 ± 3s 0.99730007 ± 4s 0.99993663 ± 5s 0.99999943 ± 6s 0.99999999 MOTOROLA Figure 9. Max. I/O Jitter (RMS) versus frequency for VCC=3.3V Power Supply Filtering The MPC9315 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Noise on the VCCA (PLL) power supply impacts the device characteristics, for instance I/O jitter. The MPC9315 provides separate power 8 TIMING SOLUTIONS MPC9315 drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20Ω the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Motorola application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50Ω resistance to VCC÷2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9315 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 11. “Single versus Dual Transmission Lines” illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9315 clock driver is effectively doubled due to its capability to drive multiple lines. supplies for the output buffers (VCC) and the phase-locked loop (VCCA) of the device.The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies, a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCCA pin for the MPC9315. Figure 10. illustrates a typical power supply filter scheme. The MPC9315 frequency and phase stability is most susceptible to noise with spectral content in the 100kHz to 20MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICCA current (the current sourced through the VCCA pin) is typically 3 mA (5 mA maximum), assuming that a minimum of 2.325V (VCC=3.3V or VCC=2.5V) must be maintained on the VCCA pin. The resistor RF shown in Figure 10. “VCCA Power Supply Filter” must have a resistance of 270 (VCC=3.3V) or 9-10 (VCC=2.5V) to meet the voltage drop criteria. W RF = 270Ω for VCC = 3.3V RF = 9–10Ω for VCC = 2.5V W CF = 1 µF for VCC = 3.3V CF = 22 µF for VCC = 2.5V RF MPC9315 OUTPUT BUFFER VCCA VCC CF 10 nF IN RS = 36Ω ZO = 50Ω OutA MPC9315 MPC9315 OUTPUT BUFFER VCC 33...100 nF IN RS = 36Ω ZO = 50Ω OutB0 14Ω RS = 36Ω Figure 10. VCCA Power Supply Filter ZO = 50Ω OutB1 The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 10. “VCCA Power Supply Filter”, the filter cut-off frequency is around 3-5 kHz and the noise attenuation at 100 kHz is better than 42 dB. As the noise frequency crosses the series resonant point of an individual capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9315 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Figure 11. Single versus Dual Transmission Lines The waveform plots in Figure 12. “Single versus Dual Line Termination Waveforms” show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9315 output buffer is more than sufficient to drive 50Ω transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9315. The output waveform in Figure 12. “Single versus Dual Line Termination Waveforms” shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36Ω series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS ( Z0 ÷ (RS+R0 +Z0)) Z0 = 50Ω || 50Ω RS = 36Ω || 36Ω R0 = 14Ω Driving Transmission Lines The MPC9315 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output TIMING SOLUTIONS 14Ω 9 MOTOROLA MPC9315 VL = 3.0 ( 25 ÷ (18+17+25) = 1.31V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns). Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 13. “Optimized Dual Line Termination” should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. 3.0 VOLTAGE (V) 2.5 OutA tD = 3.8956 OutB tD = 3.9386 MPC9315 OUTPUT BUFFER 2.0 In RS = 22Ω ZO = 50Ω RS = 22Ω ZO = 50Ω 14Ω 1.5 1.0 0.5 14Ω + 22Ω k 22Ω = 50Ω k 50Ω 25Ω = 25Ω 0 Figure 13. Optimized Dual Line Termination 2 4 6 8 TIME (nS) 10 12 14 Figure 12. Single versus Dual Waveforms MPC9315 DUT Pulse Generator Z = 50 ZO = 50Ω ZO = 50Ω W RT = 50Ω RT = 50Ω VTT VTT Figure 14. CLK0, CLK1 MPC9315 AC test reference MOTOROLA 10 TIMING SOLUTIONS MPC9315 VCC VCC 2 B CLK0, 1 GND VCC VCC 2 B FB0, 1 GND t(∅) Figure 15. Propagation delay (t(∅), SPO) test reference VCC VCC 2 VCC VCC 2 GND GND B B tP VCC VCC 2 B T0 GND DC = tP /T0 x 100% tSK(O) The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage The pin–to–pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device Figure 16. Output Duty Cycle (DC) TN TN+1 Figure 17. Output–to–output Skew tSK(O) TJIT(CC) = |TN –TN+1 | T0 The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs TJIT(PER) = |TN –1/f0 | The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles Figure 18. Cycle–to–cycle Jitter Figure 19. Period Jitter TCLK0, 1 FB0, 1 TJIT(∅) = |T0 –T1 mean| tF VCC=3.3V 2.4 VCC=2.5V 1.8V 0.55 0.6V tR The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles Figure 20. I/O Jitter TIMING SOLUTIONS Figure 21. Output Transition Time Test Reference 11 MOTOROLA MPC9315 OUTLINE DIMENSIONS A –T–, –U–, –Z– FA SUFFIX LQFP PACKAGE CASE 873A-02 ISSUE A 4X A1 32 0.20 (0.008) AB T–U Z 25 1 –U– –T– B V AE P B1 DETAIL Y 17 8 V1 AE DETAIL Y 9 4X –Z– 9 0.20 (0.008) AC T–U Z S1 S DETAIL AD G –AB– 0.10 (0.004) AC AC T–U Z –AC– BASE METAL ÉÉ ÉÉ ÉÉ ÉÉ F 8X M_ R J D SECTION AE–AE W K X DETAIL AD Q_ GAUGE PLANE H 0.250 (0.010) C E MOTOROLA M N 0.20 (0.008) SEATING PLANE 12 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE –AB– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED AT DATUM PLANE –AB–. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE –AC–. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE –AB–. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF TIMING SOLUTIONS MPC9315 NOTES TIMING SOLUTIONS 13 MOTOROLA MPC9315 NOTES MOTOROLA 14 TIMING SOLUTIONS MPC9315 NOTES TIMING SOLUTIONS 15 MOTOROLA MPC9315 Motorola reserves the right to make changes without further notice to any products herein. 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MOTOROLA and the logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. E Motorola, Inc. 2002. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1–303–675–2140 or 1–800–441–2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3–20–1, Minami–Azabu. Minato–ku, Tokyo 106–8573 Japan. 81–3–3440–3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852–26668334 Technical Information Center: 1–800–521–6274 HOME PAGE: http://www.motorola.com/semiconductors/ MOTOROLA ◊ 16 MPC9315/D TIMING SOLUTIONS