MCR8N Preferred Device Silicon Controlled Rectifiers Reverse Blocking Thyristors Designed primarily for half-wave ac control applications, such as motor controls, heating controls, and power supplies; or wherever half−wave, silicon gate−controlled devices are needed. http://onsemi.com Features • • • • • • • • SCRs 8 AMPERES RMS 600 thru 800 VOLTS Blocking Voltage of 600 thru 800 Volts On−State Current Rating of 8 Amperes RMS at 80°C High Surge Current Capability − 80 Amperes Rugged, Economical TO−220AB Package Glass Passivated Junctions for Reliability and Uniformity Minimum and Maximum Values of IGT, VGT and IH Specified for Ease of Design High Immunity to dv/dt − 100 V/msec Minimum at 125°C Pb−Free Packages are Available* G A K MARKING DIAGRAM MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Peak Repetitive Off−State Voltage (Note 1) (TJ = −40 to 125°C, Sine Wave, 50 to 60 Hz, Gate Open) MCR8M MCR8N VDRM, VRRM On-State RMS Current (180° Conduction Angles; TC = 80°C) IT(RMS) 8.0 ITSM 80 A I2t 26.5 A2sec PGM 5.0 W PG(AV) 0.5 W Forward Peak Gate Current (Pulse Width ≤ 1.0 ms, TC = 80°C) IGM 2.0 A Operating Junction Temperature Range TJ −40 to 125 °C Storage Temperature Range Tstg −40 to 150 °C Peak Non-Repetitive Surge Current (One Full Cycle, 60 Hz, TC = 125°C) Circuit Fusing Consideration (t = 8.33 ms) Forward Peak Gate Power (Pulse Width ≤ 1.0 ms, TC = 80°C) Forward Average Gate Power (t = 8.3 ms, TC = 80°C) Value Unit V AY WW MCR8NG AKA 600 800 1 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; positive gate voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the devices are exceeded. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2005 December, 2005 − Rev. 5 TO−220AB CASE 221A−09 STYLE 3 A 1 2 3 A Y WW G AKA = Assembly Location = Year = Work Week = Pb−Free Package = Diode Polarity PIN ASSIGNMENT 1 Cathode 2 Anode 3 Gate 4 Anode ORDERING INFORMATION Device Package Shipping MCR8N TO−220AB 50 Units / Rail MCR8NG TO−220AB (Pb−Free) 50 Units / Rail Preferred devices are recommended choices for future use and best overall value. Publication Order Number: MCR8/D MCR8N THERMAL CHARACTERISTICS Characteristic Thermal Resistance Junction−to−Case Junction−to−Ambient Maximum Lead Temperature for Soldering Purposes 1/8″ from Case for 10 Seconds Symbol Value Unit RqJC RqJA 2.2 62.5 °C/W TL 260 °C ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max − − − − 0.01 2.0 Unit OFF CHARACTERISTICS Peak Repetitive Forward or Reverse Blocking Current (VD = Rated VDRM and VRRM; Gate Open) TJ = 25°C TJ = 125°C IDRM, IRRM mA ON CHARACTERISTICS Peak Forward On−State Voltage (Note ) (ITM = 16 A) VTM − − 1.8 V Gate Trigger Current (Continuous dc) (VD = 12 V; RL = 100 W) IGT 2.0 7.0 15 mA Holding Current (VD = 12 V, Gate Open, Initiating Current = 200 mA) IH 4.0 17 30 mA Latch Current (VD = 12 V, IG = 15 mA) IL 6.0 20 40 mA VGT 0.5 0.65 1.0 V VGD 0.2 − − V Critical Rate of Rise of Off−State Voltage (VD = Rated VDRM, Exponential Waveform, Gate Open, TJ = 125°C) dv/dt 100 250 − V/ms Critical Rate of Rise of On−State Current IPK = 50 A, Pw = 40 msec, diG/dt = 1 A/msec, Igt = 50 mA di/dt − − 50 A/ms Gate Trigger Voltage (Continuous dc) (VD = 12 V; 100 W) TJ = 25°C Gate Non−Trigger Voltage (VD = 12 V; RL = 100 W) TJ = 125°C DYNAMIC CHARACTERISTICS 2. Indicates Pulse Test: Pulse Width v 2.0 ms, Duty Cycle v 2%. http://onsemi.com 2 MCR8N Voltage Current Characteristic of SCR + Current Anode + VTM Symbol Parameter VDRM Peak Repetitive Off State Forward Voltage IDRM Peak Forward Blocking Current VRRM Peak Repetitive Off State Reverse Voltage IRRM Peak Reverse Blocking Current VTM Peak On State Voltage IH Holding Current on state IH IRRM at VRRM + Voltage IDRM at VDRM Reverse Blocking Region (off state) Forward Blocking Region (off state) Reverse Avalanche Region P(AV), AVERAGE POWER DISSIPATION (WATTS) Anode − TC, CASE TEMPERATURE (° C) 125 120 115 110 105 dc 100 95 30° 60° 90° 180° 90 0 1 2 3 4 5 6 7 8 IT(RMS), RMS ON−STATE CURRENT (AMPS) 20 18 16 180° 90° 14 12 30° 10 8 6 4 2 0 0 1 2 3 4 5 7 6 8 IT(AV), AVERAGE ON−STATE CURRENT (AMPS) Figure 1. Typical RMS Current Derating Figure 2. On−State Power Dissipation 100 20 MAXIMUM @ TJ = 25°C GATE TRIGGER CURRENT (mA) IT, INSTANTANEOUS ON−STATE CURRENT (AMPS) dc 60° MAXIMUM @ TJ = 125°C 10 1 0.1 0.5 1.0 1.5 2.0 2.5 18 16 14 12 10 8 6 4 2 0 −40 −25 −10 3.0 5 20 35 50 65 80 95 110 125 VT, INSTANTANEOUS ON−STATE VOLTAGE (VOLTS) TJ, JUNCTION TEMPERATURE (°C) Figure 3. Typical On−State Characteristics Figure 4. Typical Gate Trigger Current versus Junction Temperature http://onsemi.com 3 VGT, GATE TRIGGER VOLTAGE (VOLTS) MCR8N 10 1 −40 −25 −10 5 20 35 50 65 80 95 110 125 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 −40 −25 −10 5 20 35 50 65 80 95 110 125 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 5. Typical Holding Current versus Junction Temperature Figure 6. Typical Gate Trigger Voltage versus Junction Temperature 100 IL, LATCHING CURRENT (mA) IH, HOLDING CURRENT (mA) 100 10 1 −40 −25 −10 5 20 35 50 65 80 95 110 125 TJ, JUNCTION TEMPERATURE (°C) Figure 7. Typical Latching Current versus Junction Temperature http://onsemi.com 4 MCR8N PACKAGE DIMENSIONS TO−220AB CASE 221A−09 ISSUE AA −T− B SEATING PLANE C F T S 4 DIM A B C D F G H J K L N Q R S T U V Z A Q 1 2 3 U H K Z L R V J NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. G D N INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.147 0.095 0.105 0.110 0.155 0.018 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 −−− −−− 0.080 STYLE 3: PIN 1. 2. 3. 4. MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 3.73 2.42 2.66 2.80 3.93 0.46 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 −−− −−− 2.04 CATHODE ANODE GATE ANODE ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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