Order this document by MC13760PP/D MC13760 Product Preview GSM/DCS/TDMA/AMPS Multi-Protocol Transceiver The MC13760 Multi–Protocol, Multi–Band Digital Transceiver IC combines, on a single Advanced BiCMOS chip, the major building blocks required for next generation multi–purpose, multi–band wireless products. The device includes the majority of the circuitry necessary for IF signal processing between the RF front end and the DSP and backend. The MC13760 contains two fractional–N synthesizers, a re–configurable zero IF receiver with programmable bandwidth, receive A/D conversion, multi–rate data interface to the baseband DSP, direct launch digital modulator, full transmit support circuits, and general purpose support circuits such as D/A and A/D converters, battery save and tri–state control switches. Intended for use in a combined GSM/TDMA/AMPS/iDEN portable wireless phone product in the 800/900/1800/1900 MHz bands. The MC13760 can be used over a wide range of RF and IF frequencies. The main PLL prescaler input is usable to over 2.0 GHz and the IF quadrature downconverter operates up to 400 MHz. The MC13760 has separate receive IF inputs and a common zero–IF IQ receiver for TDMA and for GSM accommodating the receiver architectural need to use different IF frequencies and filters without the need for additional switches. • Receiver Functions for all GSM/DCS/TDMA IS–136/AMPS Modes and Frequencies Including GPRS • Direct Interface to Motorola Baseband Processors, such as the DSP56690 through a Common Programming and Data Interface • Main Three Accumulator (24–Bit) Fractional–N Synthesizer • Resolution Capability of 6.0 Hz • Dual–Mode Charge Pump Output for TDMA TX VCO and all RX • Independent Charge Pump Output for the GSM/DCS TX VCO • GMSK Lookup ROM for Direct Transmission in GSM/DCS Mode • Digital 16–Bit Automatic Frequency Control • • • • • • • • • MULTI–PROTOCOL TRANSCEIVER SEMICONDUCTOR TECHNICAL DATA PLASTIC PACKAGE CASE 1285 (BGA–104) ORDERING INFORMATION Device Operating Temperature Range Package MC13760 TA = –40 to 85°C BGA–104 Secondary Three Accumulator (24–Bit) Fractional–N Synthesizer for use as an Accurate Frequency–Corrected Clock in GSM, or as an Additional Low Frequency LO Coarse Tuning of the VCO(s) via a 6–Bit D/A with Adapt Operates at 2.75 V Deep Sleep Mode with Current as low as 50 µA Versatile Frequency Generation including Linear and Constant Envelope Modulation Paths, Ramp and Power Level Control, Direct Gain Control of the RFPA in the TDMA Mode D/A Conversion of TDMA TXI and TXQ Reference Crystal Oscillator with a Buffered Output, Compensation/Fine Tuning via 9–Bit D/A Receiver Gain Adjustment and Bandwidth Down to 6.0 kHz Programmed over the SPI Bus A/D Conversion of RXI and RXQ to 8–Bit or 10–Bit Resolution Types of Applications • GSM/DCS/TDMA/AMPS Global Roaming Multiband Cellular Telephone • VHF/UHF 2–Way or Trunked Radio, iDEN, Tetra, or Satellite Communication Radios or Telephones • Hand–Held Wireless PDA’s • Wireless LAN’s, Industrial Devices, ISM Band Products • Any New Device Containing Some Combination of the Above Functions This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. MOTOROLA WIRELESS SEMICONDUCTOR SOLUTIONS – RF AND IF DEVICE DATA Motorola, Inc. 2000 Rev 0 1 MC13760 AGC Control RFA0 On Channel AGC Det. On Channel AGC Det. AGC Warp I PREINI PREINIB SPI Control DCOCL Step Alternator Control PRAVCC1 VACBYP VAC AGC AGCGND AGCVCC BBEGND BBEVCC DCLICIN DCLICP DMKGND DMKVCC DMKGNDDIG DMKVCCDIG Figure 1. MC13760 Detailed Block Diagram 1 Pole 2 Pole 2 Pole NVCC 2 Pole Step Atten NGND PRAGND QVCC AGC Amp PRAVCC2 Q PREINGB PREING 1 Pole 2 Pole 2 Pole QGND 2 Pole Step Atten PRAGNDDIG LOIN +2 Quadrature Generator DCLQCP DCOCL Tracking Loop & BB Filter BW Control DCLQCIN S/H Adapt Timing S/H Addressable Shift Register SPII REFVCC SPICLK TCAPP CEX Internal Reference & Bias 8 REFGND 24 Programmable Divider 6 16 LSB Look–Up ROM Accumulator #2 2 Reference Oscillator MNCPGND TBD Order Passive Filter MNCPGND MAINVCC MAINGND AOCDRIVE 2 PtC Sw. Cap Filter TXE/TXKEY RXFS/SFS TSLOTB TCLK Cont. Time Filter Cont. Time Filter 24 TCLKB Clock Gen. 200 kHz 1.0, 2.4 or 2.6 MHz CLKGENIN OUTI OUTIB 8 6 Recombination Logic Accumulator #2 OUTQ OUTQB PtB +7/ +14/ +21/ +28 MUX From PtD 8X6 3 Bit 6 Bit 6 Bit Cosine D/A 6 Reg 6 Lookup 3 Counter 8 Bit 8 Bit Reg 8 Counter 8 8 5 Bit 5 Reg Programmable Divider Accumulator #3 3 Control Logic 8 400 KHz Reference Phase Detector/ +N Charge Pump 13.0 – 16.8 MHz or 26.0 – 33.6 MHz 2 +1/+2/ +3/+4 16 From PtD TEST1 PLLCP CLKOUT PLLEMIT PLLBASE Tark Circuit VBLIN 8 Bit D/A ASW VCNTO Mixer & Preamp Current 22 49 Test Multiplex (2 Outputs) PLLCPVCC REFPLLGND CLKSEL REFPLLVCC OSCENB DETSW SATDET Output Enable D or A IREF 5 From PtB TXKEYOUT SEGND SEBYP SFOUT SFVCC +1/ +2/ +3/ +4 3 MUX 6 5 SPICLK CEX From PtA SPI REG PtD MUX From PtA From TXE/ PtC TXKEY DMCS SPII Super Filter 2 Sw. Cap Filter RSTB TSLOT +65/ +84/ +130/ +168 +1/ +2 PtA CLKGENIN 5 Bit D/A TXCLK/SCK RXCLK Clock Generation & Control Logic Accumulator #1 +10/ +26 Wideb and Charge Pump 8 Bit D/A STD 62 62 IF Control Channel AFC 62 Addressable Shift Register CPGT 8 Bit D/A B16 D Q dk 4 Dual Mode Charge Pump 8 Bit D/A Addressable Shift Register ADAPT +13/ +17/ +26/ +34 26 MHz CPGITR Transmit Data Register RXACQ SPII SPICLK CEX LONCGND XTALEMIT SRD 4 SPI 9 Bit Control D/A Phase Detector Startup XTALBASE 26 MHz 4.333 MHz GPO3 OSCGND Receive Data Register 13.0 or 16.8 MHz IREF LONCVCC OSCVCC B6 2 Comb Filter GPO2 Third Order Passive Filter Accumulator #3 Comb Filter TX DATA Buffer Start DO Clk GPO1 XTALWARP SPI 6 Bit Control D/A SERIALGND 32 Recombination Logic TM VCOCT1 Adapt 10 Bit, or 8 Bit Cyclic A/D 3:1 Input Mux 24 AFC_SEL 24 Bit Adder 26 MHz VCOCT2 AGCI Battery Save Fine Channel Accumulator #1 PRSCIN DIG_AFC Enable TESTD CREF Battery Save TEST2 TCAPM SERIALVCC S/H Loop Filter MOTOROLA WIRELESS SEMICONDUCTOR SOLUTIONS – RF AND IF DEVICE DATA ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ MC13760 Table 1. BGA Contact Identification BALL # BALL NAME DESCRIPTION SIGNAL TYPE A1 PRAGNDDIG Ground for the preamp substrate. Ground A2 PRAGND Ground for the preamp. Ground A3 PREINGB GSM IF preamp input. RF Input A4 PREINIB TDMA IF preamp input. RF Input A5 BBFGND Ground for the baseband filters. Ground A6 DCLQCP DC Offset Correction Loop (input) capacitor – Q channel Analog Input A7 CREF Bypass capacitor for the bandgap regulator. Analog A8 OUTQ TDMA Q channel analog transmit data. Analog Output A9 OUTIB TDMA I channel analog transmit data. Analog Output A10 TSLOTB TDMA low level transmit slot. Analog Output A11 TSLOT TDMA low level transmit slot. Analog Output B1 RFA0 RF attenuator 0 control line. (This line is a driver for an external RF attenuator.) Digital Output B2 DMXGND Ground for the mixer. Ground B3 PREING GSM IF preamp input. RF Input B4 PREINI TDMA IF preamp input. RF Input B5 PRAVCC2 Supply for the preamp output stage. Supply 2.775 V B6 DCLICP DC Offset Correction Loop (input) capacitor – I channel Analog Input B7 GPO3/test_so2 SPI port expansion 3. Or scan data output for MODROM module. Digital Output B8 TCAPP Differential reference capacitor. Analog B9 REFGND Ground for the internal reference. Ground B10 REFVCC Supply for the internal reference. Supply 2.775 V B11 TCLK TDMA low level transmit clock. Analog Output C1 DMXVCC Supply for the mixer. Supply 2.775 V C2 DMXGNDDIG Ground for the mixer substrate and quadrature generator. Ground C3 PRAVCC1 Supply for the preamp. Supply 2.775 V C4 BBFVCC Supply for the baseband filters. Supply 2.775 V C5 DCLICIN DC Offset Correction Loop (output) capacitor – TDMA – I channel Analog Output C6 DCLQCIN DC Offset Correction Loop (output) capacitor – TDMA – Q channel Analog Output C7 TCAPM Differential reference capacitor. Analog C8 OUTQB TDMA Q channel analog transmit data. Analog Output C9 CLKSEL Selects the source for the clock output to the digital circuitry of the radio as either the crystal reference/divided crystal reference or the Step Up PLL/divided Step Up PLL. A low on this pin selects the crystal reference/divided crystal reference. A high on this pin selects the Step Up PLL/divided Step Up PLL. Integrated weak pulldown. Digital Input C10 TCLKB TDMA low level transmit clock. Analog Output C11 QGND Quiet analog ground for the PA D/A and the data processing circuits. Ground D1 LOIN Input port for the second LO VCO signal. RF Input D2 DMXVCCDIG Supply for the quadrature generator. Supply 2.775 V D3 TEST2/EERQ Test input/MUX 2 output. (Various signals are buffered and MUX’d to this pin. Output signal is determined by programming of test bits.) Or with EER active, TDMA Q channel transmit data. Analog Test Point D4 TEST1/EERI Test input/MUX 1 output. (Various signals are buffered and MUX’d to this pin. Output signal is determined by programming of test bits.) Or with EER active, TDMA I channel transmit data. Analog Test Point D6 PKGGND1 Ground for the package flag (no direct connection to die). Pkg Ground D8 OUTI TDMA I channel analog transmit data. Analog Output D9 TESTD/GPO4 Digital test point. (Various digital signals are MUX’d to this pin. Output is determined by programming of test bits.) Or SPI port expansion 4. Digital Test Point Digital Output MOTOROLA WIRELESS SEMICONDUCTOR SOLUTIONS – RF AND IF DEVICE DATA 3 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ MC13760 Table 1. BGA Contact Identification (continued) BALL # BALL NAME DESCRIPTION SIGNAL TYPE D10 QVCC Quiet analog supply for the PA D/A and the data processing circuits. Supply 2.775 V D11 NGND Noisy analog ground for the VCO D/A, AOC D/A and the data processing circuits. Ground E1 VAG Analog ground. Analog E2 AGCGND Ground for the AGC. Ground E3 VAGBYP Bypass capacitor for the analog ground voltage. Analog E9 NVCC Noisy analog supply for the VCO D/A, AOC D/A and the data processing circuits. Supply 2.775 V E10 RSTB Reset. Low true input. Integrated weak pullup. Digital Input E11 TM Enable for the internal scan test. Digital Input F1 AGCVCC Supply for the AGC. Supply 2.775 V F2 TXKEYOUT/test_so4 Conditioned TXKEY out. Or scan data output for reference clock module. Digital Output F3 AGC Capacitor for the TDMA AGC. Analog F4 PKGGND2 Ground for the package flag (no direct connection to die). Pkg Ground F8 PKGGND3 Ground for the package flag (no direct connection to die). Pkg Ground F9 PLLCPVCC Supply for the Step Up PLL phase detector and charge pump. Supply 5.0 V F10 CLKOUT Clock output to the digital circuitry of the radio. Ranges are 13.0 to 16.8 MHz, or 26.0 to 33.6 MHz. The actual frequency provided will depend upon the configuration of the Step Up PLL and the SPI selected configuration of the MC13760. Analog Output F11 PLLCP Charge pump output for the Step Up PLL. Analog Output G1 PRSCIN Main LO prescaler input. RF Input G2 MAINGND Ground for the main prescaler and divider. Ground G3 AOCDRIVE Output to the PA bias circuitry drive input. (Output drive impedance is 620 Ohms.) Analog Output G9 PLLEMIT Emitter of the oscillator transistor for the Step Up PLL. RF Output G10 REFPLLVCC Supply for the Step Up PLL VCO and dividers. Supply 2.775 V G11 PLLBASE/vco_clk Base of the oscillator transistor for the Step Up PLL. Or scan clock input for VCO clock zone. RF Input H1 SATDET/test_si4 Input indicating saturation. Or scan data input for reference clock module. Digital Input H2 GPO2/test_so8 SPI port expansion 2. Or Main PLL Adapt Timer output. Or scan data output for SSI module. Digital Output H3 MAINVCC Supply for the main prescaler and divider. Supply 2.775 V H4 MNCPVCC Supply for the main phase detector and charge pump. Supply 5.0 V H6 PKGGND4 Ground for the package flag (no direct connection to die). Pkg Ground H8 TXE/TXKEY/test_si8 Transmit slot enable in TDMA mode; digital input to start/stop the PA Control sequence in GSM mode. Or scan data input for SSI module. Digital Input H9 RXACQ/test_si7 Serial bus enable. Or scan data input for 5 bit and 8 bit xtal clock dividers. Digital Input H10 REFPLLGND Ground for the Step Up PLL. Ground H11 4 SERIALVCC Supply for the SSI and SPI serial communication ports. Supply 1.8 — 2.775V J1 GPO1/test_so1 SPI port expansion 1. Or Coarse Tune Adapt Timer output. Or scan data output for main Frac–N. Digital Output J2 VCOCT2 High current (ADAPT) output of the 6 bit main RX VCO Coarse Tune D/A. Analog Output J3 DETSW/test_si1 Output to the PA control circuitry power range input (open drain). Or scan data input for main Frac–N. Analog Output J4 SFVCC Supply for the super filter. Supply 2.775 V J5 ASW/sc_inp1 TDMA antenna switch control input. Or scan data input for reference clock Frac–N accumulator module. Digital Input MOTOROLA WIRELESS SEMICONDUCTOR SOLUTIONS – RF AND IF DEVICE DATA ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ MC13760 Table 1. BGA Contact Identification (continued) BALL # BALL NAME DESCRIPTION SIGNAL TYPE J6 VCNTO TDMA RFPA gain control voltage output. Analog Output J7 OSCVCC Supply for the crystal oscillator. Supply 2.775 V J8 XTALWARP Output of the 9 bit WARP D/A to be used for compensation/correction of the reference crystal frequency. Analog Output J9 OSCENB Digital input used to control the crystal oscillator circuit. A logic low selects the internal oscillator. Integrated weak pulldown. Digital Input J10 RXCLK/test_so3 SSI RX clock in GSM mode; not used in TDMA mode. Or scan data output for transmit power amp control module. Digital Output J11 SRD/test_so6 SSI receive data. Or scan data output for Adapt Generator module. Digital Output K1 VCOCT1 Low current output of the 6 bit main RX VCO Coarse Tune D/A. Analog Output K2 MNCPGND Ground for the main phase detector and charge pump. Ground K3 SFGND Ground for the super filter. Ground K4 SFBYP Bypass capacitor for the super filter. (1.0 µf) Analog K5 OSCGND Ground for the crystal oscillator. Ground K6 XTALBASE/sc_clk26 Crystal oscillator base. Or scan clock input for xtal clock zone. RF Input K7 LOGICVCC Supply for the main synthesizer logic, adapt control and test MUXs. Supply 2.775 V K8 CEX Digital input that latches in the SPI data. (Low Active) Digital Input K9 SPICLK SPI clock input. Digital Input K10 STD/test_si3 SSI transmit data. Or scan data input for transmit. Digital Input K11 TXCLK/SCK/test_so5 Bit clock for TX data transfer in GSM mode. Bit clock for RX and TX data transfer in TDMA mode. Or scan data output for reference clock Frac–N accumulator module. Digital Output L1 ADAPT Synthesizer output to adapt the loop filter for the main PLL. Analog Output L2 CPGT Charge pump output for the main TX LO (GSM). Analog Output L3 CPGITR Charge pump output for the main RX LO (GSM, TDMA TX and RX). Analog Output L4 SFOUT Super filter output. (45 mA max) (bypass with 0.01 µf) Analog Output L5 VBLIN TDMA RFPA bias control voltage output. Analog Output L6 XTALEMIT Crystal oscillator emitter. RF Output L7 LOGICGND Ground for the main synthesizer logic, adapt control and test MUXs. Ground L8 SERIALGND Ground for the SSI and SPI serial communication ports. Ground L9 SPII SPI data input. Digital Input L10 DMCS/test_si2 Digital input that starts the GSM TX modulation. Or scan data input for MODROM module. Digital Input L11 RXFS/SFS/test_so7 RX SSI frame sync in GSM mode; SSI frame sync in TDMA mode. Or scan data output for 5 bit and 8 bit xtal clock dividers. Digital Output MOTOROLA WIRELESS SEMICONDUCTOR SOLUTIONS – RF AND IF DEVICE DATA 5 MC13760 OUTLINE DIMENSIONS PLASTIC PACKAGE CASE 1224B–01 (BGA–104) ISSUE B D X LASER MARK FOR PIN 1 IDENTIFICATION IN THIS AREA Y NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO DATUM PLANE Z. 4. DATUM Z (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. M K E DIM A A1 A2 b D E e M 0.20 e 8X 9 8 7 4 3 2 MILLIMETERS MIN MAX 0.95 1.30 0.20 0.34 0.94 REF 0.30 0.50 8.00 BSC 8.00 BSC 0.80 BSC METALIZED MARK FOR PIN A1 IDENTIFICATION IN THIS AREA 1 5 A B 8X C e A 0.30 Z A2 D E F G H J 3 81X A1 81X Z 4 0.15 Z DETAIL K ROTATED 90 _ CLOCKWISE b 0.25 M Z X Y 0.10 M Z VIEW M–M Motorola reserves the right to make changes without further notice to any products herein. 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