LPC47M182 Advanced I/O Controller with Motherboard GLUE Logic Data Brief Product Features 3.3V Operation (5V tolerant) LPC Interface − Multiplexed Command, Address and Data Bus − Serial IRQ Interface Compatible with Serialized IRQ Support for PCI Systems 5V Reference Generation 5V Standby Reference Generation IDE Reset/Buffered PCI Reset Outputs Power OK Signal Generation Power Sequencing Power Supply Turn On Circuitry Resume Reset Signal Generation Hard Drive Front Panel LED Voltage Translation for DDC to VGA Monitor SMBus Isolation Circuitry CNR Dynamic Down Control − − − − − Serial Ports Infrared Port − − − − − − Multiprotocol Infrared Interface 32-Byte Data FIFO IrDA 1.0 Compliant SHARP ASK IR HP-SIR 480 Address, Up to 15 IRQ and Three DMA Options Multi-Mode Parallel Port with ChiProtect − Standard Mode IBM PC/XT PC/AT, and PS/2 Compatible Bi-directional Parallel Port − Enhanced Parallel Port (EPP) Compatible - EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant) − IEEE 1284 Compliant Enhanced Capabilities Port (ECP) − ChiProtect Circuitry for Protection − 960 Address, Up to 15 IRQ and Three DMA Options 16-Byte Data FIFO , Sophisticated Power Control Circuitry (PCC) Including Multiple Powerdown Modes for Reduced Power Consumption − DMA Enable Logic − Data Rate and Drive Control Registers 8042 Software Compatible 8 Bit Microcomputer 2k Bytes of Program ROM 256 Bytes of Data RAM Four Open Drain Outputs Dedicated for Keyboard/Mouse Interface Asynchronous Access to Two Data Registers and One Status Register Supports Interrupt and Polling Access 8 Bit Counter Timer Port 92 Support Fast Gate A20 and KRESET Outputs − Two Full Function Serial Ports − High Speed 16C550A Compatible UART with Send/Receive 16-Byte FIFOs − Supports 230k and 460k Baud − Programmable Baud Rate Generator − Modem Control Circuitry − 480 Address and 15 IRQ Options − 100% IBM Compatibility − Detects All Overrun and Underrun Conditions Keyboard Controller − − − − − 2.88MB Super I/O Floppy Disk Controller − Licensed CMOS 765B Floppy Disk Controller − Software and Register Compatible with SMSC's Proprietary 82077AA Compatible Core − Supports One Floppy Drive − Configurable Open Drain/Push-Pull Output Drivers − Supports Vertical Recording Format ACPI 1.0b/2.0 Compliant Programmable Wake-up Event Interface PC99a/PC2001 Compliant General Purpose Input/Output Pins (13) Fan Tachometer Inputs (2) Green and Yellow Power LEDs ISA Plug-and-Play Compatible Register Set Motherboard GLUE Logic − − − − − − − − − − − Enhanced Digital Data Separator − 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data Rates − Programmable Precompensation Modes 480 Address, Up to Eight IRQ and Three DMA Options Interrupt Generating Registers − Registers Generate IRQ1 – IRQ15 on Serial IRQ Interface. XOR-Chain Board Test 128 Pin QFP Lead-free RoHS Compliant Package, 3.2 mm Footprint SMSC LPC47M182 SMSC/Non-SMSC Register Sets (03-23-07) PRODUCT PREVIEW ORDERING INFORMATION Order Number: LPC47M182-NW 128 Pin, QFP Lead-free RoHS Compliant Package 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2007 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. SMSC/Non-SMSC Register Sets (03-23-07) 2 PRODUCT PREVIEW SMSC LPC47M182 General Description The LPC47M182* is a 3.3V (5V tolerant) PC99a/PC2001 compliant Advanced I/O controller for Desktop PCs. The device, which implements the Low Pin Count (LPC) interface, includes I/O functionality as well as Motherboard GLUE logic into a 128-pin package. This is space saving solution on the motherboard resulting in lower cost. The LPC47M182 also provides 13 general purpose pins, which offer flexibility to the system designer, and two Fan Tachometer Inputs. The LPC47M182’s LPC interface supports LPC I/O and DMA cycles. The LPC47M182 includes complete legacy I/O: a keyboard interface; SMSC's true CMOS 765B floppy disk controller with advanced digital data separator; two 16C550A compatible UARTs; one Multi-Mode parallel port including ChiProtect circuitry plus EPP and ECP. The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures, in addition, it provides data overflow and underflow protection. The SMSC’s patented advanced digital data separator allows for ease of testing and use. The parallel port is compatible with IBM PC/AT architecture, as well as IEEE 1284 EPP and ECP. The LPC47M182 incorporates sophisticated power control circuitry (PCC) which includes support for keyboard and mouse wake up events as well as PME support. The PCC supports multiple low power-down modes. The LPC47M182 is ACPI 1.0b/2.0 compatible. The Motherboard GLUE logic includes various power management logic; including generation of nRSMRST, Power OK signal generation, 5V main and standby reference generation. There are also three LEDs to indicate power status and hard drive activity. The translation circuit converts 3.3V signals to 5V signals. Also included is SMBus main power well to resume power well isolation circuitry. The LPC47M182 supports the ISA Plug-and-Play Standard register set (Version 1.0a). The I/O Address, DMA Channel and hardware IRQ of each logical device in the LPC47M182 may be reprogrammed through the internal configuration registers. There are up to 480 (960 for Parallel Port) I/O address location options, a Serialized IRQ interface, and three DMA channels. On chip, Interrupt Generating Registers enable external software to generate IRQ1 through IRQ15 on the Serial IRQ Interface. The LPC47M182’s Enhanced Digital Data Separator does not require any external filter components and is therefore easy to use and offers lower system costs and reduced board area. The LPC47M182 is register compatible with SMSC’s proprietary 82077AA core. *The “2” at the end of the part number is a designator for particular BIOS used inside the specific chip. SMSC LPC47M182 Page 3 PRODUCT PREVIEW SMSC/Non-SMSC Register Sets (03-23-07) SER_IRQ SERIAL IRQ / Interrupt Generating Registers LAD[3:0] LPC Bus Interface nLDRQ PME / Power Control nIO_PME (GP20-GP23)* GP24* GPIOs VCC (3.3V) F_CAP Resume Reset Generation REF5V Multi-Mode Parallel Port with ChiProtectTM High-Speed 16550A UART PORT VTR (3.3V) V_5P0_STBY High-Speed 16550A UART PORT 2 W/ Infrared 5V Reference Generation REF5V_STBY nAUD_LINK_RST nCDC_DWN_ENAB* XOR* TEST_EN FAN_TACH2* FAN_TACH1* PD[7:0] LPC47M182 (128 QFP) GP10-GP15, GP16*, GP17* nRSMRST XOR-Chain Internal Bus (Data, Address, and Control lines) nLPCPD V_5P0_STBY FAN Monitoring Power LED nLFRAME nPCI_RESET YLW_LED GRN_LED CLOCK GEN nSLP_S5 PCI_CLK CLOCKI CLOCKI32 Block Diagram CNR Logic Configuration Registers nCDC_DWN_RST nPCI_RST_OUT BUSY, SLCT, PE, nERROR, nACK nSTROBE, nINITP, nSLCTIN, nALF RXD TXD nCTS nRTS nDSR nDTR* nDCD nRI RXD2 TXD2 nCTS2 nRTS2 nDSR2 nDTR2 nDCD2 nRI2 IRRX2 IRTX2 KDAT, MDAT nPCI_RST_OUT2 nIDE_RSTDRV Buffered PCI Reset nPCI_RESET Keyboard/Mouse 8042 Controller nPRIMARY_HD nKBDRST Hard Drive Front Panel LED nSECONDARY_HD nSCSI nHD_LED nFPRST nBACKFEED_CUT LATCHED_BF_CUT SCK_BJT_GATE nPS_ON KCLK, MCLK GA20M WDATA WCLOCK Power Sequencing SMBus Isolation SMSC PROPRIETARY 82077 COMPATIBLE VERTICAL FLOPPYDISK CONTROLLER CORE VGA Voltage Translation RCLOCK RDATA DIGITAL DATA SEPARATOR WITH WRITE PRECOMPENSATION nRDATA nWDATA nWGATE, nHDSEL nTRK0, nDSKCHG, nINDEX, nWRTPRT DRVDEN0, DRVDEN1 nDIR, nSTEP, nDS0, nMTR0 DDCSDA_3V* DDCSCL_3V* DDCSCL_5V* DDCSDA_5V* SMB_CLK_R SMB_DAT_R SMB_DAT_M SMB_CLK_M nSLP_S3 nSLP_S5 nCPU_PRESENT PWRGD_PLATFORM PWRGD_PS Note 1: This diagram shows the various functions available on the chip (not pin layout). The block diagram should not be used for pin count. Note 2: Functions with asterisks (*) are located on multifunctional pins. Figure 1 - LPC47M182 Block Diagram SMSC/Non-SMSC Register Sets (03-23-07) 4 PRODUCT PREVIEW SMSC LPC47M182 Package Outline Figure 2 - 128 Pin QFP Package Outline, 14x20x2.7 Body, 3.2MM Footprint A A1 A2 D D1 E E1 H L L1 e θ W R1 R2 ccc MIN ~ 0.05 2.55 23.00 19.90 17.00 13.90 0.09 0.73 ~ 0o 0.10 0.08 0.08 ~ Table 1 - 128 Pin QFP Package Parameters NOMINAL MAX REMARKS ~ 3.4 Overall Package Height ~ 0.5 Standoff ~ 3.05 Body Thickness 23.20 23.40 X Span 20.00 20.10 X body Size 17.20 17.40 Y Span 14.00 14.10 Y body Size ~ 0.20 Lead Frame Thickness 0.88 1.03 Lead Foot Length 1.60 ~ Lead Length 0.50 Basic Lead Pitch ~ 7o Lead Foot Angle ~ 0.30 Lead Width ~ ~ Lead Shoulder Radius ~ 0.30 Lead Foot Radius ~ 0.08 Coplanarity Notes: 1 Controlling Unit: millimeter. 2 Tolerance on the position of the leads is ± 0.04 mm maximum. 3 Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm. 4 Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane. 5 Details of pin 1 identifier are optional but must be located within the zone indicated. SMSC LPC47M182 Page 5 PRODUCT PREVIEW SMSC/Non-SMSC Register Sets (03-23-07)