STK15C88 32Kx8 PowerStore nvSRAM FEATURES DESCRIPTION • 25, 45 ns Read Access & R/W Cycle Time The Simtek STK15C88 is a 256Kb fast static RAM with a non-volatile Quantum Trap storage element included with each memory cell. • Unlimited Read/Write Endurance • Pin compatible with industry standard SRAMs • Automatic Non-volatile STORE on Power Loss • Automatic RECALL to SRAM on Power Up • Non-Volatile STORE or RECALL under Software Control The SRAM provides the fast access & cycle times, ease of use and unlimited read & write endurance of a normal SRAM. Data transfers automatically to the non-volatile storage cells when power loss is detected (the STORE operation). On power up, data is automatically restored to the SRAM (the RECALL operation). Both STORE and RECALL operations are also available under software control. • Unlimited RECALL Cycles • 1 Million Store Cycles • 100-Year Non-volatile Data Retention • Single 5V ± 10% Power Supply PowerStore nvSRAM products depend on the intrinsic system capacitance to maintain system power long enough for an automatic store on power loss. If the power ramp from 5 volts to 3.6 volts is faster than 10 ms, consider our 14C88 or 16C88 for more reliable operation. • Commercial and Industrial Temperatures • 28-pin 300-mil and 330 mil SOIC Packages (RoHS-Compliant) The Simtek nvSRAM is the first monolithic non-volatile memory to offer unlimited writes and reads. It is the highest performance, most reliable non-volatile memory available. BLOCK DIAGRAM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 STORE STATIC RAM ARRAY 512 X 512 STORE/ RECALL CONTROL RECALL SOFTWARE DETECT INPUT BUFFERS A5 A6 A7 A8 A9 A11 A12 A13 A14 ROW DECODER QUANTUM TRAP 512 x 512 A13 – A0 COLUMN I/O COLUMN DEC A 0 A 1 A 2 A 3 A 4 A10 G E W This product conforms to specifications per the terms of Simtek standard warranty. The product has completed Simtek internal qualification testing and has reached production status. 1 Document Control #ML0016 Rev 0.3 February, 2007 STK15C88 PIN CONFIGURATIONS A14 28 VCC A12 A7 1 2 3 27 26 A6 4 25 W A13 A8 A5 24 A4 5 6 A3 7 22 A2 A1 8 21 20 A0 DQ0 10 DQ1 12 DQ2 13 14 VSS 23 9 19 18 11 17 16 15 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 28 Pin 300 mil SOIC 28 Pin 330 mil SOIC PIN NAMES Pin Name I/O Description A14-A0 Input Address: The 15 address inputs select one of 32,768 bytes in the nvSRAM array DQ7-DQ0 I/O Data: Bi-directional 8-bit data bus for accessing the nvSRAM E Input Chip Enable: The active low E input selects the device W Input Write Enable: The active low W enables data on the DQ pins to be written to the address location latched by the falling edge of E G Input Output Enable: The active low G input enables the data output buffers during read cycles. De-asserting G high caused the DQ pins to tri-state. VCC Power Supply Power: 5.0V, ±10% VSS Power Supply Ground Document Control #ML0016 Rev 0.3 February, 2007 2 STK15C88 ABSOLUTE MAXIMUM RATINGSa Voltage on Input Relative to Ground . . . . . . . . . . . . . –0.5V to 7.0V Voltage on Input Relative to VSS . . . . . . . . . . –0.6V to (VCC + 0.5V) Voltage on DQ0-7 . . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V) Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W DC Output Current (1 output at a time, 1s duration) . . . . . . . .15mA Note a: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. (VCC = 5.0V ± 10%) DC CHARACTERISTICS COMMERCIAL SYMBOL INDUSTRIAL PARAMETER UNITS MIN MAX MIN NOTES MAX ICC1b Average VCC Current 97 70 100 70 mA mA tAVAV = 25ns tAVAV = 45ns ICC2c Average VCC Current during STORE 3 3 mA All Inputs Don’t Care, VCC = max Average VCC Current at tAVAV = 200ns 5V, 25°C, Typical 10 10 mA W ≥ (V CC – 0.2V) All Others Cycling, CMOS Levels ICC4c Average VCAP Current during AutoStore Cycle 2 2 mA ISB1d Average VCC Current (Standby, Cycling TTL Input Levels) 30 22 31 23 mA mA tAVAV = 25ns, E ≥ VIH tAVAV = 45ns, E ≥ VIH ISB2d VCC Standby Current (Standby, Stable CMOS Input Levels) 1.5 1.5 mA E ≥ (V CC – 0.2V) All Others VIN ≤ 0.2V or ≥ (VCC – 0.2V) IILK Input Leakage Current ±1 ±1 μA VCC = max VIN = VSS to VCC IOLK Off-State Output Leakage Current ±5 ±5 μA VCC = max VIN = VSS to VCC, E or G ≥ VIH VIH Input Logic “1” Voltage 2.2 VCC + .5 2.2 VCC + .5 V All Inputs VIL Input Logic “0” Voltage VSS – .5 0.8 VSS – .5 0.8 V All Inputs VOH Output Logic “1” Voltage V IOUT = – 4mA VOL Output Logic “0” Voltage 0.4 V IOUT = 8mA TA Operating Temperature 85 °C ICC3 b 2.4 2.4 0.4 0 70 –40 All Inputs Don’t Care Note b: ICC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. Note c: ICC2 and ICC4 are the average currents required for the duration of the respective STORE cycles (tSTORE ) . Note d: E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. AC TEST CONDITIONS Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1 CAPACITANCEe SYMBOL 5.0V (TA = 25°C, f = 1.0MHz) PARAMETER MAX UNITS CIN Input Capacitance 5 pF ΔV = 0 to 3V COUT Output Capacitance 7 pF ΔV = 0 to 3V 480 Ohms CONDITIONS OUTPUT 255 Ohms Note e: These parameters are guaranteed but not tested. 30 pF INCLUDING SCOPE AND FIXTURE Figure 1: AC Output Loading Document Control #ML0016 Rev 0.3 February, 2007 3 STK15C88 SRAM READ CYCLES #1 & #2 (VCC = 5.0V ± 10%) SYMBOLS NO. STK15C88-25 STK15C88-45 PARAMETER #1, #2 1 tELQV 2 f tAVAV g 3 tAVQV 4 tGLQV 5 tAXQX 6 tELQX UNITS Alt. g h MIN 25 tRC Read Cycle Time tAA Address Access Time 25 45 ns tOE Output Enable to Data Valid 10 20 ns tOH Output Hold after Address Change 5 5 ns tLZ Chip Enable to Output Active 5 5 ns Chip Disable to Output Inactive 8 tGLQX tOLZ Output Enable to Output Active 9 tGHQZh tOHZ Output Disable to Output Inactive tPA Chip Enable to Power Active tPS Chip Disable to Power Standby tELICCH tEHICCLd, e 45 25 tHZ 11 45 10 0 0 10 0 25 2 tAVAV ADDRESS 3 tAVQV 5 tAXQX DATA VALID DQ (DATA OUT) SRAM READ CYCLE #2: E Controlledf 2 tAVAV ADDRESS 1 tELQV 6 11 tEHICCL tELQX E 7 tEHQZ G 8 tGLQX 9 tGHQZ 4 tGLQV DQ (DATA OUT) DATA VALID 10 tELICCH ACTIVE STANDBY Document Control #ML0016 Rev 0.3 February, 2007 4 ns ns 45 SRAM READ CYCLE #1: Address Controlledf, g ns ns 15 0 ns ns 15 Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles. Note g: I/O state assumes E, G < VIL and W > VIH; device is continuously selected. Note h: Measured + 200mV from steady state output voltage. ICC MAX Chip Enable Access Time tEHQZ 10 MIN tACS 7 e MAX ns STK15C88 (VCC = 5.0V ± 10%) SRAM WRITE CYCLES #1 & #2 SYMBOLS STK15C88-25 NO. STK15C88-45 PARAMETER UNITS #1 #2 Alt. 12 tAVAV tAVAV tWC Write Cycle Time 25 45 ns 13 tWLWH tWLEH tWP Write Pulse Width 20 30 ns 14 tELWH tELEH tCW Chip Enable to End of Write 20 30 ns 15 tDVWH tDVEH tDW Data Set-up to End of Write 10 15 ns 16 tWHDX tEHDX tDH Data Hold after End of Write 0 0 ns 17 tAVWH tAVEH tAW Address Set-up to End of Write 20 30 ns 18 tAVWL tAVEL tAS Address Set-up to Start of Write 0 0 ns 19 tWHAX tEHAX tWR Address Hold after End of Write 0 0 ns 20 tWLQZh, i tWZ Write Enable to Output Disable 21 tWHQX tOW Output Active after End of Write Note i: Note j: MIN MAX 10 5 SRAM WRITE CYCLE #1: W Controlledj 12 tAVAV ADDRESS 19 tWHAX 14 tELWH E 17 tAVWH tAVWL 13 tWLWH W 15 tDVWH DATA IN DATA OUT 16 tWHDX DATA VALID 20 tWLQZ 21 tWHQX HIGH IMPEDANCE PREVIOUS DATA SRAM WRITE CYCLE #2: E Controlledj 12 tAVAV ADDRESS 14 tELEH 18 tAVEL 19 tEHAX E 17 tAVEH 13 tWLEH W 15 tDVEH DATA IN DATA OUT Document Control #ML0016 Rev 0.3 February, 2007 16 tEHDX DATA VALID HIGH IMPEDANCE 5 MAX 15 5 If W is low when E goes low, the outputs remain in the high-impedance state. E or W must be ≥ VIH during address transitions. 18 MIN ns ns STK15C88 (VCC = 5.0V ± 10%) AutoStore/POWER-UP RECALL SYMBOLS STK15C88 NO. PARAMETER Standard UNITS NOTES MIN 22 tRESTORE Power-up RECALL Duration 23 tSTORE STORE Cycle Duration 24 VSWITCH Low Voltage Trigger Level 25 VRESET Low Voltage Reset Level MAX 550 4.0 10 ms 4.5 V 3.6 V Note k: tRESTORE starts from the time VCC rises above VSWITCH. AutoStore/POWER-UP RECALL VCC 5V 24 VSWITCH 25 VRESET AutoStore™ 23 tSTORE POWER-UP RECALL 22 tRESTORE W DQ (DATA OUT) POWER-UP RECALL BROWN OUT NO STORE DUE TO NO SRAM WRITES BROWN OUT AutoStore BROWN OUT AutoStore NO RECALL (VCC DID NOT GO BELOW VRESET) NO RECALL (VCC DID NOT GO BELOW VRESET) RECALL WHEN VCC RETURNS ABOVE VSWITCH Document Control #ML0016 Rev 0.3 February, 2007 6 μs k g STK15C88 SOFTWARE STORE/RECALL MODE SELECTION E W A13 - A0 (hex) MODE I/O NOTES H 0E38 31C7 03E0 3C1F 303F 0FC0 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Output Data Output Data Output Data Output Data Output Data Output High Z l, m H 0E38 31C7 03E0 3C1F 303F 0C63 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL Output Data Output Data Output Data Output Data Output Data Output High Z l, m L L Note l: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle. Note m: While there are 15 addresses on the STK15C88, only the lower 14 are used to control software modes. (VCC = 5.0V ± 10%) SOFTWARE STORE/RECALL CYCLEn, o NO. 26 27 28 SYMBOLS tAVAV tAVEL STK15C88-25 STK15C88-45 MIN MIN PARAMETER UNITS MAX MAX STORE/RECALL Initiation Cycle Time 25 45 ns n Address Set-up Time 0 0 ns n Clock Pulse Width 20 30 ns g, n Address Hold Time 20 20 ns tELEH 29 tELAX 30 tRECALL RECALL Duration 20 20 μs Note n: The software sequence is clocked with E controlled reads. Note o: The six consecutive addresses must be in the order listed in the Software STORE/RECALL Mode Selection Table: (0E38, 31C7, 03E0, 3C1F, 303F, 0FC0) for a STORE cycle or (0E38, 31C7, 03E0, 3C1F, 303F, 0C63) for a RECALL cycle. W must be high during all six consecutive cycles. SOFTWARE STORE/RECALL CYCLE: E Controlledo 26 26 tAVAV ADDRESS tAVAV ADDRESS #1 27 tAVEL ADDRESS #6 28 tELEH E 29 tELAX 23 tSTORE DQ (DATA DATA VALID DATA VALID Document Control #ML0016 Rev 0.3 February, 2007 7 30 / tRECALL HIGH IMPEDANCE STK15C88 nvSRAM OPERATION The STK15C88 is a versatile memory chip that provides several modes of operation. The STK15C88 can operate as a standard 32K x 8 SRAM. It has a 32K x 8 nonvolatile element shadow to which the SRAM information can be copied, or from which the SRAM can be updated in nonvolatile mode. NOISE CONSIDERATIONS Note that the STK15C88 is a high-speed memory and so must have a high-frequency bypass capacitor of approximately 0.1μF connected between VCC and VSS, using leads and traces that are as short as possible. As with all high-speed CMOS ICs, normal careful routing of power, ground and signals will help prevent noise problems. SRAM READ The STK15C88 performs a READ cycle whenever E and G are low and W is high. The address specified on pins A0-14 determines which of the 32,768 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAVQV (READ cycle #1). If the READ is initiated by E or G, the outputs will be valid at tELQV or at tGLQV, whichever is later (READ cycle #2). The data outputs will repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins, and will remain valid until another address change or until E or G is brought high. SRAM WRITE A WRITE cycle is performed whenever E and W are low. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle. The data on the common I/O pins DQ0-7 will be written into the memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on the common I/O lines. If G is left low, internal circuitry will turn off the output buffers tWLQZ after W goes low. Document Control #ML0016 Rev 0.3 February, 2007 8 SOFTWARE NONVOLATILE STORE The STK15C88 software STORE cycle is initiated by executing sequential READ cycles from six specific address locations. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. The program operation copies the SRAM data into nonvolatile memory. Once a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence or the sequence will be aborted and no STORE or RECALL will take place. To initiate the software STORE cycle, the following READ sequence must be performed: 1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 0E38 (hex) 31C7 (hex) 03E0 (hex) 3C1F (hex) 303F (hex) 0FC0 (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate STORE cycle The software sequence must be clocked with E controlled READs. Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence, although it is not necessary that G be low for the sequence to be valid. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation. SOFTWARE NONVOLATILE RECALL A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of READ operations must be performed: 1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 0E38 (hex) 31C7 (hex) 03E0 (hex) 3C1F (hex) 303F (hex) 0C63 (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate RECALL cycle STK15C88 Internally, RECALL is a two-step procedure. First, the SRAM data is cleared, and second, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time the SRAM will once again be ready for READ and WRITE operations. The RECALL operation in no way alters the data in the nonvolatile elements. The nonvolatile data can be recalled an unlimited number of times. AutoStoreTM OPERATION The STK15C88 uses the intrinsic system capacitance to perform an automatic STORE on power down. As long as the system power supply takes at least tSTORE to decay from VSWITCH down to 3.6V, the STK15C88 will safely and automatically store the SRAM data in nonvolatile elements on power down. In order to prevent unneeded STORE operations, automatic STOREs will be ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Softwareinitiated STORE cycles are performed regardless of whether a WRITE operation has taken place. Additional information may be found in applications note “Applying the STK11C88, STK15C88 and STK16C88 32K nvSRAM.” POWER-UP RECALL To help avoid this situation, a 10K Ohm resistor should be connected either between W and system VCC or between E and system VCC. HARDWARE PROTECT The STK15C88 offers hardware protection against inadvertent STORE operation and SRAM WRITEs during low-voltage conditions. When VCC < VSWITCH, all software STORE operations and SRAM WRITEs are inhibited. LOW AVERAGE ACTIVE POWER The STK15C88 draws significantly less current when it is cycled at times longer than 50ns. Figure 2 shows the relationship between ICC and READ cycle time. Worst-case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 5.5V, 100% duty cycle on chip enable). Figure 3 shows the same relationship for WRITE cycles. If the chip enable duty cycle is less than 100%, only standby current is drawn when the chip is disabled. The overall average current drawn by the STK15C88 depends on the following items: 1) CMOS vs. TTL input levels; 2) the duty cycle of chip enable; 3) the overall cycle rate for accesses; 4) the ratio of READs to WRITEs; 5) the operating temperature; 6) the VCC level; and 7) I/O loading. During power up, or after any low-power condition (VCC < VRESET), an internal RECALL request will be latched. When VCC once again exceeds the sense voltage of VSWITCH, a RECALL cycle will automatically be initiated and will take tRESTORE to complete. If the STK15C88 is in a WRITE state at the end of power-up RECALL, the SRAM data will be corrupted. 100 Average Active Current (mA) Average Active Current (mA) 100 80 60 40 TTL 20 CMOS 100 150 Cycle Time (ns) TTL 40 CMOS 20 50 200 Figure 2: ICC (max) Reads Document Control #ML0016 Rev 0.3 February, 2007 60 0 0 50 80 100 150 Cycle Time (ns) Figure 3: ICC (max) Writes 9 200 STK15C88 ORDERING INFORMATION STK15C88 - N F 45 I TR Packaging Options Blank = Tube TR = Tape and Reel Temperature Range Blank = Commercial (0 to 70°C) I = Industrial (–40 to 85°C) Access Time 25 = 25ns 45 = 45ns Lead Finish F = 100% Sn (Matte Tin) Package S = Plastic 28-pin 330 mil SOIC N = Plastic 28-pin 300 mil SOIC Document Control #ML0016 Rev 0.3 February, 2007 10 STK15C88 ORDERING CODES STK15C88-SF25 5V 32Kx8 PowerStore nvSRAM SOP28-330 STK15C88-SF45 5V 32Kx8 PowerStore nvSRAM SOP28-330 Commercial STK15C88-NF25 5V 32Kx8 PowerStore nvSRAM SOP28-300 Commercial STK15C88-NF45 5V 32Kx8 PowerStore nvSRAM SOP28-300 Commercial STK15C88-SF25TR 5V 32Kx8 PowerStore nvSRAM SOP28-330 Commercial STK15C88-SF45TR 5V 32Kx8 PowerStore nvSRAM SOP28-330 Commercial STK15C88-NF25TR 5V 32Kx8 PowerStore nvSRAM SOP28-300 Commercial STK15C88-NF45TR 5V 32Kx8 PowerStore nvSRAM SOP28-300 Commercial STK15C88-SF25I 5V 32Kx8 PowerStore nvSRAM SOP28-330 Industrial STK15C88-SF45I 5V 32Kx8 PowerStore nvSRAM SOP28-330 Industrial STK15C88-NF25I 5V 32Kx8 PowerStore nvSRAM SOP28-300 Industrial STK15C88-NF45I 5V 32Kx8 PowerStore nvSRAM SOP28-300 Industrial STK15C88-SF25ITR 5V 32Kx8 PowerStore nvSRAM SOP28-330 Industrial STK15C88-SF45ITR 5V 32Kx8 PowerStore nvSRAM SOP28-330 Industrial STK15C88-NF25ITR 5V 32Kx8 PowerStore nvSRAM SOP28-300 Industrial STK15C88-NF45ITR 5V 32Kx8 PowerStore nvSRAM SOP28-300 Industrial Document Control #ML0016 Rev 0.3 February, 2007 11 Commercial STK15C88 PACKAGE DRAWINGS 28 Pin 300 mil SOIC ( 0.292 7.42 0.300 7.59 ) 0.400 10.16 0.410 10.41 ( ) Pin 1 Index .050 (1.27) BSC ( 0.701 17.81 0.711 18.06 ) 0.097 2.46 0.104 2.64 ( ) ( 0.090 2.29 0.094 2.39 ( 0.014 0.35 0.019 0.48 0.009 0.23 0.013 0.32 ( ) ( 0.005 0.12 0.012 0.29 ) 0° 8° ) ( 0.024 0.61 Document Control #ML0016 Rev 0.3 February, 2007 12 ) ) DIM = INCHES DIM = mm MIN MAX MIN ) ( MAX STK15C88 28 Pin 330 mil SOIC 0.713 0.733 ( 18.11 ) 18.62 0.112 (2.845) 0.020 0.014 ( 0.508 ) 0.356 0.050 (1.270) 0.103 0.093 0.336 0.326 0.004 (0.102) ( 2.616 ) 2.362 ( 8.534 ) 8.280 0.477 0.453 ( 12.116 ) 11.506 Pin 1 0.014 0.008 10° 0° ( 0.356 ) 0.203 0.044 0.028 MIN MAX DIM = INCHES DIM = mm Document Control #ML0016 Rev 0.3 February, 2007 MIN ) ( MAX 13 ( 1.117 ) 0.711 STK15C88 Document Revision History Revision Date Summary 0.0 December 2002 0.1 September 2003 Added lead-free lead finish 0.2 March 2006 Removed DIP packages, Removed 35ns Speed Grade, Remove leaded lead finish 0.3 February 2007 Add fast power-down slew rate information Add Tape Reel Ordering Options Add Product Ordering Code Listing Add Package Drawings Reformat Entire Document SIMTEK STK15C88 Datasheet, February 2007 Copyright 2007, Simtek Corporation. All rights reserved. This datasheet may only be printed for the expressed use of Simtek Customers. No part of the datasheet may be reproduced in any other form or means without the express written permission from Simtek Corporation. The information contained in this publication is believed to be accurate, but changes may be made without notice. Simtek does not assume responsibility for, or grant or imply any warranty, including MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE regarding this information, the product or its use. Nothing herein constitutes a license, grant or transfer of any rights to any Simtek patent, copyright, trademark, or other proprietary right. Document Control #ML0016 Rev 0.3 February, 2007 14