INTERSIL ISL21007BFB812Z

ISL21007
®
Data Sheet
April 12, 2007
Precision, Low Noise FGA™ Voltage
References
FN6326.1
Features
• Reference Output Voltage . . . . . . . . . . . . . . .1.25V, 2.50V
The ISL21007 FGA™ voltage references are extremely low
power, high precision, and low noise voltage references
fabricated on Intersil’s proprietary Floating Gate Analog
technology. The ISL21007 features very low noise (4µVP-P
for 0.1Hz to 10Hz) and very low operating current (150µA,
Max). In addition, the ISL21007 family features guaranteed
initial accuracy as low as ±0.5mV.
• Initial Accuracy . . . . . . . . . . . . . . . . . . . . ±0.5mV (B grade)
• Input Voltage Range: . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
• Low Output Voltage Noise . . . . . . 4µVP-P (0.1Hz to 10Hz)
• Supply Current . . . . . . . . . . . . . . . . . . . . . . . .150µA (Max)
• Temperature Coefficient . . . . . . . . . . . . 3ppm/°C (B grade)
This combination of high initial accuracy, low drift, and low
output noise performance of the ISL21007 enables versatile
high performance control and data acquisition applications
with low power consumption.
• Operating Temperature Range. . . . . . . . . -40°C to +125°C
Available Options
Applications
• Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ld SOIC
• Pb-Free Plus Anneal Available (RoHS Compliant)
• High Resolution A/Ds and D/As
VOUT
OPTION
(V)
INITIAL
ACCURACY
(mV)
TEMPCO.
(ppm/°C)
ISL21007BFB812Z
1.250
±0.5
3
ISL21007CFB812Z
1.250
±1.0
5
ISL21007DFB812Z
1.250
±2.0
10
ISL21007BFB825Z
2.500
±0.5
3
ISL21007CFB825Z
2.500
±1.0
5
ISL21007DFB825Z
2.500
±2.0
10
PART NUMBER
• Digital Meters
• Bar Code Scanners
• Basestations
• Battery Management/Monitoring
• Industrial/Instrumentation Equipment
Pinout
ISL21007
(8 LD SOIC)
TOP VIEW
GND or NC 1
8 DNC
VIN 2
7 DNC
DNC 3
6 VOUT
GND 4
5 TRIM
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL21007
Ordering Information
PART NUMBER
(Note)
PART MARKING
VOUT OPTION
(V)
GRADE
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG. DWG. #
ISL21007BFB812Z
21007BF Z12
1.250
±0.5mV, 3ppm/°C
-40 to +125
8 Ld SOIC
M8.15
ISL21007CFB812Z
21007CF Z12
1.250
±1.0mV, 5ppm/°C
-40 to +125
8 Ld SOIC
M8.15
ISL21007DFB812Z
21007DF Z12
1.250
±2.0mV, 10ppm/°C
-40 to +125
8 Ld SOIC
M8.15
ISL21007BFB825Z
21007BF Z25
2.500
±0.5mV, 3ppm/°C
-40 to +125
8 Ld SOIC
M8.15
ISL21007CFB825Z
21007CF Z25
2.500
±1.0mV, 5ppm/°C
-40 to +125
8 Ld SOIC
M8.15
ISL21007DFB825Z
21007DF Z25
2.500
±2.0mV, 10ppm/°C
-40 to +125
8 Ld SOIC
M8.15
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
*Add “-TK” suffix for tape and reel
2
FN6326.1
April 12, 2007
ISL21007
Pin Descriptions
PIN NUMBER
PIN NAME
DESCRIPTION
1
GND or NC
2
VIN
Power Supply Input Connection
4
GND
Voltage Reference Output Connection
5
TRIM
Allows user trim ±2.5%
6
VOUT
Do Not Connect; Internal Connection – Must Be Left Floating
3, 7, 8
DNC
Do Not Connect; Internal Connection - Must Be Left Floating
Ground Connection
Typical Application Circuit
1
+3V
2
C1
10µF
3
4
GND
NC
VIN
NC
NC
VOUT
GND
NC
8
7
6
5
ISL21007-12, 25
SPI BUS
X79000
1
SCK
2
3
4
5
6
A0
CLR
A1
VCC
A2
VH
SI
VL
SO
7
/RDY
8
9
10
/CS
VREF
VSS
UP
VOUT
DOWN
VBUF
OE
VFB
20
19
18
17
16
C1
0.001µF
15
14
13
12
LOW NOISE DAC OUTPUT
11
FIGURE 1. TYPICAL APPLICATION PRECISION 12-BIT SUBRANGING DAC
3
FN6326.1
April 12, 2007
ISL21007
Absolute Voltage Ratings
Thermal Information
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Max Voltage VIN to Gnd . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +6.5V
Max Voltage VOUT to Gnd (10s). . . . . . . . . . . . . . . -0.5V to VOUT + 1
Voltage on “DNC” pins . . . . No connections permitted to these pins.
Lead Temperature, soldering (10s) . . . . . . . . . . . . . . . . . . . . +260°C
ESD Rating
Human Body Model (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . .6kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .600V
Charged Device Model (CDM) . . . . . . . . . . . . . . . . . . . . . . . . .2kV
Continuous Power Dissipation (TA = +70°C) (Note 1)
8 Lead SOIC derate 5.88mW/°C above +70°C . . . . . .
471mW
Pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature Range (Industrial) . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at
the specified temperature and are pulsed tests, therefore: TJ = TC = TA
NOTE:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Common Electrical Specifications (ISL21007-12, -25)TA = -40°C to +125°C, unless otherwise specified.
PARAMETER
DESCRIPTION
VIN
Input Voltage Range
VOA
VOUT Accuracy @ TA = +25°C
TC VOUT
Output Voltage Temperature
Coefficient (Note 2)
IIN
Supply Current
ΔVOUT/Δt
Long Term Stability (Note 4)
CONDITIONS
MIN
TYP
MAX
UNIT
2.7
5.5
V
ISL21007B
-0.5
+0.5
mV
ISL21007C
-1.0
+1.0
mV
ISL21007D
-2.0
+2.0
mV
ISL21007B
3
ppm/°C
ISL21007C
5
ppm/°C
ISL21007D
10
ppm/°C
150
µA
75
TA = +25°C
Trim Range
±2.0
TBD
ppm/√1kHrs
±2.5
%
Turn on Settling Time
VOUT = ±0.1%
120
µs
Ripple Rejection
f = 10kHz
60
dB
eN
Output Voltage Noise
0.1Hz ≤ f ≤ 10Hz
4
µVP-P
VN
Broadband Voltage Noise
10Hz ≤ f ≤ 1kHz
2.2
µVRMS
Noise Density
f = 1kHz
60
nV/√Hz
tR
Electrical Specifications (ISL21007-12, VOUT = 1.250V) VIN = 3.0V, TA = -40°C to +125°C, unless otherwise specified.
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
VOUT
Output Voltage
ΔVOUT /ΔVIN
Line Regulation
2.7V < VIN < 5.5V
100
700
µV/V
ΔVOUT/ΔIOUT
Load Regulation
Sourcing: 0mA ≤ IOUT ≤ 7mA
10
100
µV/mA
Sinking: -7mA ≤ IOUT ≤ 0mA
20
150
µV/mA
1.250
V
ISC
Short Circuit Current
TA = +25°C, VOUT tied to GND
40
mA
ΔVOUT/ΔTA
Thermal Hysteresis (Note 3)
ΔTA = +165°C
50
ppm
4
FN6326.1
April 12, 2007
ISL21007
Electrical Specifications (ISL21007-25, VOUT = 2.50V) VIN = 3.0V, TA = -40°C to +125°C, unless otherwise specified
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
200
µV/V
VOUT
Output Voltage
ΔVOUT /ΔVIN
Line Regulation
2.7V < VIN < 5.5V
2.500
V
ΔVOUT/ΔIOUT
Load Regulation
Sourcing: 0mA ≤ IOUT ≤ 5mA
10
100
µV/mA
Sinking: -5mA ≤ IOUT ≤ 0mA
20
150
µV/mA
50
ISC
Short Circuit Current
TA = +25°C, VOUT tied to GND
50
mA
ΔVOUT/ΔTA
Thermal Hysteresis (Note 3)
ΔTA = +165°C
50
ppm
NOTES:
2. Over the specified temperature range. Temperature coefficient is measured by the box method whereby the change in VOUT is divided by the
temperature range; in this case, -40°C to +125°C = +165°C.
3. Thermal Hysteresis is the change of VOUT measured @ TA = +25°C after temperature cycling over a specified range, ΔTA. VOUT is read initially
at TA = +25°C for the device under test. The device is temperature cycled and a second VOUT measurement is taken at +25°C. The difference
between the initial VOUT reading and the second VOUT reading is then expressed in ppm. For Δ TA = +165°C, the device under test is cycled
from +25°C to +125°C to -40°C to +25°C.
4. FGA voltage reference long term drift is a logarithmic characteristic. Changes that occur after the first few hundred hours of operation are
significantly smaller with time, asymptotically approaching zero beyond 1,000 hours. Because of this decreasing characteristics, long term drift
is specified in ppm/√1kHrs.
Typical Performance Curves (ISL21007-12) (REXT = 100kΩ)
95
120
UNIT 3
90
100
UNIT 2
60
IIN (µA)
IIN (µA)
+125°C
85
80
UNIT 1
40
80
+25°C
75
70
20
-40°C
65
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
60
2.5
3.0
3.5
4.5
5.0
5.5
FIGURE 3. IIN vs VIN OVER TEMPERATURE
1.25015
150
ΔVO (µV)
(NORMALIZED TO VIN = 3.0V)
VOUT (V)
(NORMALIZED TO 1.25V AT VIN = 3.0V)
FIGURE 2. IIN vs VIN (3 UNITS)
1.25010
UNIT 3
1.25005
1.25000
UNIT 2
1.24995
1.24990
UNIT 1
1.24985
1.24980
2.5
4.0
VIN (V)
VIN (V)
3.0
3.5
4.0
VIN (V)
4.5
FIGURE 4. LINE REGULATION (3 UNITS)
5
5.0
5.5
100
50
+125°C
0
+25°C
-50
-40°C
-100
-150
-200
-250
-300
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VIN (V)
FIGURE 5. LINE REGULATION OVER TEMPERATURE
FN6326.1
April 12, 2007
ISL21007
Typical Performance Curves (ISL21007-12) (REXT = 100kΩ)
0.15
1.25010
+125°C
+25°C
1.25005
0.10
VOUT (V)
ΔVOUT (mV)
-40°C
-0.05
1.24995
UNIT 2
1.24990
UNIT 3
1.24985
-0.10
-0.15
-7
UNIT 1
1.25000
0.05
0.00
(Continued)
1.24980
-6 -5 -4
SINKING
-3 -2 -1 0 1 2 3
OUTPUT CURRENT (mA)
4 5 6 7
SOURCING
1.24975
-40
FIGURE 6. LOAD REGULATION OVER TEMPERATURE
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
140
FIGURE 7. VOUT vs TEMPERATURE (3 UNITS)
X: 5µs/DIV
Y: 500mV/DIV
X: 5µs/DIV
Y: 500mV/DIV
FIGURE 8. LINE TRANSIENT RESPONSE, NO CAPACITIVE
LOAD
FIGURE 9. LINE TRANSIENT RESPONSE, 0.001µF LOAD
CAPACITANCE
X: 20µs/DIV
Y: 1V/DIV
120
1nF LOAD
NO LOAD
100
10nF LOAD
VIN
ZOUT (Ω)
80
60
40
VOUT = 1.25V (FOR TYP IIN)
20
0
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 10. TURN ON TIME
6
FIGURE 11. ZOUT vs FREQUENCY
FN6326.1
April 12, 2007
ISL21007
Typical Performance Curves (ISL21007-12) (REXT = 100kΩ)
GAIN IS x1000,
NOISE IS 4µVp-p
(Continued)
+7mA
2mV/DIV
NO OUTPUT CAPACITANCE
X: 50µs/DIV
Y: 1V/DIV
-7mA
FIGURE 13. LOAD TRANSIENT RESPONSE
FIGURE 12. VOUT NOISE, 0.1Hz to 10Hz
0
VIN (DC) = 3V
VIN (AC) = 50mVP-P
-10
PSRR (dB)
-20
NO LOAD
-30
-40
1nF LOAD
-50
-60
-70
10nF LOAD
-80
-90
-100
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 14. PSRR vs CAPACITIVE LOADS
7
FN6326.1
April 12, 2007
ISL21007
Typical Performance Curves (ISL21007-25) (REXT = 100kΩ)
100
120
UNIT 3
95
100
+125°C
90
UNIT 2
85
UNIT 1
60
IIN (µA)
IIN (µA)
80
40
80
+25°C
-40°C
75
70
20
65
60
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
2.5
3.0
3.5
4.5
5.0
5.5
FIGURE 16. IIN vs VIN OVER TEMPERATURE
2.50020
100
ΔVO (µV)
(NORMALIZED TO VIN = 3.0V)
VOUT (V)
(NORMALIZED TO 2.5V AT VIN = 3V)
FIGURE 15. IIN vs VIN (3 UNITS)
UNIT 1
2.50010
2.50000
UNIT 2
2.49990
UNIT 3
2.49980
2.49970
2.49960
2.5
3.0
3.5
4.0
4.5
5.0
50
0
-50
-100
-150
+125°C
-200
-250
-300
-40°C
-350
-400
2.5
5.5
+25°C
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VIN (V)
VIN (V)
FIGURE 18. LINE REGULATION OVER TEMPERATURE
FIGURE 17. LINE REGULATION (3 UNITS)
2.5003
0.60
+125°C
0.40
UNIT 2
2.5002
NORMALIZED TO +25°C
2.5001
0.20
2.5000
-0.20
VOUT (V)
0.00
ΔVOUT (mV)
4.0
VIN (V)
VIN (V)
+25°C
-40°C
-0.40
UNIT 1
2.4999
2.4998
2.4997
2.4996
-0.60
2.4995
-0.80
2.4994
-1.00
2.4993
-40
-7
-6
-5
SINKING
-4
-3
-2
-1
0
1
2
OUTPUT CURRENT (mA)
3
4
5
6
SOURCING
FIGURE 19. LOAD REGULATION OVER TEMPERATURE
8
7
UNIT 3
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
140
FIGURE 20. VOUT vs TEMPERATURE (3 UNITS)
FN6326.1
April 12, 2007
ISL21007
Typical Performance Curves (ISL21007-25) (REXT = 100kΩ)
(Continued)
X: 5µs/DIV
Y: 500mV/DIV
X: 5µs/DIV
Y: 500mV/DIV
FIGURE 21. LINE TRANSIENT RESPONSE, NO CAPACITIVE
LOAD
FIGURE 22. LINE TRANSIENT RESPONSE, 0.001µF LOAD
CAPACITANCE
X: 20µs/DIV
Y: 1V/DIV
160
1nF LOAD
140
VIN
VOUT = 2.5V (FOR TYP IIN)
ZOUT (Ω)
120
NO LOAD
10nF LOAD
100
80
60
40
20
0
1
FIGURE 23. TURN ON TIME
GAIN IS x1000,
NOISE IS 4µVP-P
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
FIGURE 24. ZOUT vs FREQUENCY
+5mA
2mV/DIV
NO OUTPUT CAPACITANCE
X: 50µs/DIV
Y: 500mV/DIV
-5mA
FIGURE 25. VOUT NOISE, 0.1Hz to 10Hz
9
FIGURE 26. LOAD TRANSIENT RESPONSE
FN6326.1
April 12, 2007
ISL21007
Typical Performance Curves (ISL21007-25) (REXT = 100kΩ)
(Continued)
0
-20
PSRR (dB)
NO LOAD
VIN (DC) = 3V
VIN (AC) = 50mVP-P
-10
-30
-40
1nF LOAD
-50
-60
-70
10nF LOAD
-80
-90
-100
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 27. PSRR vs CAPACITIVE LOADS
Applications Information
FGA Technology
The ISL21007 voltage reference uses floating gate
technology to create references with very low drift and
supply current. Essentially the charge stored on a floating
gate cell is set precisely in manufacturing. The reference
voltage output itself is a buffered version of the floating gate
voltage. The resulting reference device has excellent
characteristics which are unique in the industry: very low
temperature drift, high initial accuracy, and almost zero
supply current. Also, the reference voltage itself is not limited
by voltage bandgaps or zener settings, so a wide range of
reference voltages can be programmed (standard voltage
settings are provided, but customer-specific voltages are
available).
The process used for these reference devices is a floating
gate CMOS process, and the amplifier circuitry uses CMOS
transistors for amplifier and output transistor circuitry. While
providing excellent accuracy, there are limitations in output
noise level and load regulation due to the MOS device
characteristics. These limitations are addressed with circuit
techniques discussed in other sections.
Micropower Operation
The ISL21007 consumes extremely low supply current due
to the proprietary FGA technology. Low noise performance is
achieved using optimized biasing techniques. Supply current
is typically 75µA and noise is 4µVP-P benefitting precision,
low noise portable applications such as handheld meters
and instruments.
Data Converters in particular can utilized the ISL21007 as an
external voltage reference. Low power DAC and ADC
circuits will realize maximum resolution with lowest noise.
10
Board Mounting Considerations
For applications requiring the highest accuracy, board
mounting location should be reviewed. The device uses a
plastic SOIC package which will subject the die to mild
stresses when the PC board is heated and cooled and
slightly changes shape. Placing the device in areas subject
to slight twisting can cause degradation of the accuracy of
the reference voltage due to these die stresses. It is normally
best to place the device near the edge of a board, or the
shortest side, as the axis of bending is most limited at that
location. Mounting the device in a cutout also minimizes flex.
Obviously mounting the device on flexprint or extremely thin
PC material will likewise cause loss of reference accuracy.
Noise Performance and Reduction
The output noise voltage in a 0.1Hz to 10Hz bandwidth is
typically 4µVP-P. The noise measurement is made with a
bandpass filter made of a 1 pole high-pass filter with a corner
frequency at 0.1Hz and a 2-pole low-pass filter with a corner
frequency at 12.6Hz to create a filter with a 9.9Hz bandwidth.
Noise in the 10kHz to 1MHz bandwidth is approximately
40µVP-P with no capacitance on the output. This noise
measurement is made with a 2 decade bandpass filter made
of a 1 pole high-pass filter with a corner frequency at 1/10 of
the center frequency and 1-pole low-pass filter with a corner
frequency at 10 times the center frequency. Load capacitance
up to 1000pF can be added but will result in only marginal
improvements in output noise and transient response. The
output stage of the ISL21007 is not designed to drive heavily
capactive loads, so for load capacitances above 0.001µF the
noise reduction network shown in Figure 28 is recommended.
This network reduces noise significantly over the full
bandwidth. Noise is reduced to less than 20µVP-P from 1Hz to
1MHz using this network with a 0.01µF capacitor and a 2kΩ
resistor in series with a 10µF capacitor. Also, transient
response is improved with higher value output capacitor. The
FN6326.1
April 12, 2007
ISL21007
0.01µF value can be increased for better load transient
response with little sacrifice in output stability.
VIN = 3.0V
10µF
0.1µF
VIN
VO
ISL21007
GND
2kΩ
0.01µF
10µF
FIGURE 28. HANDLING HIGH LOAD CAPACITANCE
Turn-On Time
The ISL21007 devices have low supply current and thus the
time to bias up internal circuitry to final values will be longer
than with higher power references. Normal turn-on time is
typically 120µs. This is shown in Figure 10. Circuit design
must take this into account when looking at power up delays
or sequencing.
Temperature Coefficient
The limits stated for temperature coefficient (tempco) are
governed by the method of measurement. The overwhelming
standard for specifying the temperature drift of a reference is to
measure the reference voltage at two temperatures, take the
total variation, (VHIGH – VLOW), and divide by the temperature
extremes of measurement (THIGH – TLOW). The result is
divided by the nominal reference voltage (at T = +25°C) and
multiplied by 106 to yield ppm/°C. This is the “Box” method for
specifying temperature coefficient.
Output Voltage Adjustment
The output voltage can be adjusted up or down by 2.5% by
placing a potentiometer from Vout to ground, and connecting
the wiper to the TRIM pin. The TRIM input is high impedance,
so no series resistance is needed. The resistor in the
potentiometer should be a low tempco (<50ppm/°C) and the
resulting voltage divider should have very low tempco
<5ppm/°C. A digital potentiometer such as the ISL95810
provides a low tempco resistance and excellent resistor and
tempco matching for trim applications.
11
FN6326.1
April 12, 2007
ISL21007
Typical Application Circuits
VIN = +5.0V
R = 200Ω
2N2905
VIN
ISL21007 VOUT
VOUT = 2.50V
2.5V/50mA
0.001µF
GND
FIGURE 29. PRECISION 2.5V 50mA REFERENCE
+2.7 to 5.5V
10µF
0.1µF
VIN
VOUT
ISL21007-25
VOUT = 2.50V
GND
0.001µF
VCC
RH
VOUT
X9119
(UNBUFFERED)
+
SDA
2-WIRE BUS
EL8178
SCL
VSS
–
VOUT
(BUFFERED)
RL
FIGURE 30. 2.5V FULL SCALE LOW-DRIFT, LOW NOISE, 10-BIT ADJUSTABLE VOLTAGE SOURCE
12
FN6326.1
April 12, 2007
ISL21007
Typical Application Circuits
10µF
+2.7 to 5.5V
0.1µF
VIN
2.5V ±2.5%
VOUT
ISL21007-12
TRIM
GND
VCC
RH
SDA
I2C BUS
SCL
ISL95810
VSS
RL
FIGURE 31. OUTPUT ADJUSTMENT USING THE TRIM PIN
+2.7 to 5.5V
0.1µF
10µF
VIN
EL8178
VOUT
ISL21007-12
+
VOUT SENSE
–
LOAD
GND
FIGURE 32. KELVIN SENSED LOAD
13
FN6326.1
April 12, 2007
ISL21007
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
H
0.25(0.010) M
B M
INCHES
E
SYMBOL
-B-
1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
MIN
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
e
α
B S
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
N
α
NOTES:
MILLIMETERS
8
0°
8
8°
0°
7
8°
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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14
FN6326.1
April 12, 2007