WM8746 w 24-bit, 192kHz 6-Channel DAC with Volume Control DESCRIPTION FEATURES WM8746 is a high performance 6-channel DAC designed for audio applications such as DVD, home theatre systems, and digital TV. The WM8746 supports data input word lengths from 16 to 32-bits and sampling rates up to 192kHz. The WM8746 can convert up to 6 channels at sample rates from 8 to 192kHz. Additionally WM8746 supports 2 channels at 192kHz and 4 channels at 96kHz simultaneously. The WM8746 consists of a serial interface port, digital interpolation filters, multi-bit sigma delta modulators and 6 DACs in a small 28-pin SSOP package. The WM8746 also includes a digitally controllable mute and attenuator function on each channel. The WM8746 supports a variety of connection schemes for audio DAC control. The serial control interface provides access to a wide range of features including on-chip mute, attenuation and phase reversal. A hardware controllable interface is also available. It is pin-compatible with the WM8736, (apart from RSTB pin which is typically unused). The WM8746 is an ideal device to interface to AC-3, DTS, and MPEG audio decoders for surround sound applications, or for use in “universal” high definition audio players supporting DVD-A formats. • • 6-Channel DAC Audio Performance • − 106dB SNR (‘A’ weighted @ 48kHz) DAC − -95dB THD DAC Sampling Frequency: 8kHz – 192kHz • • 3-Wire Serial Control Interface Programmable Audio Data Interface Modes − I2S, Left, Right Justified or DSP • − 16/20/24/32 bit Word Lengths Independent Digital Volume Control on Each Channel with 127.5dB Range in 0.5dB Steps 3.0V – 5.5V Supply Operation • • • 28-Pin SSOP Package Exceeds Dolby Class A Performance Requirements Pin Compatible with WM8736 • APPLICATIONS • • • DVD and DVD ‘Universal’ Players Home theatre systems Digital broadcast receivers BLOCK DIAGRAM ML/I2S SCKI MC/IWL MD/DM MODE MUTE WM8746 CONTROL INTERFACE PDWN PDWN PDWN DEEMPH RxA[23:0] LxA[23:0] UPDATE PL[3:0] ATC MUTE PDWN LRP BCP FMT[1:0] IWL[1:0] L0A[7:0] BCKIN Digital Filter Sigma Delta Modulator Stereo DAC OUT0L GR0 OUT0R Digital Filter Sigma Delta Modulator Stereo DAC OUT1L GR1 OUT1R Digital Filter Sigma Delta Modulator Stereo DAC OUT2L GR2 OUT2R LRCIN LRCIN2 R0A[7:0] L1A[7:0] AUDIO INTERFACE DAC CHANNEL CONTROL R1A[7:0] DIN0 L2A[7:0] DIN1 DIN2 R2A[7:0] DVDD DGND AGND1 AGND2 WOLFSON MICROELECTRONICS plc To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/ AVDD1 AVDD2 CAP Production Data, March 2006, Rev 4.0 Copyright 2006 Wolfson Microelectronics plc WM8746 Production Data TABLE OF CONTENTS DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................3 ORDERING INFORMATION ..................................................................................3 PIN DESCRIPTION ................................................................................................4 ABSOLUTE MAXIMUM RATINGS.........................................................................5 DC ELECTRICAL CHARACTERISTICS ........................................................................ 6 AC ELECTRICAL CHARACTERISTICS ........................................................................ 6 TERMINOLOGY ............................................................................................................ 7 MASTER CLOCK TIMING ............................................................................................. 8 DIGITAL AUDIO INTERFACE TIMING.......................................................................... 8 DIGITAL CONTROL INTERFACE ................................................................................. 9 DEVICE DESCRIPTION.......................................................................................10 INTRODUCTION ......................................................................................................... 10 AUDIO DATA SAMPLING RATES............................................................................... 10 DIGITAL AUDIO INTERFACE ..................................................................................... 11 MODES OF OPERATION ........................................................................................... 14 SOFTWARE CONTROL MODES................................................................................ 15 HARDWARE CONTROL MODES ............................................................................... 21 SOFTWARE CONTROL INTERFACE......................................................................... 22 REGISTER MAP...................................................................................................23 DAC FILTER RESPONSES .................................................................................26 DIGITAL DE-EMPHASIS CHARACTERISTICS ...................................................27 RECOMMENDED EXTERNAL COMPONENTS ..................................................28 RECOMMENDED EXTERNAL COMPONENTS VALUES ........................................... 28 DECOUPLING APPLICATIONS INFORMATION ................................................29 SUPPLY PINS DESCRIPTION.................................................................................... 29 DC ELECTRICAL CHARACTERISTICS ...................................................................... 29 DECOUPLING EXAMPLES......................................................................................... 29 RECOMMENDED ANALOGUE LOW-PASS FILTER (OPTIONAL) ....................30 PACKAGE DIMENSIONS ....................................................................................31 IMPORTANT NOTICE ..........................................................................................32 ADDRESS: .................................................................................................................. 32 w March 2006, PD Rev 4.0 2 WM8746 Production Data PIN CONFIGURATION ORDERING INFORMATION DEVICE WM8746SEDS TEMPERATURE RANGE PACKAGE MOISTURE SENSITIVITY LEVEL PEAK SOLDERING TEMPERATURE -25 to +85oC 28-lead SSOP MSL1 260°C MSL1 260°C (Pb-free) WM8746SEDS/R -25 to +85oC 28-lead SSOP (Pb-free, tape and reel) Note: Reel quantity = 2,000 w March 2006, PD Rev 4.0 3 WM8746 Production Data PIN DESCRIPTION PIN NAME TYPE 1 DVDD Supply DESCRIPTION Digital Positive Supply. 2 SCKI Digital input System Clock Input 3 BCKIN Digital input Audio Data Bit Clock Input. 4 LRCIN Digital input DAC Sample Rate Clock Input 5 DIN0 Digital input Channel 0 Serial Audio Data Input. 6 DIN1 Digital input Channel 1 Serial Audio Data Input. 7 DIN2 Digital input 8 MODE Digital input Internal pull-up Control Method Selection Pin. Low = Software Mode High = Hardware Control Mode 9 MUTE Digital bidirectional Mute Control Pin in PCM Mode. Channel 2 Serial Audio Data Input. Input Output (Automute Enabled) Low: Not Mute Low: Mute Off High: Mute High: Mute On (Zero Flag) Z: Automute 10 LRCIN2 Digital input Internal pull-down 2nd LRCIN for use in mixed 192kHz/96kHz operation (bit 2SPD = ‘hi’) Digital GND 11 DGND Supply 12 ML/I2S Digital input Internal pull-up Software mode: 3-Wire Serial Control Latch Hardware Mode: Input Format Selection: 13 MC/IWL Digital input Internal pull-up Software Mode: 3-Wire Serial Control Clock Input Hardware mode: Input Word Length Selection: 14 MD/DM Digital input Software mode: 3-Wire Serial Control Data Input Hardware mode: De-emphasis selection 15 AVDD2 Supply 16 CAP Analogue output Analogue Internal Mid-Rail Reference De-Coupling Point 17 OUT2L Analogue output Left Channel 2 Output. 18 GR2 Analogue input 19 OUT2R Analogue output 20 AGND1 Supply 21 OUT1L Analogue output 22 GR1 Analogue input 23 OUT1R Analogue output 24 AGND2 Supply 25 OUT0L Analogue output 26 GR0 Analogue input 27 OUT0R Analogue output 28 AVDD1 Supply Analogue Positive DAC Reference Channel 2 Negative Reference. Right Channel 2 Output. Analogue GND Left Channel 1 Output. Channel 1 Negative Reference. Right Channel 1 Output. Analogue GND Left Channel 0 Output. Channel 0 Negative Reference. Right Channel 0 Output. Analogue VDD Note: 1. Digital input pins have Schmitt trigger input buffers w March 2006, PD Rev 4.0 4 WM8746 Production Data ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. MIN MAX Digital supply voltage -0.3V +7V Analogue supply voltage -0.3V +7V Voltage range digital inputs DGND -0.3V DVDD +0.3V Voltage range analogue inputs AGND -0.3V AVDD +0.3V CONDITION Master Clock Frequency 37MHz Operating temperature range, TA -25°C +85°C Storage temperature after soldering -65°C +150°C w March 2006, PD Rev 4.0 5 WM8746 Production Data DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL Digital supply range Analogue supply range Ground TEST CONDITIONS MIN TYP MAX UNIT DVDD 3.0 5.5 V AVDD1, AVDD2 3.0 5.5 V AGND, GR0,GR1, DGND 0 Difference DGND to AGND -0.3 0 V +0.3 V Analogue supply current AVDD = 5V 58 Digital supply current DVDD = 5V 22 mA AVDD = 3.3V 57 mA Analogue supply current Digital supply current mA DVDD = 3.3V 11 mA Analogue supply current Power down, stop clock 0.4 mA Digital supply current Power down, stop clock 0.09 mA Note: 1. The digital supply voltages must not exceed the analogue supply voltages. AC ELECTRICAL CHARACTERISTICS Test Conditions AVDD = DVDD = 5V, AGND = 0V = DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT 0.8 V Digital Logic Levels (TTL Levels) Input LOW level VIL Input HIGH level VIH Output LOW VOL IOL = 2mA Output HIGH VOH IOH = 2mA 2.0 V 0.4 2.4 V V Analogue Reference Levels Reference voltage VCAP (AVDD2GR2)/2 V Potential divider resistance RCAP 25k Ω DAC Output (Load = 10kΩ 50pF) 0dBFs Full scale output voltage At DAC outputs SNR (Note 1,2,3) A-weighted, @ fs = 48kHz SNR (Note 1,2,3) 1.1 x AVDD1/5 106 dB A-weighted @ fs = 96kHz 105 dB SNR (Note 1,2,3) A-weighted @ fs = 192kHz 105 dB SNR (Note 1,2,3) A-weighted, @ fs = 48kHz AVDD=DVDD=3.3V 103 dB SNR (Note 1,2,3) A-weighted @ fs = 96kHz AVDD=DVDD=3.3V 103 dB SNR (Note 1,2,3) Non ‘A’ weighted @ fs = 48kHz AVDD=DVDD=5V 103 dB -95 dB THD (Note 1,2,3) THD+N (Dynamic range, Note 2) DAC channel separation w 100 Vrms 1kHz, 0dBFs 1kHz, -60dBFs -100 -106 dB 100 dB March 2006, PD Rev 4.0 6 WM8746 Production Data Test Conditions AVDD = DVDD = 5V, AGND = 0V = DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Analogue Output Levels Output level Load = 10kΩ, 0 dBFS, (AVDD=5.0V) 1.1 Load = 10kΩ, 0 dBFS, (AVDD=3.3V) 0.73 Gain mismatch channel-to-channel Minimum resistance load Maximum capacitance load Vrms ±1 %FSR To midrail or a.c. coupled 1 kΩ To midrail or a.c. coupled (AVDD = 3.3V) 1 kΩ 5V or 3.3V Output d.c. level 100 pF (AVDD1AGND)/2 V 2.0 V Power On Reset (POR) POR threshold Notes: 1. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’ weighted over a 20Hz to 20kHz bandwidth. 2. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. 3. CAP decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance). TERMINOLOGY 1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). 2. Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB). 3. THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal. 4. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band). 5. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other. 6. Pass-Band Ripple - Any variation of the frequency response in the pass-band region. w March 2006, PD Rev 4.0 7 WM8746 Production Data MASTER CLOCK TIMING tSCKIL SCKI tSCKIH tSCKIY Figure 1 Master Clock Timing Requirements Test Conditions AVDD = DVDD = 5V, AGND = GR = DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT System Clock Timing Information SCKI System clock pulse width high tSCKIH 13 ns SCKI System clock pulse width low tSCKIL 13 ns SCKI System clock cycle time tSCKIY 26 ns 40:60 SCKI Duty cycle 60:40 Table 1 Master Clock Timing Requirements DIGITAL AUDIO INTERFACE TIMING tBCH tBCL BCLK tBCY DACLRC tDS tLRH tLRSU DIN0/1/2 tDH Figure 2 PCM Digital Audio Data Timing Test Conditions AVDD = DVDD = 5V, AGND = GR = DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information BCKIN cycle time tBCY 40 ns BCKIN pulse width high tBCH 16 ns BCKIN pulse width low tBCL 16 ns LRCIN set-up time to BCKIN rising edge tLB 8 ns LRCIN hold time from BCKIN rising edge tBL 8 ns DIN0/1/2 set-up time to BCKIN rising edge tDS 8 ns DIN0/1/2 hold time from BCKIN rising edge tDH 8 ns Table 2 PCM Digital Audio Timing w March 2006, PD Rev 4.0 8 WM8746 Production Data DIGITAL CONTROL INTERFACE tMLL tMLH ML/I2S tMCY tMCH tCSS tSCS tMCL MC/IWL MD/DM LSB tDSU tDHO Figure 3 Control Interface Input Timing: 3-Wire Serial Control Mode Test Conditions AVDD = DVDD = 5V, AGND = GR = DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Program Register Input Information MC/IWL rising edge to ML/I2S rising edge tSCS 20 ns MC/IWL pulse cycle time tMCY 80 ns MC/IWL pulse width low tMCL 30 ns MC/IWL pulse width high tMCH 30 ns MD/DM to MC/IWL set-up time tDSU 20 ns MC/IWL to MD/DM hold time tDHO 20 ns ML/I2S pulse width low tMLL 20 ns ML/I2S pulse width high tMLH 20 ns ML/I2S rising to MC/IWL rising tCSS 20 ns Table 3 Control Interface Input Timing Information: 3-Wire Serial Control Mode w March 2006, PD Rev 4.0 9 WM8746 Production Data DEVICE DESCRIPTION INTRODUCTION WM8746 is a complete 6-channel stereo audio digital-to-analogue converter, including digital interpolation filter, multi-bit sigma delta with dither, and switched capacitor multi-bit stereo DAC and output smoothing filters. The device is implemented as three separate stereo DACs in a single package and controlled by a single interface. Each DAC has its own data input DIN0/1/2, and LRCIN, BCKIN and SCKI are shared between them. An additional LRCIN2 input is provided to allow for the front channels in a surround system to be run at higher sample rate than the other 4 channels (ie. 192kHz for front channels and 96kHz). In this mode the same SCKI is used for all channels, the front channels being run at twice the over-sampling rate of the other channels. Control of internal functionality of the device is by either hardware control (pin programmed) or software control (3-wire serial control interface). The MODE pin selects between hardware and software control. In software control mode, an SPI type interface is used. This interface may be asynchronous to the audio data interface. Control data will be re-synchronised to the audio processing internally. Operation using a system clock of 256fs, 384fs, 512fs or 768fs is provided, selection between clock rates being automatically detected. Sample rates (fs) from less than 8kHz to 96kHz are allowed, provided the appropriate system clock is input. Support is also provided for up to 192kHz using a system clock of 128fs or 192fs. 2 The audio data interface supports right, left and I S interface formats along with a highly flexible DSP serial port interface. When in hardware mode, the three serial interface pins become control pins to allow selection of input data format type (I2S or right justified), input word length (16, 20, 24, or 32-bit) and de-emphasis functions. AUDIO DATA SAMPLING RATES In a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio system’s Master Clock. The external master system clock can be applied directly through the SCKI input pin with no software configuration necessary. Note that on the WM8746, SCKI is used to derive clocks for the DAC path. The DAC path consists of DAC sampling clock, DAC digital filter clock and DAC digital audio interface timing. In a system where there are a number of possible sources for the reference clock it is recommended that the clock source with the lowest jitter be used to optimise the performance of the DAC. The system clock for WM8746 supports audio sampling rates from 128fs to 768fs, where fs is the audio sampling frequency (LRCIN) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The system clock is used to operate the digital filters and the noise shaping circuits. The WM8746 has a system clock detection circuit that automatically determines the relationship between the system clock frequency and the sampling rate (to within +/- 32 system clocks). If greater than 32 clocks error, the interface defaults to 768fs and maintains the output level at the last sample. The system clock should be synchronised with LRCIN, although the WM8746 is tolerant of phase differences or jitter on this clock. Table 4 shows the typical system clock frequency inputs for the WM8746. SAMPLING RATE (FS) (LRCIN) SYSTEM CLOCK FREQUENCY (MHZ) 128fs 192fs 256fs 384fs 512fs 768fs 32kHz 4.096 6.144 8.192 12.288 16.384 24.576 44.1kHz 5.6448 8.467 11.2896 16.9340 22.5792 33.8688 48kHz 6.144 9.216 12.288 18.432 24.576 36.864 96kHz 12.288 18.432 24.576 36.864 Unavailable Unavailable 192kHz 24.576 36.864 Unavailable Unavailable Unavailable Unavailable Table 4 System Clock Frequencies Versus Sampling Rate w March 2006, PD Rev 4.0 10 WM8746 Production Data DIGITAL AUDIO INTERFACE Audio data is applied to the internal DAC filters via the Digital Audio Interface. Five popular interface formats are supported: • Left Justified mode • Right Justified mode • I2S mode • DSP Mode A • DSP Mode B All 5 formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits, except right justified that does not support 32 bit data. DIN0/1/2 and LRCIN are sampled on the rising, or falling edge of BCKIN. In left justified, right justified and I2S modes, the digital audio interface receives data on the DIN0/1/2 inputs. Audio Data for each stereo channel is time multiplexed with LRCIN indicating whether the left or right channel is present. LRCIN is also used as a timing reference to indicate the beginning or end of the data words. In left justified, right justified and I2S modes, the minimum number of BCKINs per LRCIN period is twice the selected word length. LRCIN must be high for at least the word length number of BCKINs and low for at least the same. Any mark to space ratio on LRCIN is acceptable provided the above requirements are met. The WM8746 will automatically detect when data with a LRCIN period of exactly 32 is sent, and select 16 bit mode - overriding any previously programmed word length. Word length will revert to the previously programmed value if a LRCIN period other than 32 is detected. In DSP Mode A or B, all 6 channels are time multiplexed onto DIN0. LRCIN is used as a frame sync signal to identify the MSB of the first word. The minimum number of BCKINs per LRCIN period is 6 times the selected word length. Any mark to space ratio is acceptable on LRCIN provided the rising edge is correctly positioned. (see Figure 7, Figure 8) LEFT JUSTIFIED MODE In left justified mode, the MSB is sampled on the first rising edge of BCKIN following a LRCIN transition. LRCIN is high during the left samples and low during the right samples. 1/fs LEFT CHANNEL RIGHT CHANNEL LRCIN BCKIN DIN0/1/2 1 MSB 2 3 n-2 n-1 n LSB 1 MSB 2 3 n-2 n-1 n LSB Figure 4 Left Justified Mode Timing Diagram w March 2006, PD Rev 4.0 11 WM8746 Production Data RIGHT JUSTIFIED MODE In right justified mode, the LSB is sampled on the rising edge of BCKIN preceding a transition. LRCIN is high during the left samples and low during the right samples. LRCIN 1/fs LEFT CHANNEL RIGHT CHANNEL LRCIN BCKIN DIN0/1/2 1 2 3 n-2 n-1 MSB n 1 LSB 2 3 n-2 n-1 MSB n LSB Figure 5 Right Justified Mode Timing Diagram I2S MODE In I2S mode, the MSB is sampled on the second rising edge of BCKIN following a LRCIN transition. LRCIN is low during the left samples and high during the right samples. 1/fs LEFT CHANNEL RIGHT CHANNEL LRCIN BCKIN 1 BCKIN 1 BCKIN DIN0/1/2 1 2 3 n-2 n-1 n 1 LSB MSB 2 3 n-2 n-1 n LSB MSB 2 Figure 6 I S Mode Timing Diagram DSP MODE A In DSP mode A, the first bit is sampled on the BCKIN edge following the one which detects a low to high transition on LRCIN. 1 BCKIN 1 BCKIN 1/fs LRCIN BCKIN CHANNEL 0 LEFT DIN0 1 MSB 2 n-1 CHANNEL 0 RIGHT n 1 2 n-1 CHANNEL 1 LEFT n 1 2 CHANNEL 2 RIGHT n-1 NO VALID DATA n LSB Input Word Length (IWL) Figure 7 DSP Mode A Timing Diagram w March 2006, PD Rev 4.0 12 WM8746 Production Data DSP MODE B In DSP mode B, the first bit is sampled on the BCKIN edge which detects a low to high transition on LRCIN. 1/fs LRCIN BCKIN CHANNEL 0 LEFT DIN0 1 2 CHANNEL 0 RIGHT n n-1 MSB 1 2 CHANNEL 1 LEFT n n-1 1 CHANNEL 2 RIGHT 2 n-1 NO VALID DATA n 1 LSB Input Word Length (IWL) Figure 8 DSP Mode B Timing Diagram In both DSP modes, DAC0 left is always sent first, followed immediately by data words for the other 5 channels. No BCKIN edges are allowed between the data words. The word order is DAC0 left, DAC0 right, DAC1 left, DAC1 right, DAC2 left, DAC2 right. SPLIT RATE MODE The WM8746 can be used with differing sample rates on the front and rear channels. This allows extremely high quality audio to be played on the front two channels whilst the other channels use normal high quality data streams. This mode will only work with a front data rate of 192kHz and a rear rate of 96kHz but can be used with all the normal data formats except the two DSP modes and with the system at either 128fs or 192fs see Table 4. When running in split rate mode all the channels are clocked in using a common BCKIN; the front channels using LRCIN and all the other channels using LRCIN2 see Figure 9. 2/fs LEFT CHANNEL LEFT CHANNEL RIGHT CHANNEL RIGHT CHANNEL LRCIN BCKIN DIN0 1 2 MSB LRCIN2 DIN1/2 n LSB 1 2 MSB n LSB 1 2 MSB n LEFT CHANNEL 1 2 MSB n LSB 1 2 LSB n MSB LSB RIGHT CHANNEL 1 2 MSB n LSB Figure 9 Split Rate Audio Mode Timing Diagram Notes: 1. Figure 9 shows the timing for left justified however this is similar for right justified and I2S. 2. The edges of LRCIN and LRCIN2 must be coincidental. w March 2006, PD Rev 4.0 13 WM8746 Production Data MODES OF OPERATION Control of the various modes of operation for the WM8746 is either by software control over the serial interface ,or by hard-wired pin control. Selection of software or hardware mode is via the MODE pin. The following functions may be controlled either via the serial control interface or by hard wiring of the appropriate pins. OPTIONS SOFTWARE CONTROL DEFAULT VALUE PIN 8: MODE = 0 HARDWARE CONTROL BEHAVIOUR PIN 8: MODE = 1 Input audio data format Right justified Left justified I2S format DSP formats FMT = 00 (default) FMT = 01 FMT = 10 FMT = 11 Pin 12, 13: ML/I2S, MC/IWL = 00, 01 or 10 Not available in hardware mode Pin 12, 13: ML/I2S, MC/IWL = 11 Not available in hardware mode Input word length 16 20 24 32 IWL[1:0] = 00 IWL[1:0] = 01 IWL[1:0] = 10 (default) IWL[1:0] = 11 Pin 12, 13: ML/I2S, MC/IWL = 00 (RJ) Pin 12, 13: ML/I2S, MC/IWL = 01 (RJ) Pin 12, 13: ML/I2S, MC/IWL = 10 (RJ) Pin 12, 13: ML/I2S, MC/IWL = 11 (I2S) De-emphasis selection On Off DEEMPH = 1 DEEMPH = 0 (Default) Pin 14: MD/DM = 1 Pin 14: MD/DM = 0 Mute On Off MUTE = 1 MUTE = 0 (default) Pin 9: MUTE = 1 Pin 9: MUTE = 0 Input LRCIN polarity Normal Inverted LRP = 0 (default) LRP = 1 Not available in hardware mode, default value set Volume control Lch, Rch individually Lch, Rch common ATC = 0; 0dB (default) Not available in hardware mode, gain defaults to 0dB Infinite zero detect On Off IZD = 1 IZD = 0 (default) Automute function controlled from MUTE pin low = never mute floating = automute enable high = mute Power down Chip on Chip off PWDN = 0 (default) PWDN = 1 Run SCKI Stop SCKI DAC output control See Table 6 for all options Default is PL[3:0] = 1001, stereo mode Not available in hardware mode FUNCTION ATC = 1 Table 5 Control Function Summary w March 2006, PD Rev 4.0 14 WM8746 Production Data SOFTWARE CONTROL MODES DIGITAL AUDIO INTERFACE CONTROL REGISTERS Interface format is selected via the FMT[1:0] register bits: REGISTER ADDRESS BIT LABEL DEFAULT 0000011 Interface Control 1:0 FMT[1:0] 00 DESCRIPTION Interface format Select 00 : right justified mode 01: left justified mode 10: I2S mode 11: DSP mode A or B In left justified, right justified or I2S modes, the LRP register bit controls the polarity of LRCIN. If this bit is set high, the expected polarity of LRCIN will be the opposite of that shown Figure 4, Figure 5 and Figure 6. Note that if this feature is used as a means of swapping the left and right channels, a 1 sample phase difference will be introduced. REGISTER ADDRESS 0000011 Interface Control BIT LABEL DEFAULT 2 LRP 0 DESCRIPTION LRCIN Polarity 0 : normal LRCIN polarity 1: inverted LRCIN polarity In DSP modes, the LRCIN register bit is used to select between early and late modes: REGISTER ADDRESS 0000011 Interface Control BIT LABEL DEFAULT 2 LRP 0 DESCRIPTION DSP Format 0: Mode A 1: Mode B By default, LRCIN and DIN0/1/2 are sampled on the rising edge of BCKIN and should ideally change on the falling edge. Data sources which change LRCIN and DIN0/1/2 on the rising edge of BCKIN can be supported by setting the BCP register bit. Setting BCP to 1 inverts the polarity of BCKIN to the inverse of that shown in Figure 4, Figure 5, Figure 6, Figure 7 and Figure 8. REGISTER ADDRESS 0000011 Interface Control BIT LABEL DEFAULT 3 BCP 0 DESCRIPTION BCKIN Polarity 0 : normal BCKIN polarity 1: inverted BCKIN polarity The IWL[1:0] bits are used to control the input word length. REGISTER ADDRESS BIT LABEL DEFAULT 0000011 Interface Control 5:4 IWL[1:0] 10 DESCRIPTION Input Word Length 00 : 16 bit data 01: 20 bit data 10: 24 bit data 11: 32 bit data Note: If 32-bit mode is selected in right justified mode, the WM8746 defaults to 24 bits. In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If the DAC is programmed to receive 16 or 20 bit data, the WM8746 pads the unused LSBs with zeros. If the DAC is programmed into 32 bit mode, the 8 LSBs are ignored. The PHASE bits control the orientation of the data output of the three stereo channels. By default all the channels are non-inverting. w REGISTER ADDRESS BIT LABEL DEFAULT 0000011 Interface Control 8:6 PHASE 000 DESCRIPTION Output phase direction 1 in bit 6 reverses OUT0L/R. 1 in bit 7 reverses OUT1L/R. 1 in bit 8 reverses OUT2L/R. March 2006, PD Rev 4.0 15 WM8746 Production Data MUTE MODES Setting the MUTE register bit will apply a 'soft' mute to the input of the digital filters: REGISTER ADDRESS 0000010 DAC Channel Control BIT LABEL DEFAULT 0 MUTE 0 DESCRIPTION Soft Mute select 0 : Normal Operation 1: Soft mute all channels 1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 0 0.001 0.002 0.003 0.004 0.005 0.006 Time(s) Figure 10 Application and Release of Soft Mute Figure 10 shows the application and release of MUTE whilst a full amplitude sinusoid is being played at 48kHz sampling rate. When MUTE (lower trace) is asserted, the output (upper trace) begins to decay exponentially from the DC level of the last input sample. The output will decay towards VCAP with a time constant of approximately 64 input samples. If MUTE is applied for 1024 or more input samples, the outputs will be connected directly to VCAP - this feature can be disabled using the IZD (infinite zero detect) bit. When MUTE is de-asserted, the output will restart almost immediately from the current input sample. Note that all other means of muting the DAC channels: setting the PL[3:0] bits to 0, setting the PWDN bit or setting attenuation to 0 will cause much more abrupt muting of the output. Setting the IZD register bit will enable the infinite zero detect feature: REGISTER ADDRESS 0000010 DAC Channel Control BIT LABEL DEFAULT 4 IZD 0 DESCRIPTION Internal Analogue Mute Disable 0 : Disable Analogue Mute 1: Enable Analogue Mute With IZD=1, applying MUTE for 1024 consecutive input samples will cause all outputs to be connected directly to VCAP. This also happens if 2048 consecutive zero input samples are applied to all 6 channels, and IZD=0. It will be removed as soon as any channel receives a non-zero input. The MUTE pin can be used as an input. In this case it performs the same function as the MUTE register bit. Driving the MUTE pin high will apply a 'soft' mute. Driving it low again, will remove the MUTE immediately. Note that this hardware mute feature doesn't require the MODE pin to be set high. w March 2006, PD Rev 4.0 16 WM8746 Production Data MUTE PIN DESCRIPTION 0 Normal Operation 1 Mute all DAC channels Floating MUTE becomes an output to indicate when IZD occurs. H = IZD detected (MUTE enabled) L = IZD not detected (MUTE disabled) A diagram showing how the various MUTE modes interact is shown below in Figure 11. IZD (Register Bit) AUTOMUTED (Internal Signal) Ω 10kΩ SOFTMUTE (Internal Signal) MUTE PIN MUTE (Register Bit) Figure 11 Selection Logic for MUTE Modes The MUTE pin behaves as a bi-directional function, that is, as an input to select MUTE or NOTMUTE, or as an output indication of automute operation. MUTE is active high; taking the pin high causes the filters to soft mute, ramping down the audio signal over a few milliseconds. Taking MUTE low again allows data into the filter. The automute function detects a series of zero value audio samples of 1024 samples long being applied to all 6 channels. After such an event, a latch is set whose output (AUTOMUTED) is wire OR’ed through a 10kohm resistor to the MUTE pin. Thus if the MUTE pin is not being driven, the automute function will assert MUTE. If MUTE is tied low, AUTOMUTED is overridden and will not mute. If MUTE is driven from a source follower, or diode, then both MUTE and automute functions are available. If MUTE is not driven, AUTOMUTED appears as a weak output (10k source impedance) so can be used to drive external mute circuits. The automute signal is AND’ed with IZD, this qualified mute signal then being OR’ed into the SOFTMUTE control. Therefore, in software mode, automute operation may be controlled with the IZD control bit. DE-EMPHASIS MODE Setting the DEEMPH register bit puts all the digital filters into de-emphasis mode: REGISTER ADDRESS 0000010 DAC Channel Control BIT LABEL DEFAULT 1 DEEMPH 0 DESCRIPTION De-emphasis mode select: 0 : Normal Mode 1: De-emphasis Mode Refer to Figure 18 - Figure 23 for details of the De-Emphasis filtering effects at different sample rates. In hardware mode (MODE=1) driving the MD/DM pin high has the same effect as setting the DEEMPH bit: w MODE PIN MD/DM PIN 0 ignored DESCRIPTION 1 0 Normal Mode 1 1 De-Emphasis Mode De-Emphasis controlled from DEEMPH register bit March 2006, PD Rev 4.0 17 WM8746 Production Data POWERDOWN MODE Setting the PWDN register bit immediately connects all outputs to VCAP and selects a low power mode. All trace of the previous input samples is removed, but all control register settings are preserved. When PWDN is cleared again the first 16 input samples will be ignored as the FIR will repeat it's power-on initialisation sequence. REGISTER ADDRESS BIT LABEL DEFAULT 2 PWDN 0 0000010 DAC Channel Control DESCRIPTION Power Down Mode Select: 0 : Normal Mode 1: Power Down Mode ATTENUATOR CONTROL MODE Setting the ATC register bit causes the left channel attenuation settings to be applied to both left and right channels for all three pairs of DACs from the next audio input sample. No update to the attenuation registers is required for ATC to take effect. REGISTER ADDRESS BIT LABEL DEFAULT 3 ATC 0 0000010 DAC Channel Control DESCRIPTION Attenuator Control Mode: 0 : Right channels use Right attenuations 1: Right Channels use Left Attenuations DAC OUTPUT CONTROL The DAC output control word determines how the left and right inputs to the audio Interface are applied to the left and right DACs: REGISTER ADDRESS BIT LABEL DEFAULT 0000010 DAC Control 8:5 PL[3:0] 1001 DESCRIPTION PL[3:0] Left Output Right Output 0000 Mute Mute 0001 Left Mute 0010 Right Mute 0011 (L+R)/2 Mute 0100 Mute Left 0101 Left Left 0110 Right Left 0111 (L+R)/2 Left 1000 Mute Right 1001 Left Right 1010 Right Right 1011 (L+R)/2 Right 1100 Mute (L+R)/2 1101 Left (L+R)/2 1110 Right (L+R)/2 1111 (L+R)/2 (L+R)/2 Table 6 Input to Output Control w March 2006, PD Rev 4.0 18 WM8746 Production Data ATTENUATION CONTROL Each DAC channel can be attenuated digitally before being applied to the digital filter. Attenuation is 0dB by default but can be set between 0 and 127.5dB in 0.5dB steps using the 8 Attenuation control bits. All attenuation registers are double latched allowing new values to be pre-latched to several channels before being updated synchronously. Setting the UPDATE bit on any attenuation write will cause all pre-latched values to be immediately applied to the DAC channels. A master attenuation register is also included, allowing all attenuations to be set to the same value in a single write. REGISTER ADDRESS BIT LABEL DEFAULT 0000000 Attenuation DACL0 7:0 L0A[7:0] 11111111 (0dB) 8 UPDATE Not latched 0000001 Attenuation DACR0 7:0 R0A[7:0] 11111111 (0dB) 8 UPDATE Not latched 0000100 Attenuation DACL1 7:0 L1A[7:0] 11111111 (0dB) 8 UPDATE Not latched 0000101 Attenuation DACR1 7:0 R1A[7:0] 11111111 (0dB) 8 UPDATE Not latched 0000110 Attenuation DACL2 7:0 L2A[7:0] 11111111 (0dB) 8 UPDATE Not latched 0000111 Attenuation DACR2 7:0 R2A[7:0] 11111111 (0dB) 8 UPDATE Not latched 0001000 Master Attenuation (all channels) 7:0 MASTA[7:0] 11111111 (0dB) 8 UPDATE Not latched DESCRIPTION Attenuation data for DACL0 in 0.5dB steps, see Table 8. Controls simultaneous update of all Attenuation Latches 0: Store DACL0 in intermediate latch (no change to output) 1: Store DACL0 and update attenuation on all channels. Attenuation data for DACR0 in 0.5dB steps, see Table 8. Controls simultaneous update of all Attenuation Latches 0: Store DACR0 in intermediate latch (no change to output) 1: Store DACR0 and update attenuation on all channels. Attenuation data for DACL1 in 0.5dB steps, see Table 8. Controls simultaneous update of all Attenuation Latches 0: Store DACL1 in intermediate latch (no change to output) 1: Store DACL1 and update attenuation on all channels. Attenuation data for DACR1 in 0.5dB steps, see Table 8. Controls simultaneous update of all Attenuation Latches 0: Store DACR1 in intermediate latch (no change to output) 1: Store DACR1 and update attenuation on all channels. Attenuation data for DACL2 in 0.5dB steps, see Table 8. Controls simultaneous update of all Attenuation Latches 0: Store DACL2 in intermediate latch (no change to output) 1: Store DACL2 and update attenuation on all channels. Attenuation data for DACR2 in 0.5dB steps, see Table 8. Controls simultaneous update of all Attenuation Latches 0: Store DACR2 in intermediate latch (no change to output) 1: Store DACR2 and update attenuation on all channels. Attenuation data for all channels in 0.5dB steps, see Table 8. Controls simultaneous update of all Attenuation Latches 0: Store MASTA[7:0] in all intermediate latches (no change to output) 1: Store MASTA[7:0] and update attenuation on all channels. Table 7 Attenuation Register Map Note: The UPDATE bit is not latched. If UPDATE=0, the Attenuation value will be written to the pre-latch but not applied to the relevant DAC. If UPDATE=1, all pre-latched values will be applied from the next input sample. Writing to MASTA[7:0] overwrites any values previously sent to L0A[7:0], L1A[7:0], L2A[7:0], R0A[7:0], R1A[7:0], R2A[7:0]. w March 2006, PD Rev 4.0 19 WM8746 Production Data DAC OUTPUT ATTENUATION Register bits [7:0] of L0A and R0A control the left and right channel attenuation of DAC 0. Register bits [7:0] of L1A and R1A control the left and right channel attenuation of DAC 1. Register bits [7:0] of L2A and R2B control the left and right channel attenuation of DAC 2. Register bits [7:0] of MASTA are a register that can be used to control attenuation of all channels. Table 8 shows how the attenuation levels are selected from the 8-bit words. XA[7:0] ATTENUATION LEVEL 00(hex) -∞dB (mute) 01(hex) -127.5dB : : : : : : FE(hex) -0.5dB FF(hex) 0dB Table 8 Attenuation Control Levels EXTENDED INTERFACE CONTROL It is possible to run the WM8746 channels at different rates with the front two channels running at twice the rate of the rear four channels. In this mode which is enabled by bit 0 of register 9, the interface runs at the faster data rate but pin 10 (LRCIN2) acts as the framing LRCIN for the rear channels see Figure 9. REGISTER ADDRESS 0001001 Split rate mode BIT LABEL DEFAULT 0 2SPD 0 DESCRIPTION Activates the split rate mode 0: Normal operation 1: Split rate operation When the WM8746 receives updates to the volume levels it will, by default, wait for the signal to pass through the VCAP voltage level before applying the change to the output. This zero cross detect function ensures that minimal distortion is seen on the output when the volume is changed and is applied separately to each channel. REGISTER ADDRESS 0001001 Zero crossing detect w BIT LABEL DEFAULT 1 ZCD 0 DESCRIPTION Controls the ZCD 0: Enabled 1: Disabled March 2006, PD Rev 4.0 20 WM8746 Production Data HARDWARE CONTROL MODES When the MODE pin is held high the following hardware modes of operation are available. MUTE AND AUTOMUTE OPERATION Pin 9 (MUTE) controls selection of MUTE directly, and can be used to enable and disable the automute function, or as an output of the automuted signal. AUTOMUTED (Internal Signal) Ω 10kΩ SOFTMUTE (Internal Signal) MUTE PIN Figure 12 Mute Circuit Operation The MUTE pin behaves as a bi-directional function, that is, as an input to select MUTE or NOTMUTE, or as an output indication of automute operation. MUTE is active high; taking the pin high causes the filters to soft mute, ramping down the audio signal over a few milliseconds. Taking MUTE low again allows data into the filter. The automute function detects a series of zero value audio samples of 1024 samples long being applied to all 6 channels. After such an event, a latch is set whose output (AUTOMUTED) is wire OR’ed through a 10kohm resistor to the MUTE pin. Thus if the MUTE pin is not being driven, the automute function will assert MUTE. If MUTE is tied low, AUTOMUTED is overridden and will not mute. If MUTE is driven from a source follower, or diode, then both MUTE and automute functions are available. If MUTE is not driven, AUTOMUTED appears as a weak output (10k source impedance) so can be used to drive external mute circuits. ML/I2S AND MC/IWL INPUT FORMAT SELECTION In hardware mode, pins 12 and 13 become input controls for selection of input data format type and input data word length, see Table 5. I2S mode is designed to support any word length provided enough bit clocks are sent. ML/I2S MC/IWL INPUT DATA MODE 0 0 16-bit right justified 0 1 20-bit right justified 1 0 24-bit right justified 1 1 I2S mode Table 9 Control of Input Data Format Type and Input Data Word Length MD/DM DE-EMPHASIS In hardware mode, pin 14 becomes an input control for selection of de-emphasis filtering to be applied. See Table 5. MD/DM DE-EMPHASIS MODE 0 De-emphasis off 1 De-emphasis on Table 10 De-emphasis Control w March 2006, PD Rev 4.0 21 WM8746 Production Data SOFTWARE CONTROL INTERFACE The software control interface uses a 3-wire serial control interface. Selection of interface format is achieved by setting the state of the MODE pin. MODE INTERFACE FORMAT 0 Software Control Mode 1 Hardware Control Mode Table 11 Control Interface Mode Selection 3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE The WM8746 can be controlled using a 3-wire serial interface. MD/DM is used for the program data, MC/IWL is used to clock in the program data and ML/I2S is use to latch in the program data. The 3wire interface protocol is shown in Figure 13. ML/I2S MC/IWL MD/DM A6 A5 A4 A3 A2 A1 A0 D8 D7 D6 D5 D4 D3 D2 D1 D0 Figure 13 3-wire Serial Interface Notes: w 1. A[6:0] are Control Address Bits 2. D[8:0] are Control Data Bits March 2006, PD Rev 4.0 22 WM8746 Production Data REGISTER MAP The complete register map is shown below. The detailed description can be found in the relevant text of the device description. There are 9 registers with 9 bits per register. These can be controlled using the Control Interface. A6 A5 A4 A3 A2 A1 A0 D8 D7 D6 D5 D4 D3 D2 D1 D0 M0 0 0 0 0 0 0 0 UPDATE L0A7 L0A 6 L0A 5 L0A 4 L0A 3 L0A 2 L0A 1 L0A 0 M1 0 0 0 0 0 0 1 UPDATE R0A7 R0A 6 R0A 5 R0A 4 R0A 3 R0A 2 R0A 1 R0A 0 M2 0 0 0 0 0 1 0 PL3 PL2 PL1 PL0 IZD ATC M3 0 0 0 0 0 1 1 REV2 REV1 REV0 IWL1 IWL0 BCP LRP FMT1 FMT0 M4 0 0 0 0 1 0 0 UPDATE L1A7 L1A 6 L1A 5 L1A 4 L1A 3 L1A 2 L1A 1 L1A 0 M5 0 0 0 0 1 0 1 UPDATE R1A7 R1A 6 R1A 5 R1A 4 R1A 3 R1A 2 R1A 1 R1A 0 M6 0 0 0 0 1 1 0 UPDATE L2A7 L2A 6 L2A 5 L2A 4 L2A 3 L2A 2 L2A 1 L2A 0 M7 0 0 0 0 1 1 1 UPDATE R2A7 R2A 6 R2A 5 R2A 4 R2A 3 R2A 2 R2A 1 R2A 0 M8 0 0 0 1 0 0 0 UPDATE MASTA7 MASTA 6 MASTA 5 MASTA 4 MASTA 3 MASTA 2 MASTA 1 MASTA 0 M9 0 0 0 1 0 0 1 0 0 0 0 0 0 PDWN DEEMPH 0 ZCD MUTE 2SPD Table 12 Register Map REGISTER ADDRESS BIT LABEL DEFAULT 0000000 Attenuation DACL0 7:0 L0A[7:0] 11111111 (0dB) 8 UPDATE Not latched 0000001 Attenuation DACR0 7:0 R0A[7:0] 11111111 (0dB) 8 UPDATE Not latched w DESCRIPTION Attenuation level of left channel DACL0 in 0.5dB steps, see Table 8. Controls simultaneous update of all Attenuation Latches 0: Store DACL0 in intermediate latch (no change to output) 1: Store DACL0 and update attenuation on all channels. Attenuation level of left channel DACR0 in 0.5dB steps, see Table 8. Controls simultaneous update of all Attenuation Latches 0: Store DACR0 in intermediate latch (no change to output) 1: Store DACR0 and update attenuation on all channels. March 2006, PD Rev 4.0 23 WM8746 REGISTER ADDRESS 0000010 DAC Control 0000011 Interface Control Production Data BIT LABEL DEFAULT 0 MUTE 0 Left and Right DACs soft mute control 0: No Mute 1: Mute 1 DEEMPH 0 De-emphasis Control 0: Normal Response (see Figure 14 - Figure 17) 1: De-emphasis Response (see Figure 18 - Figure 23) 2 PWDN 0 Left and Right DACs Power-down Control 0: All DACs running, output is active 1: All DACs in power saving mode, output muted 3 ATC 0 Attenuator Control 0: All DACs use attenuations as programmed. 1: Right chan. DACs use corresponding left DAC attenuations 4 IZD 0 Infinite zero detection circuit control and automute control 0: Infinite zero detect disabled 1: Infinite zero detect enabled 8:5 PL[3:0] 1001 1:0 FMT[1:0] 00 2 LRP 0 DESCRIPTION DAC Output Control PL[3:0] Left Output Right Output PL[3:0] Left Output Right Output 0000 Mute Mute 1000 Mute Right 0001 Left Mute 1001 Left Right 0010 Right Mute 1010 Right Right 0011 (L+R)/2 Mute 1011 (L+R)/2 Right 0100 Mute Left 1100 Mute (L+R)/2 0101 Left Left 1101 Left (L+R)/2 0110 Right Left 1110 Right (L+R)/2 0111 (L+R)/2 Left 1111 (L+R)/2 (L+R)/2 Interface format select 00: right justified mode 01: left justified mode 10: I2S mode 11: DSP Mode A or B LRCIN Polarity or LRCIN Phase 2 Left Justified / Right Justified / I S 0: Standard LRCIN Polarity 1: Inverted LRCIN Polarity DSP Mode 0: DSP Mode A 1: DSP Mode B 3 BCP 0 BCKIN Polarity 0: Normal (DIN[2:0] and LRCIN sampled on rising edge) 1: Inverted (DIN[2:0] and LRCIN sampled on falling edge) 5:4 WL[1:0] 10 Input Word Length 00: 16-bit Mode 01: 20-bit Mode 10: 24-bit Mode 11: 32-bit Mode (not supported in right justified mode) 8:6 PHASE 000 Controls the output phase of the three stereo channels Bit 6 reverses the phase of data output on OUT0L/R. Bit 7 reverses the phase of data output on OUT1L/R. Bit 8 reverses the phase of data output on OUT2L/R. w March 2006, PD Rev 4.0 24 WM8746 REGISTER ADDRESS 0000100 Attenuation DACL1 0000101 Attenuation DACR1 0000110 Attenuation DACL2 0000111 Attenuation DACR2 0001000 Master Attenuation (all channels) 0001001 Extended interface control Production Data BIT LABEL DEFAULT DESCRIPTION 7:0 L1A[7:0] 11111111 (0dB) 8 UPDATE Not latched 7:0 R1A[7:0] 11111111 (0dB) 8 UPDATE Not latched 7:0 L2A[7:0] 11111111 (0dB) 8 UPDATE Not latched 7:0 R2A[7:0] 11111111 (0dB) 8 UPDATE Not latched 7:0 MASTA[7:0] 11111111 (0dB) 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0: Store MASTA[7:0] in all intermediate latches (no change to output) 1: Store DACR0 and update attenuation on all channels 0 2SPD 0 Activates the split rate mode where the front channels run at 192kHz and the rear four channels run at 96kHz. 0: Normal operation. 1: Split rate operation. 1 ZCD 0 Controls the operation of the zero crossing detect mechanism which ensures that the volume is only updated on each channel when the signal passes through midrail. 0: Enable zero detect. 1: Disable zero detect. Attenuation level of left channel DACL1 in 0.5dB steps. See Table 8 Controls simultaneous update of all Attenuation Latches 0: Store DACL1 in intermediate latch (no change to output) 1: Store DACL1 and update attenuation on all channels. Attenuation level of right channel DACR1 in 0.5dB steps, see Table 8. Controls simultaneous update of all Attenuation Latches 0: Store DACR1 in intermediate latch (no change to output) 1: Store DACR1 and update attenuation on all channels. Attenuation level of left channel DACL2 in 0.5dB steps, see Table 8. Controls simultaneous update of all Attenuation Latches 0: Store DACL2 in intermediate latch (no change to output) 1: Store DACL2 and update attenuation on all channels. Attenuation level of right channel DACR2 in 0.5dB steps, see Table 8. Controls simultaneous update of all Attenuation Latches 0: Store DACR2 in intermediate latch (no change to output) 1: Store DACR2 and update attenuation on all channels. Attenuation data for all channels in 0.5dB steps, see Table 8. Table 13 Register Map Description w March 2006, PD Rev 4.0 25 WM8746 Production Data DIGITAL FILTER CHARACTERISTICS PARAMETER TEST CONDITIONS MIN Passband SYMBOL ±0.05 dB 0.444fs Stopband -3dB TYP UNIT dB 0.487fs Passband Ripple Stopband Attenuation MAX f > 0.555fs ±0.05 dB -60 dB Table 14 Digital Filter Characteristics DAC FILTER RESPONSES 0.2 0 0.15 -20 -40 Response (dB) Response (dB) 0.1 -60 0.05 0 -0.05 -80 -0.1 -100 -0.15 -120 -0.2 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 Figure 14 DAC Digital Filter Frequency Response – 44.1, 48 and 96kHz 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5 Figure 15 DAC Digital Filter Ripple –44.1, 48 and 96kHz 0.2 0 0 -0.2 Response (dB) Response (dB) -20 -40 -0.4 -0.6 -60 -0.8 -80 -1 0 0.2 0.4 0.6 Frequency (Fs) 0.8 Figure 16 DAC Digital Filter Frequency Response – 192kHz w 1 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5 Figure 17 DAC Digital Filter Ripple – 192 kHz March 2006, PD Rev 4.0 26 WM8746 Production Data DIGITAL DE-EMPHASIS CHARACTERISTICS 0 1 0.5 -2 Response (dB) Response (dB) 0 -4 -6 -0.5 -1 -1.5 -2 -8 -2.5 -10 -3 0 2 4 6 8 10 Frequency (kHz) 12 14 16 Figure 18 De-Emphasis Frequency Response (32kHz) 0 2 4 6 8 10 Frequency (kHz) 12 14 16 Figure 19 De-Emphasis Error (32kHz) 0 0.4 0.3 -2 Response (dB) Response (dB) 0.2 -4 -6 0.1 0 -0.1 -0.2 -8 -0.3 -10 -0.4 0 5 10 Frequency (kHz) 15 20 Figure 20 De-Emphasis Frequency Response (44.1kHz) 0 5 10 Frequency (kHz) 15 20 Figure 21 De-Emphasis Error (44.1kHz) 0 1 0.8 -2 0.6 Response (dB) Response (dB) 0.4 -4 -6 0.2 0 -0.2 -0.4 -8 -0.6 -0.8 -10 -1 0 5 10 15 Frequency (kHz) 20 Figure 22 De-Emphasis Frequency Response (48kHz) w 0 5 10 15 Frequency (kHz) 20 Figure 23 De-Emphasis Error (48kHz) March 2006, PD Rev 4.0 27 WM8746 Production Data APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 24 External Components Diagram RECOMMENDED EXTERNAL COMPONENTS VALUES COMPONENT REFERENCE SUGGESTED VALUE DESCRIPTION De-coupling for DVDD and AVDD1. C1 and C5 10µF C2 to C4 0.1µF De-coupling for DVDD and AVDD1. C6 to C11 10µF Output AC coupling caps to remove midrail DC level from outputs. C12 0.1µF Reference de-coupling capacitors for CAP pin. C13 10µF C14 10µF Filtering for AVDD2. Omit if AVDD low noise. R1 33Ω Filtering for AVDD2. Use 0Ω if AVDD low noise. Table 15 External Components Description w March 2006, PD Rev 4.0 28 WM8746 Production Data DECOUPLING APPLICATIONS INFORMATION SUPPLY PINS DESCRIPTION PIN NAME TYPE 1 DVDD Supply Digital Positive Supply. DESCRIPTION 11 DGND Supply Digital GND 15 AVDD2 Supply Analogue Positive DAC Reference 16 CAP Analogue output 20 AGND1 Supply Analogue GND 24 AGND2 Supply Analogue GND 28 AVDD1 Supply Analogue VDD Analogue Internal Mid-Rail Reference De-Coupling Point DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Analogue supply current AVDD = 5V 58 Digital supply current DVDD = 5V 22 mA AVDD = 3.3V 57 mA DVDD = 3.3V 11 mA Analogue supply current Digital supply current mA For proper decoupling, 0.1µF surface-mount ceramic capacitors are recommended for AVDD1, AVDD2, DVDD and CAP. Also recommended are 10µF capacitors for AVDD, DVDD and CAP. These are a general guideline and are dependent on the amount of noise present in the system. If there is excessive noise on the supply, such as may be present in a commercial DVD receiver with motors and switching amplifiers, additional filtering will be required. The supply AVDD2 is the reference voltage for the DAC. It has no supply noise rejection, so any noise on this pin will affect the DAC outputs. There is not much current drawn on this supply pin. Supply AVDD1 does have supply rejection and draws most of the analogue supply current. DECOUPLING EXAMPLES Figure 25 Decoupling Example 1 In Figure 25, there is a single analogue supply that is fairly noisy. The AVDD1 and DVDD pins can tolerate this, but the AVDD2 needs additional filtering. The schematic illustrates a suitable solution. w March 2006, PD Rev 4.0 29 WM8746 Production Data It is important that the supply pins are connected correctly. If AVDD1 and AVDD2 pins had both been connected to the 10Ω resistor, the performance would be worse. The value of 10Ω is too high and will cause an increase in THD. This is because currents drawn by AVDD1 will affect the reference voltage on AVDD2. A full-scale output FFT plot will show increased harmonics, because the output current drawn modulates the reference voltage. 4.7µF ceramic capacitors are becoming available in 0805 package with Y5V dielectric. Whilst they do not have quite as good performance as 10µF, it is possible to use them instead. Their capacitance goes down significantly with supply voltage, but at 3.3V (VDD) and 1.65V (CAP pin), the drop is not too great, if a 10V-rated part is used. As they are already in a low-inductance package, the 0.1µF is no longer necessary. See Figure 26 for an example. Figure 26 Decoupling Example 2 RECOMMENDED ANALOGUE LOW-PASS FILTER (OPTIONAL) 4.7kΩ 4.7kΩ +VS _ 10u F + 51Ω 1.8kΩ 7.5KΩ + 1.0nF 680pF -VS 10kΩ Figure 27 Recommended Low Pass Filter (Optional) w March 2006, PD Rev 4.0 30 WM8746 Production Data PACKAGE DIMENSIONS DS: 28 PIN SSOP (10.2 x 5.3 x 1.75 mm) b DM007.E e 28 15 E1 1 D E GAUGE PLANE 14 c A A2 A1 Θ L 0.25 L1 -C0.10 C Symbols A A1 A2 b c D e E E1 L L1 θ MIN ----0.05 1.65 0.22 0.09 9.90 7.40 5.00 0.55 o 0 REF: Dimensions (mm) NOM --------1.75 0.30 ----10.20 0.65 BSC 7.80 5.30 0.75 1.25 REF o 4 SEATING PLANE MAX 2.0 0.25 1.85 0.38 0.25 10.50 8.20 5.60 0.95 o 8 JEDEC.95, MO-150 NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM. D. MEETS JEDEC.95 MO-150, VARIATION = AH. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. w March 2006, PD Rev 4.0 31 WM8746 Production Data IMPORTANT NOTICE Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM’s standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical components in life support devices or systems without the express written approval of an officer of the company. Life support devices or systems are devices or systems that are intended for surgical implant into the body, or support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be reasonably expected to result in a significant injury to the user. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of WM covering or relating to any combination, machine, or process in which such products or services might be or are used. WM’s publication of information regarding any third party’s products or services does not constitute WM’s approval, license, warranty or endorsement thereof. Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use. Resale of WM’s products or services with statements different from or beyond the parameters stated by WM for that product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use. ADDRESS: Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: [email protected] w March 2006, PD Rev 4.0 32