W3EG72128S-AD4 -BD4 White Electronic Designs PRELIMINARY* 1GB – 2x64Mx72 DDR SDRAM UNBUFFERED ECC w/PLL FEATURES DESCRIPTION Double-data-rate architecture DDR200, DDR266 and DDR333 Bi-directional data strobes (DQS) The W3EG72128S is a 2x64Mx72 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM components. This module consists of eighteen 64Mx8 bit DDR SDRAMs in 66 pin TSOP packages mounted on a 200 pin FR4 substrate. Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh Serial presence detect Dual Rank Power supply: 2.5V ± 0.20V JEDEC standard 200 pin SO-DIMM package Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. * This product is under development, is not qualified or characterized and is subject to change without notice. • Package height options: AD4: 35.5 mm (1.38") and BD4: 31.75 mm (1.25") NOTE: Consult factory for availability of: • RoHS compliant products • Vendor source control options • Industrial temperature option OPERATING FREQUENCIES August 2005 Rev. 3 DDR333 @CL=2.5 DDR266 @CL=2 DDR266 @CL=2.5 DDR200 @CL=2 Clock Speed 166MHz 133MHz 133MHz 100MHz CL-tRCD-tRP 2.5-3-3 2-2-2 2.5-3-3 2-2-2 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG72128S-AD4 -BD4 PRELIMINARY PIN CONFIGURATION PIN# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 SYMBOL PIN# VREF 51 VREF 52 53 VSS VSS 54 DQ0 55 DQ4 56 DQ1 57 DQ5 58 VCC 59 VCC 60 DQS0 61 DQM0 62 DQ2 63 DQ6 64 65 VSS VSS 66 DQ3 67 DQ7 68 DQ8 69 DQ12 70 VCC 71 72 VCC DQ9 73 DQ13 74 DQS1 75 DQM1 76 VSS 77 78 VSS DQ10 79 DQ14 80 DQ11 81 DQ15 82 83 VCC VCC 84 CK0 85 VCC 86 CK0# 87 VSS 88 VSS 89 VSS 90 DQ16 91 DQ20 92 DQ17 93 DQ21 94 VCC 95 VCC 96 DQS2 97 DQM2 98 DQ18 99 DQ22 100 August 2005 Rev. 3 SYMBOL PIN# VSS 101 VSS 102 DQ19 103 DQ23 104 DQ24 105 DQ28 106 VCC 107 VCC 108 DQ25 109 DQ29 110 DQS3 111 DQM3 112 VSS 113 VSS 114 DQ26 115 DQ30 116 DQ27 117 DQ31 118 VCC 119 VCC 120 CB0 121 CB4 122 CB1 123 CB5 124 VSS 125 VSS 126 DQS8 127 DQM8 128 NC 129 CB6 130 VCC 131 VCC 132 CB3 133 CB7 134 NC 135 NC 136 VSS 137 VSS 138 NC 139 VSS 140 NC 141 VCC 142 VCC 143 VCC 144 CKE1 145 CKE0 146 NC 147 NC 148 A12 149 A11 150 SYMBOL PIN# A9 151 A8 152 VSS 153 VSS 154 A7 155 A6 156 A5 157 A4 158 A3 159 A2 160 A1 161 A0 162 VCC 163 VCC 164 A10/AP 165 BA1 166 BA0 167 RAS# 168 WE# 169 CAS# 170 CS0# 171 CS1# 172 NC 173 NC 174 VSS 175 VSS 176 DQ32 177 DQ36 178 DQ33 179 DQ37 180 VCC 181 VCC 182 DQS4 183 DQM4 184 DQ34 185 DQ38 186 VSS 187 VSS 188 DQ35 189 DQ39 190 DQ40 191 DQ44 192 VCC 193 VCC 194 DQ41 195 DQ45 196 DQS5 197 DQM5 198 VSS 199 VSS 200 PIN NAMES A0-A12 BA0-BA1 DQ0-DQ63 DQS0-DQS8 CK0 CK0# CKE0, CKE1 CS0#, CS1# RAS# CAS# WE# DQM0-DQM8 VCC VSS VREF VCCSPD SYMBOL DQ42 DQ46 DQ43 DQ47 VCC VCC VCC NC VSS NC VSS VSS DQ48 DQ52 DQ49 DQ53 VCC VCC DQS6 DQM6 DQ50 DQ54 VSS VSS DQ51 DQ55 DQ56 DQ60 VCC VCC DQ57 DQ61 DQS7 DQM7 VSS VSS DQ58 DQ62 DQ59 DQ63 VCC VCC SDA SA0 SCL SA1 VCCSPD SA2 VCCID SDA SCL SA0-SA2 VCCID NC Address input (Multiplexed) Bank Select Address Data Input/Output Data Strobe Input/Output Clock Input Clock Input Clock Enable input Chip Select Input Row Address Strobe Column Address Strobe Write Enable Data-In Mask Power Supply (2.5V) Ground Power Supply for Reference Serial EEPROM Power Supply (2.3V to 3.6V) Serial data I/O Serial clock Address in EEPROM VCC Indentification Flag No Connect NC 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3EG72128S-AD4 -BD4 White Electronic Designs PRELIMINARY FUNCTIONAL BLOCK DIAGRAM CS1# CS0# DQS0 DQM0 DQS4 DQM4 CS# CS# DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# DQS DQS1 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQS5 DQM1 DQM5 CS# CS# DQS DQS2 DQS6 DQM2 DQM6 CS# CS# DQS DQS7 DQS3 DQM3 DQM7 CS# DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 CS# DQS DQS8 DQM8 CS# DQS VCC 120Ω CLK0/CLK0# CK0A CK0 CLK1/CLK1# PLL RAS# RAS: DDR SDRAMs CAS# CAS: DDR SDRAMs CLK2/CLK2# CLK3/CLK3# CK0A# CK0# FEEDBACK BA0-BA1 WE# A0-A12 BA0-BA1: DDR SDRAMs WE: DDR SDRAMs SERIAL PD A0-A12: DDR SDRAMs SCL CKE0 CKE0: DDR SDRAMs CKE1 CKE1: DDR SDRAMs SDA A0 A1 A2 SA0 SA1 SA2 VCC DDR SDRAM GND DDR SDRAM Note: All datalines are terminated through a 22 ohms series resistor. August 2005 Rev. 3 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3EG72128S-AD4 -BD4 White Electronic Designs PRELIMINARY ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Units Voltage on any pin relative to VSS VIN, VOUT -0.5 to 3.6 V Voltage on VCC supply relative to VSS VCC, VCCQ -1.0 to 3.6 V TSTG -55 to +150 °C Power Dissipation PD 9 W Short Circuit Current IOS 50 mA Storage Temperature Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC CHARACTERISTICS 0°C ≤ TA ≤ 70°C, VCC = 2.5V ± 0.2V Parameter Symbol Min Max Unit Supply Voltage VCC 2.3 2.7 V Supply Voltage VCCQ 2.3 2.7 V Reference Voltage VREF VCCQ/2 - 50mV VCCQ/2 + 50mV V Termination Voltage VTT VREF - 0.04 VREF + 0.04 V Input High Voltage VIH VREF + 0.15 VCCQ + 0.3 V Input Low Voltage VIL -0.3 VREF - 0.15 V Output High Voltage VOH VTT + 0.76 — V Output Low Voltage VOL — VTT - 0.76 V Symbol Max Unit CIN1 56 pF Input Capacitance (RAS#, CAS#, WE#) CIN2 56 pF Input Capacitance (CKE0) CIN3 29 pF CAPACITANCE TA = 25°C, f = 1MHz, VCC = 3.3V, VREF =1.4V ± 200mV Parameter Input Capacitance (A0-A12) Input Capacitance (CK0,CK0#) CIN4 5.5 pF Input Capacitance (CS0#) CIN5 29 pF Input Capacitance (DQM0-DQM8) CIN6 13 pF Input Capacitance (BA0-BA1) CIN7 56 pF Data input/output capacitance (DQ0-DQ63)(DQS) COUT 13 pF August 2005 Rev. 3 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3EG72128S-AD4 -BD4 White Electronic Designs PRELIMINARY IDD SPECIFICATIONS AND TEST CONDITIONS Recommended operating conditions, 0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V Parameter Symbol Conditions DDR333@CL=2.5 DDR266@CL=2 DDR266@CL=2.5 DDR200@CL=2 Max Max Max Max Units IDD0 One device bank; Active - Precharge; tRC=tRC(MIN); tCK=tCK(MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. 2620 2620 2620 2620 mA Operating Current IDD1 One device bank; Active-ReadPrecharge; Burst = 2; tRC=tRC(MIN) ;tCK=tCK(MIN); Iout = 0mA; Address and control inputs changing once per clock cycle. 2890 2890 2890 2890 mA Precharge PowerDown Standby Current IDD2P All device banks idle; Power- down mode; tCK=tCK(MIN); CKE=(low) 90 90 90 90 mA Idle Standby Current IDD2F CS# = High; All device banks idle; tCK=tCK(MIN); CKE = high; Address and other control inputs changing once per clock cycle. Vin = Vref for DQ, DQS and DM. 1085 1085 1085 1085 mA Active Power-Down Standby Current IDD3P One device bank active; Power-down mode; tCK(MIN); CKE=(low) 630 630 630 630 mA IDD3N CS# = High; CKE = High; One device bank; Active-Precharge; tRC=tRAS(MAX); tCK=tCK(MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. 1175 1175 1175 1175 mA IDD4R Burst = 2; Reads; Continous burst; One device bank active;Address and control inputs changing once per clock cycle; tCK=tCK(MIN); Iout = 0mA. 2935 2935 2935 2935 mA IDD4W Burst = 2; Writes; Continous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK=tCK(MIN); DQ,DM and DQS inputs changing twice per clock cycle. 3025 2845 2845 2845 mA Auto Refresh Current IDD5 tRC=tRC(MIN) 4060 4060 4060 4060 mA Self Refresh Current IDD6 CKE ≤ 0.2V 360 365 365 365 mA IDD7A Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK(MIN); Address and control inputs change only during Active Read or Write commands. 5095 5050 5050 5050 mA Operating Current Active Standby Current Operating Current Operating Current Operating Current August 2005 Rev. 3 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG72128S-AD4 -BD4 PRELIMINARY DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A IDD1 : OPERATING CURRENT : ONE BANK IDD7A : OPERATING CURRENT : FOUR BANKS 1. Typical Case : VCC=2.5V, T=25°C 1. Typical Case : VCC=2.5V, T=25°C 2. Worst Case : VCC=2.7V, T=10°C 2. Worst Case : VCC=2.7V, T=10°C 3. Only one bank is accessed with tRC (min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. IOUT = 0mA 3. Four banks are being interleaved with tRC (min), Burst Mode, Address and Control inputs on NOP edge are not changing. Iout=0mA 4. Timing Patterns : 4. Timing Patterns : • DDR200 (100 MHz, CL=2) : tCK=10ns, CL2, BL=4, tRCD=2*tCK, tRAS=5*tCK Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst • DDR266 (133MHz, CL=2.5) : tCK=7.5ns, CL=2.5, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst • DDR266 (133MHz, CL=2) : tCK=7.5ns, CL=2, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst • DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4, tRCD=10*tCK, tRAS=7*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst • DDR200 (100 MHz, CL=2) : tCK=10ns, CL2, BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst • DDR266 (133MHz, CL=2.5) : tCK=7.5ns, CL=2.5, BL=4, tRRD=3*tCK, tRCD=3*tCK Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst • DDR266 (133MHz, CL=2) : tCK=7.5ns, CL2=2, BL=4, tRRD=2*tCK, tRCD=2*tCK Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst • DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4, tRRD=3*tCK, tRCD=3*tCK, Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst Legend : A = Activate, R = Read, W = Write, P = Precharge, N = NOP A (0-3) = Activate Bank 0-3 R (0-3) = Read Bank 0-3 August 2005 Rev. 3 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3EG72128S-AD4 -BD4 White Electronic Designs PRELIMINARY DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS AC CHARACTERISTICS 335 PARAMETER 262 265/202 SYMBOL MIN MAX MIN MAX MIN MAX UNITS Access window of DQs from CK/CK# tAC -0.70 +0.70 -0.75 +0.75 -0.75 0.75 ns CK high-level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK CK low-level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK 26 CL = 2.5 tCK (2.5) 6 13 7.5 13 7.5 13 ns 39, 44 CL = 2 tCK (2) 7.5 13 7.5 13 7.5/10 13 ns 39, 44 tDH 0.45 ns 23, 27 DQ and DM input setup time relative to DQS tDS 0.45 0.5 0.5 ns 23, 27 DQ and DM input pulse width (for each input) tDIPW 1.75 1.75 1.75 ns 27 Access window of DQS from CK/CK# tDQSCK -0.60 DQS input high pulse width tDQSH 0.35 tDQSL 0.35 Clock cycle time DQ and DM input hold time relative to DQS DQS input low pulse width DQS-DQ skew, DQS to last DQ valid, per group, per access 0.5 +0.60 0.5 -0.75 +0.75 0.35 +0.75 0.35 0.35 tDQSQ -0.75 26 ns tCK 0.35 0.4 NOTES tCK 0.5 0.5 ns 1.25 tCK 22, 23 Write command to first DQS latching transition tDQSS 0.75 DQS falling edge to CK rising - setup time tDSS 0.20 DQS falling edge from CK rising - hold time tDSH 0.20 Half clock period tHP Data-out high-impedance window from CK/CK# tHZ ns 16, 36 Data-out low-impedance window from CK/CK# tLZ -0.70 -0.75 -0.75 ns 16, 36 Address and control input hold time (fast slew rate) tIHF 0.75 0.90 0.90 ns 12 Address and control input setup time (fast slew rate) tISF 0.75 0.90 0.90 ns 12 Address and control input hold time (slow slew rate) tIHS 0.8 1 1 ns 12 August 2005 Rev. 3 1.25 0.75 1.25 0.20 0.2 0.20 tCH,tCL tCK 0.2 tCH,tCL +0.70 7 0.75 tCK tCH, tCL +0.75 +0.75 ns 30 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3EG72128S-AD4 -BD4 White Electronic Designs PRELIMINARY DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued) AC CHARACTERISTICS PARAMETER 335 262 SYMBOL MIN UNITS NOTES tISS 0.8 1 1 ns 12 Address and Control input pulse width (for each input) tIPW 2.2 2.2 2.2 ns LOAD MODE REGISTER command cycle time tMRD 12 15 15 ns DQ-DQS hold, DQS to first DQ to go non-valid, per access tQH tHP - tQHS tHP - tQHS tHP - tQHS ns Data hold skew factor tQHS ACTIVE to PRECHARGE command tRAS 42 ACTIVE to READ with Auto precharge command tRAP 15 15 20 ns ACTIVE to ACTIVE/AUTO REFRESH command period tRC 60 60 65 ns AUTO REFRESH command period tRFC 72 75 78 ns ACTIVE to READ or WRITE delay tRCD 15 15 20 ns Address and control input setup time (slow slew rate) PRECHARGE command period MAX MIN 265/202 0.50 70,000 MAX MIN 0.75 40 120,000 40 MAX 0.75 ns 120,000 ns 22, 23 30, 47 42 tRP 15 DQS read preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK 37 DQS read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK 37 ACTIVE bank a to ACTIVE bank b command tRRD 12 15 15 ns DQS write preamble tWPRE 0.25 0.25 0.25 tCK DQS write preamble setup time tWPRES 0 DQS write postamble tWPST 0.4 Write recovery time tWR 15 15 15 ns Internal WRITE to READ command delay tWTR 1 1 1 tCK Data valid output window 15 0 0.6 ns 0 0.4 tQH -tDQSQ NA 20 0.6 tQH -tDQSQ 0.4 0.6 tQH - tDQSQ ns 18, 19 tCK 17 ns 22 70.3 µs 21 7.8 µs 21 REFRESH to REFRESH command interval tREFC Average periodic refresh interval tREFI Terminating voltage delay to VCC tVTD Exit SELF REFRESH to non-READ command tXSNR 75 75 75 ns Exit SELF REFRESH to READ command tXSRD 200 200 200 tCK August 2005 Rev. 3 70.3 70.3 7.8 0 8 7.8 0 0 ns White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG72128S-AD4 -BD4 PRELIMINARY Notes 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load: 16. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ). 17. The intent of the Don’t Care state after completion of the postamble is the DQSdriven signal should either be high, low, or high-Z and that any signal transition within the input switching region must follow valid input requirements. That is, if DQS transitions high (above VIH DC (MIN) then it must not transition low (below VIH DC) prior to tDQSH (MIN). 18. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 19. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. 20. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the minimum absolute Value for the respective parameter. tRAS (MAX) for IDD measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS. 21. The refresh period 64ms. This equates to an aver-age refresh rate of 7.8125µs. However, an AUTO REFRESH command must be asserted at least once every 70.3µs; burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. 22. The valid data window is derived by achieving other specifications: tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly porportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55, beyon which functionality is uncertain. Figure 7, Derating Data Valid Window, shows derating curves for duty cycles ranging between 50/50 and 45/55. 23. Each byte lane has a corresponding DQS. 24. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during standby). 25. To maintain a valid level, the transitioning edge of the input must: a. Sustain a constant slew rate from the current AC level through to the target AC level, VIL(AC) or VIH(AC).Reach at least the target AC level. b. After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC). 26. JEDEC specifies CK and CK# input slew rate must be ≥ 1V/ns (2V/ns differentially). 27. DQ and DM input slew rates must not deviate from DQS by more than 10 percent. If the DQ/ DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100mv/ns reduction in slew rate. If slew rate exceeds 4V/ns, functionality is uncertain. For 335, slew rates must be ≥ 0.5 V/ns. 28. VCC must not vary more than 4 percent if CKE is not active while any bank is active. 29. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary by the same amount. tHP min is the lesser of tCL minimum and tCH minimum actually applied to the device CK and CK# inputs, collectively during bank active. 30. READs and WRITEs with auto precharge are not allowed to be issued until tRAS(MIN) can be satisfied prior to the internal precharge command being issued. 31. Any positive glitch must be less than 1/3 of the clock and not more than +400mV or 2.9V, whichever is less. Any negative glitch must be less than 1/3 of the clock cycle and not exceed either -300mV or 2.2V, whichever is more positive. VTT Output (VOUT) 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 50Ω Reference Point 30pF AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The mini-mum slew rate for the input signals used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC). The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). VREF is expected to equal VCCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (non-common mode) on VREF may not exceed ±2 percent of the DC value. Thus, from VCCQ/2, VREF is allowed ±25mV for DC error and an additional ±25mV for AC noise. This measurement is to be taken at the nearest VREF bypass capacitor. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. IDD is dependent on output loading and cycle rates. Specified values are obtained with mini-mum cycle time at CL = 2 for 262, and 263, CL = 2.5 for 335 and 265 with the outputs open. Enables on-chip refresh and address counters. IDD specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate. This parameter is sampled. VCC = +2.5V ±0.2V, VCCQ = +2.5V ±0.2V, VREF = VSS, f = 100 MHz, TA = 25°C, VOUT(DC) = VCCQ/2, VOUT (peak to peak) = 0.2V. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading. For slew rates < 1 V/ns and ≥ to 0.5 Vns. If the slew rate is < 0.5V/ns, timing must be derated: tIS has an additional 50ps per each 100 mV/ns reduction in slew rate from 500mV/ns, while tIH is unaffected. If the slew rate exceeds 4.5 V/ns, functionality is uncertain. For 335, slew rates must be 0.5 V/ns. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK# is VREF. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE < 0.3 x VCCQ is recognized as LOW. The output timing reference level, as measured at the timing reference point indicated in Note 3, is VTT. August 2005 Rev. 3 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG72128S-AD4 -BD4 PRELIMINARY 37. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). 38. During Initialization, VCCQ, VTT, and VREF must be equal to or less than VCC + 0.3V. Alternatively, VTT may be 1.35V maximum during power up, even if VCC/VCCQ are 0.0V, provided a minimum of 42 0 of series resistance is used between the VTT supply and the input pin. 39. The current part operates below the slowest JEDEC operating frequency of 83 MHz. As such, future die may not reflect this option. 40. Random addressing changing and 50 percent of data changing at every transfer. 41. Random addressing changing and 100 percent of data changing at every transfer. 42. CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until tREF later. 43. IDD2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level. IDD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs to remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is “worst case.” 44. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles. 45. Leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes. 46. When an input signal is HIGH or LOW, it is defined as a steady state logic HIGH or LOW. 47. The 335 speed grade will operate with tRAS (MIN) = 40ns and tRAS (MAX) = 120,000ns at any slower frequency. 32. Normal Output Drive Curves: a. The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 8, Pull-Down Characteristics. b. The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 8, Pull-Down Characteristics. c. The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 9, Pull-Up Characteristics. d. The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 9, Pull-Up Characteristics. e. The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between 0.71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0V, and at the same voltage and temperature. f. The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10 percent, for device drain-to-source volt-ages from 0.1V to 1.0V. 33. The voltage levels used are derived from a mini-mum VCC level and the referenced test load. In practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values. 34. VIH overshoot: VIH (MAX) = VCCQ + 1.5V for a pulse width !5 3ns and the pulse width can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) = -1.5V for a pulse width !5 3ns and the pulse width can not be greater than 1/3 of the cycle rate. 35. VCC and VCCQ must track each other. 36. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will prevail over tDQSCK (MIN) + tRPRE (MAX) condition. August 2005 Rev. 3 10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3EG72128S-AD4 -BD4 White Electronic Designs PRELIMINARY ORDERING INFORMATION FOR BD4 Part Number Speed CAS Latency tRCD tRP Height* W3EG72128S335BD4-xG 166MHz/333Mb/s 2.5 3 3 31.75 (1.25") W3EG72128S262BD4-xG 133MHz/266Mb/s 2 2 2 31.75 (1.25") W3EG72128S265BD4-xG 133MHz/266Mb/s 2.5 3 3 31.75 (1.25") W3EG72128S202BD4-xG 100MHz/200Mb/s 2 2 2 31.75 (1.25") NOTES: • Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant) • Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “-x” in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) • Consult factory for availability of industrial temperature (-40°C to 85°C) option PACKAGE DIMENSIONS FOR BD4 6.35 (0.250) MAX. 67.56 (2.666) MAX 3.98 ± 0.1 (0.157 ± 0.004) 31.75 (1.25) 20 (0.787) 2.31 (0.091) REF. 4.19 (0.165) 11.40 (0.449) 1.80 (0.071) 3.99 (0.157) MIN. 47.40 (1.866) 0.99 ± 0.10 (0.039 ± 0.004) * ALL DIMENSIONS ARE IN MILIMETERS AND (INCHES) August 2005 Rev. 3 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3EG72128S-AD4 -BD4 White Electronic Designs PRELIMINARY ORDERING INFORMATION FOR AD4 Part Number Speed CAS Latency tRCD tRP Height* W3EG72128S335AD4-xG 166MHz/333Mb/s 2.5 3 3 35.05 (1.138") W3EG72128S262AD4-xG 133MHz/266Mb/s 2 2 2 35.05 (1.138") W3EG72128S265AD4-xG 133MHz/266Mb/s 2.5 3 3 35.05 (1.138") W3EG72128S202AD4-xG 100MHz/200Mb/s 2 2 2 35.05 (1.138") NOTES: • Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant) • Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “-x” in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) • Consult factory for availability of industrial temperature (-40°C to 85°C) option PACKAGE DIMENSIONS FOR AD4 67.56 (2.666) MAX. 6.35 (0.250) MAX. 2.0 (0.079) 35.05 (1.138) MAX. 3.98 ± 0.1 (0.157 ± 0.004) 20 (0.787) P1 2.31 (0.091) REF. 4.19 (0.165) 1.80 (0.071) 3.99 (0.157) MIN. 47.40 (1.866) 0.99 ± 0.10 (0.039 ± 0.004) 11.40 (0.449) * ALL DIMENSIONS ARE IN MILIMETERS AND (INCHES) August 2005 Rev. 3 12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG72128S-AD4 -BD4 PRELIMINARY PART NUMBERING GUIDE W 3 E G 72 128 S xxx D4 x -x G WEDC MEMORY DDR GOLD BUS WIDTH DEPTH 2.5V SPEED (MHz) PACKAGE 200 PIN I = INDUSTRIAL COMPONENT VENDOR NAME (M = Micron) (S = Samsung) G = RoHS COMPLIANT August 2005 Rev. 3 13 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3EG72128S-AD4 -BD4 White Electronic Designs PRELIMINARY Document Title 1GB – 2x64Mx72 DDR SDRAM UNBUFFERED ECC w/PLL Revision History Rev # History Release Date Status Rev 0 Created 7-23-03 Advanced Rev 1 Added AD4 and BD4 package height option 4-6-04 Preliminary Rev 2 Added AC specs 10-4-04 Preliminary Rev 3 3.1 Added part number matrix 8-05 Preliminary August 2005 Rev. 3 14 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com