CY62137FV30 MoBL® 2-Mbit (128K x 16) Static RAM is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption by 90% when addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99% when deselected (CE HIGH or both BLE and BHE are HIGH). The input and output pins (IO0 through IO15) are placed in a high impedance state in the following conditions: Features ■ Very high speed: 45 ns Temperature ranges ❐ Industrial: –40°C to +85°C ❐ Automotive-A: –40°C to +85°C ❐ Automotive-E: –40°C to +125°C ■ Wide voltage range: 2.20V–3.60V ■ ■ Pin compatible with CY62137CV/CV25/CV30/CV33, CY62137V, and CY62137EV30 Ultra low standby power ❐ Typical standby current: 1 µA ❐ Maximum standby current: 5 µA (Industrial) ■ Ultra low active power ❐ Typical active current: 1.6 mA at f = 1 MHz (45 ns speed) ■ Easy memory expansion with CE and OE features ■ Deselected (CE HIGH) ■ Outputs are disabled (OE HIGH) ■ Both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH) ■ Write operation is active (CE LOW and WE LOW) ■ ■ Automatic power down when deselected ■ CMOS for optimum speed and power ■ Byte power down feature ■ Available in Pb-free 48-Ball VFBGA and 44-pin TSOP II package Write to the device by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0 through IO7) is written into the location specified on the address pins (A0 through A16). If Byte High Enable (BHE) is LOW, then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A16). Read from the device by taking Chip Enable (CE) and Output Enable (OE) LOW, while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from memory appears on IO8 to IO15. See the “Truth Table” on page 9 for a complete description of read and write modes. Functional Description The CY62137FV30 is a high performance CMOS static RAM organized as 128K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines. Logic Block Diagram SENSE AMPS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS 128K x 16 RAM Array Cypress Semiconductor Corporation Document Number: 001-07141 Rev. *E • A16 A15 A14 A13 A11 A12 CE BHE BLE 198 Champion Court IO8–IO15 BHE WE CE OE BLE COLUMN DECODER POWER DOWN CIRCUIT IO0–IO7 • San Jose, CA 95134-1709 • 408-943-2600 Revised August 03, 2007 CY62137FV30 MoBL® Product Portfolio Power Dissipation Product VCC Range (V) Range CY62137FV30LL Min Typ  Max Ind’l/Auto-A 2.2V 3.0V 3.6V Auto-E 2.2V 3.0V 3.6V Speed (ns) Operating ICC (mA) f = 1MHz Standby ISB2 (µA) f = fmax Typ  Max Typ  Max Typ  Max 45 1.6 2.5 13 18 1 5 55 2 3 15 25 1 20 Pin Configuration Figure 1. 48-Ball VFBGA Pinout [2, 3] Figure 2. 44-Pin TSOP II  1 2 3 4 5 6 BLE OE A0 A1 A2 NC A IO8 BHE A3 A4 CE IO0 B IO9 IO10 A5 A6 IO1 IO2 C VSS IO11 NC A7 IO3 VCC D VCC IO12 NC A16 IO4 VSS E IO14 IO13 A14 A15 IO5 IO6 F IO15 NC A12 A13 WE IO7 G NC A8 A9 A10 A11 NC H A4 A3 A2 A1 A0 CE IO0 IO1 IO2 IO3 VCC VSS IO4 IO5 IO6 IO7 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE IO15 IO14 IO13 IO12 VSS VCC IO11 IO10 IO9 IO8 NC A8 A9 A10 A11 NC Notes 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C. 2. NC pins are not connected on the die. 3. Pins D3, H1, G2, and H6 in the VFBGA package are address expansion pins for 4 Mb, 8 Mb, 16 Mb, and 32 Mb, respectively. Document Number: 001-07141 Rev. *E Page 2 of 12 CY62137FV30 MoBL® DC Input Voltage [4, 5] .......................................–0.3V to 3.9V Maximum Ratings Output Current into Outputs (LOW) ............................ 20 mA Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Static Discharge Voltage ......................................... > 2001V (MIL–STD–883, Method 3015) Storage Temperature ................................ –65°C to + 150°C Latch up Current .................................................... > 200 mA Ambient Temperature with Power Applied .......................................... –55°C to + 125°C Operating Range Supply Voltage to Ground Potential ...........................................................-0.3V to 3.9V Device DC Voltage Applied to Outputs in High Z state [4, 5] ............................................-0.3V to 3.9V Ambient Temperature Range VCC  CY62137FV30LL Ind’l/Auto-A –40°C to +85°C 2.2V to 3.6V Auto-E –40°C to +125°C Electrical Characteristics Over the Operating Range Parameter Description Output HIGH Voltage VOH Output LOW Voltage VOL Input HIGH Voltage VIH Input LOW Voltage VIL Test Conditions 45 ns (Ind’l/Auto-A) Min Typ Max 55 ns (Auto-E) Min Typ Max Unit 2.2 < VCC < 2.7 IOH = –0.1 mA 2.0 2.0 V 2.7 < VCC < 3.6 IOH = –1.0 mA 2.4 2.4 V 2.2 < VCC < 2.7 IOL = 0.1 mA 0.4 0.4 V 2.7 < VCC < 3.6 IOL = 2.1mA 0.4 0.4 V 2.2 < VCC < 2.7 1.8 VCC + 0.3 1.8 VCC + 0.3 V 2.7 < VCC < 3.6 2.2 VCC + 0.3 2.2 VCC + 0.3 V 2.2 < VCC < 2.7 –0.3 0.6 –0.3 0.6 V 2.7 < VCC < 3.6 –0.3 0.8 –0.3 0.8 V IIX Input Leakage Current GND < VI < VCC –1 +1 –4 +4 µA IOZ Output Leakage Current GND < VO < VCC, Output disabled –1 +1 –4 +4 µA ICC VCC Operating Supply Current f = fmax = 1/tRC mA f = 1 MHz VCC = VCC(max) IOUT = 0 mA CMOS levels CE > VCC – 0.2V, Automatic CE Power Down Current – CMOS VIN > VCC – 0.2V, VIN < 0.2V Inputs f = fmax (address and data only), ISB1 13 18 15 25 1.6 2.5 2 3 1 5 1 20 µA 1 5 1 20 µA f = 0 (OE, WE, BHE, and BLE), VCC = 3.60V ISB2  CE > VCC – 0.2V, Automatic CE Power Down Current – CMOS VIN > VCC – 0.2V or VIN < 0.2V, Inputs f = 0, VCC = 3.60V Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = VCC(typ) Max Unit 10 pF 10 pF Notes 4. VIL(min) = –2.0V for pulse durations less than 20 ns. 5. VIH(max)=VCC+0.75V for pulse durations less than 20 ns. 6. Full device AC operation assumes a minimum of 100 µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization. 7. Only chip enable (CE) and byte enables (BHE and BLE) are tied to CMOS levels to meet the ISB2 / ICCDR specification. Other inputs can be left floating. Document Number: 001-07141 Rev. *E Page 3 of 12 CY62137FV30 MoBL® Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions VFBGA TSOP II Unit Still air, soldered on a 3 × 4.5 inch, two layer printed circuit board 75 77 °C/W 10 13 °C/W AC Test Loads and Waveforms Figure 3. AC Test Loads and Waveform R1 VCC OUTPUT VCC 30 pF 10% GND Rise Time = 1 V/ns R2 INCLUDING JIG AND SCOPE ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT V Parameters 2.5V (2.2V to 2.7V) 3.0V (2.7V to 3.6V) Unit R1 16667 1103 Ω 1554 Ω R2 15385 RTH 8000 645 Ω VTH 1.20 1.75 V Data Retention Characteristics Over the Operating Range Parameter VDR tR  Conditions VCC for Data Retention ICCDR tCDR Description   VCC = 1.5V, CE > VCC - 0.2V, Ind’l/Auto-A VIN > VCC - 0.2V or VIN < 0.2V Auto-E Chip Deselect to Data Retention Time Operation Recovery Time VCC CE or Typ  Max 1.5 Data Retention Current Data Retention Waveform Min Unit V µA 4 12 0 ns tRC ns Figure 4. Data Retention Waveform  VCC(min) tCDR DATA RETENTION MODE VDR > 1.5V VCC(min) tR BHE.BLE Notes 8. Tested initially and after any design or process changes that may affect these parameters. 9. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs. 10. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE. Document Number: 001-07141 Rev. *E Page 4 of 12 CY62137FV30 MoBL® Switching Characteristics Over the Operating Range [11, 12] Parameter Description 45 ns (Ind’l/Auto-A) Min Max 55 ns (Auto-E) Min Max Unit Read Cycle tRC Read Cycle Time 45 tAA Address to Data Valid tOHA Data Hold From Address Change tACE CE LOW to Data Valid 45 55 ns tDOE OE LOW to Data Valid 22 25 ns tLZOE OE LOW to Low Z  tHZOE OE HIGH to High Z [13, 14]  55 45 10 ns 55 10 5 ns 5 18 10 ns ns 20 10 ns ns tLZCE CE LOW to Low Z tHZCE CE HIGH to High Z [13, 14] tPU CE LOW to Power Up tPD CE HIGH to Power Down 45 55 ns tDBE BLE/BHE LOW to Data Valid 45 55 ns tLZBE BLE/BHE LOW to Low Z [13, 15] tHZBE BLE/BHE HIGH to High Z [13, 14] 18 0 20 0 5 ns 10 18 ns ns 20 ns Write Cycle  tWC Write Cycle Time 45 55 ns tSCE CE LOW to Write End 35 40 ns tAW Address Setup to Write End 35 40 ns tHA Address Hold from Write End 0 0 ns tSA Address Setup to Write Start 0 0 ns tPWE WE Pulse Width 35 40 ns tBW BLE/BHE LOW to Write End 35 40 ns tSD Data Setup to Write End 25 25 ns tHD Data Hold From Write End 0 0 ns tHZWE WE LOW to High Z [13, 14] tLZWE WE HIGH to Low Z  18 10 20 10 ns ns Notes 11. Test conditions for all parameters, other than tri-state parameters, assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in “AC Test Loads and Waveforms” on page 4. 12. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. Please see application note AN13842 for further clarification. 13. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 14. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 15. If both byte enables are toggled together, this value is 10 ns. 16. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals are ACTIVE to initiate a write and any of these signals terminate a write by going INACTIVE. The data input setup and hold timing are referenced to the edge of the signal that terminates the write. Document Number: 001-07141 Rev. *E Page 5 of 12 CY62137FV30 MoBL® Switching Waveforms Figure 5. Read Cycle 1: Address Transition Controlled [17, 18] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 6. Read Cycle 2: OE Controlled [18, 19] ADDRESS tRC CE tPD tHZCE tACE OE tHZOE tDOE tLZOE BHE/BLE tHZBE tDBE tLZBE DATA OUT HIGHIMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE tPU VCC SUPPLY CURRENT 50% 50% ICC ISB Notes 17. The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL. 18. WE is HIGH for read cycle. 19. Address valid before or similar to CE and BHE, BLE transition LOW. Document Number: 001-07141 Rev. *E Page 6 of 12 CY62137FV30 MoBL® Switching Waveforms (continued) Figure 7. Write Cycle 1: WE Controlled [16, 20, 21] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE/BLE OE DATA IO tSD NOTE 22 tHD DATAIN tHZOE Figure 8. Write Cycle 2: CE Controlled [16, 20, 21] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tBW BHE/BLE OE tSD DATA IO tHD DATAIN NOTE 22 tHZOE Notes 20. Data IO is high impedance if OE = VIH. 21. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state. 22. During this period, the IOs are in output state. Do not apply input signals. Document Number: 001-07141 Rev. *E Page 7 of 12 CY62137FV30 MoBL® Switching Waveforms (continued) Figure 9. Write Cycle 3: WE Controlled, OE LOW  tWC ADDRESS tSCE CE tBW BHE/BLE tAW tHA tSA WE tPWE tSD DATA IO NOTE 22 tHD DATAIN tLZWE tHZWE Figure 10. Write Cycle 4: BHE/BLE Controlled, OE LOW  tWC ADDRESS CE tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tHZWE DATA IO NOTE 22 tSD tHD DATAIN tLZWE Document Number: 001-07141 Rev. *E Page 8 of 12 CY62137FV30 MoBL® Truth Table CE WE OE BHE BLE Inputs or Outputs H X X X X High Z Deselect or Power Down Standby (ISB) X X X H H High Z Deselect or Power Down Standby (ISB) L H L L L Data Out (IO0–IO15) Read Active (ICC) L H L H L Data Out (IO0–IO7); IO8–IO15 in High Z Read Active (ICC) L H L L H Data Out (IO8–IO15); IO0–IO7 in High Z Read Active (ICC) L H H L L High Z Output Disabled Active (ICC) L H H H L High Z Output Disabled Active (ICC) L H H L H High Z Output Disabled Active (ICC) L L X L L Data In (IO0–IO15) Write Active (ICC) L L X H L Data In (IO0–IO7); IO8–IO15 in High Z Write Active (ICC) L L X L H Data In (IO8–IO15); IO0–IO7 in High Z Write Active (ICC) Document Number: 001-07141 Rev. *E Mode Power Page 9 of 12 CY62137FV30 MoBL® Ordering Information Speed (ns) 45 Package Diagram Ordering Code CY62137FV30LL-45BVXI Operating Range Package Type 51-85150 48-Ball VFBGA (Pb-free) Industrial CY62137FV30LL-45ZSXI 51-85087 44-Pin TSOP II (Pb-free) 45 CY62137FV30LL-45ZSXA 51-85087 44-Pin TSOP II (Pb-free) Automotive-A 55 CY62137FV30LL-55ZSXE 51-85087 44-Pin TSOP II (Pb-free) Automotive-E Contact your local Cypress sales representative for availability of these parts. Package Diagram Figure 11. 48-Ball VFBGA (6 x 8 x 1 mm) BOTTOM VIEW TOP VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 2 3 4 5 6 6 5 4 3 2 1 C C E F G D E 2.625 D 0.75 A B 5.25 A B 8.00±0.10 8.00±0.10 1 F G H H A 1.875 A B 0.75 6.00±0.10 3.75 0.55 MAX. 6.00±0.10 0.10 C 0.21±0.05 0.25 C B 0.15(4X) Document Number: 001-07141 Rev. *E 1.00 MAX 0.26 MAX. SEATING PLANE C 51-85150-*D Page 10 of 12 CY62137FV30 MoBL® Package Diagram (continued) Figure 12. 44-Pin TSOP II 51-85087-*A Document Number: 001-07141 Rev. *E Page 11 of 12 CY62137FV30 MoBL® Document History Page Document Title: CY62137FV30 MoBL® 2-Mbit (128K x 16) Static RAM Document Number: 001-07141 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 449438 See ECN NXR New datasheet *A 464509 See ECN NXR Changed the ISB2(typ) value from 1.0 µA to 0.5 µA Changed the ISB2(max) value from 4 µA to 2.5 µA Changed the ICC(typ) value from 2 mA to 1.6 mA and ICC(max) value from 2.5 mA to 2.25 mA for f=1 MHz test condition Changed the ICC(typ) value from 15 mA to 13 mA and ICC(max) value from 20 mA to 18 mA for f=1 MHz test condition Changed the ICCDR(typ) value from 0.7 µA to 0.5 µA and ICCDR(max) value from 3 µA to 2.5 µA *B 566724 See ECN NXR Converted from preliminary to final Changed the ICC(max) value from 2.25 mA to 2.5 mA for test condition f=1 MHz Changed the ISB2(typ) value from 0.5 µA to 1 µA Changed the ISB2(max) value from 2.5 µA to 5 µA Changed the ICCDR(typ) value from 0.5 µA to 1 µA and ICCDR(max) value from 2.5 µA to 4 µA *C 869500 See ECN VKN Added Automotive-A and Automotive-E information Updated Ordering Information Table Added footnote 13 related to tACE *D 901800 See ECN VKN Added footnote 9 related to ISB2 and ICCDR Made footnote 14 applicable to AC parameters from tACE *E 1371124 See ECN VKN/AESA Converted Automotive information from preliminary to final Changed IIX min spec from –1 µA to –4 µA and IIX max spec from +1 µA to +4 µA Changed IOZ min spec from –1 µA to –4 µA and IOZ max spec from +1 µA to +4 µA © Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 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Document Number: 001-07141 Rev. *E Revised August 03, 2007 Page 12 of 12 MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.