10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 AIN0/STOP5/P60 AIN1/P61 AIN2/P62 AIN3/INT0/P63 AIN4/STOP2/P64 AIN5/STOP3/P65 AIN6/STOP4/P66 AIN7/P67 (RXD)RXD0/SEG39/P00 (TXD)TXD0/SEG38/P01 INT1/SEG37/P02 INT2/SEG36/P03 INT3/SEG35/P04 9 STOP/INT5/P20 AVDD VAREF 8 6 XTIN/P21 (RESET)RESET 5 (VDD)VDD 7 3 4 XTOUT/P22 2 1 (XIN)XIN (VSS)VSS C1 V1 V2 V3 SI1/P40 SO1/P41 SCK1/P42 TXD1/P43 DVO/P30 PWM3/PDO3/TC3/P31 PWM4/PDO4/PPG4/TC4/P32 EMG/P33 TC7/P34 PPG1/P35 PPG2/P36 RXD1/P37 (XOUT)XOUT (TEST)TEST 86FS27-3 P70/SEG15 P57/SEG16 P56/SEG17 P55/SEG18 42 41 P76/SEG9 50 P71/SEG14 P77/SEG8 51 43 SEG7 52 P72/SEG13 SEG6 53 44 SEG4 SEG5 55 54 45 SEG3 56 46 SEG2 57 P75/SEG10 SEG1 58 P73/SEG12 SEG0 59 P74/SEG11 COM0 60 47 COM2 COM1 62 61 48 COM3 63 49 C0 64 TMP86FS27 Pin Assignments (Top view) 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 P54/SEG19 P53/SEG20 P52/SEG21 P51/SEG22 P50/SEG23 P17/SEG24 P16/SEG25 P15/SEG26 P14/SEG27 P13/SEG28 P12/SEG29 P11/SEG30 P10/SEG31 P07/SEG32/SCK0 P06/SEG33/SO0 P05/SEG34/SI0 2007-08-07 TMP86FS27 Block Diagram I/O port (Segment output) Power supply Common outputs Segment outputs COM0 to COM3 SEG0 to SEG7 P77(SEG8) to P70(SEG15) P57(SEG16) to P50(SEG23) P17(SEG24) to P10(SEG31) P07(SEG32) to P00(SEG39) P7 P5 P1 P0 VDD LCD driver circuit VSS C0 Address/data bus C1 LCD power supply V1 LCD voltage booster circuit V2 V3 Program memory (EEPROM) TLCS-870/C CPU EEPROM I/F RESET TEST System control circuit Timing generator Resonator XIN connecting pins XOUT Data memory (RAM) Interrupt controller Standby control circuit Reset input TEST pin Boot program (ROM) High frequency Low frequency Clock generator P2 P22 to P20 Time base timer 10-bit timer/counter Watchdog timer TC7 P3 P37 to P30 I/O ports 86FS27-4 8-bit timer/counter TC3 P6 UART/SIO UART TC4 SIO 10-bit AD converter P67 to P60 AVDD (AIN7 to AIN0) VAREF AD Analog converter reference power pin supply P4 P43 to P40 I/O ports 2007-08-07 TMP86FS27 Pin Function The TMP86FS27 has MCU mode and serial PROM mode. (1) MCU mode In the MCU mode, the TMP86FS27 is a pin compatible with the TMP86CM27/P27 (Make sure to fix the TEST pin to low level). (2) Serial PROM mode The serial PROM mode is set by fixing TEST pin, P00 and P01 at “high” respectively when RESET pin is fixed “low”. After release of reset, the built-in BOOT ROM program is activated and the built-in flash memory is rewritten by serial I/F (UART). Pin Name (Serial PROM mode) Input/ Output Functions BOOT1/RXD Input/Input Fix “High” during reset. This pin is used as RXD pin after releasing reset. P00 BOOT2/TXD Input/Output Fix “High” during reset. This pin is used as TXD pin after releasing reset. P01 TEST Input RESET I/O VDD, AVDD VSS Fix to “High”. Reset signal input or an internal error reset output. 5V Power supply VAREF P07 to P02, P17 to P10, P22 to P20, P37 to P30, P43 to P40, P57 to P50, P67 to P60, P77 to P70 0V Leave open or apply reference voltage. I/O Open SEG7 to SEG0 Output 0 V output (Open) COM3 to COM0 Output 0 V output (Open) C0, C1, V1, V2, V3 XIN XOUT Pin Name (MCU mode) LCD power supply Input Output Not use Self oscillation with resonator (2 MHz, 4 MHz, 8 MHz, 16 MHz) 86FS27-5 2007-08-07 TMP86FS27 Operation This section describes the functions and basic operational blocks of TMP86FS27. The TMP86FS27 has flash memory in place of the mask ROM which is included in the TMP86CM27/P27. The configuration and function are the same as the TMP86C847/H47. 1. Operating Mode The TMP86FS27 has MCU mode and serial PROM mode. 1.1 MCU Mode The MCU mode is set by fixing the TEST pin to the low level. In the MCU mode, the operation is the same as the TMP86CM27/P27 (TEST pin cannot be used open because it has no built-in pull-down resistor). 1.1.1 Program memory The TMP86FS27 has a 60-Kbyte built-in flash memory (addresses 1000H to FFFFH in the MCU mode). When using TMP86FS27 for evaluation of TMP86CM27/P27, the program is written by the serial PROM mode. 0000H 0000H 4000H 4000H Program Program FFFFH FFFFH MCU mode TMP86FS27 TMP86CP27 (a) ROM Size = 48 Kbytes 0000H 0000H 8000H 8000H Program Program FFFFH FFFFH TMP86CM27 MCU mode TMP86FS27 (b) ROM Size = 32 Kbytes Figure 1.1.1 Program Memory Area Note: The area that is not in use should be set data to FFH. 86FS27-6 2007-08-07 TMP86FS27 1.1.2 Data Memory TMP86FS27 has a built-in 1024-byte data memory (Static RAM). 1.1.3 Input/Output Circuitry (1) Control pins The control pins of the TMP86FS27 are the same as those of the TMP86CM27/P27. (2) I/O ports The I/O circuitries of TMP86FS27 I/O ports are the same as the those of TMP86CM27/P27. 86FS27-7 2007-08-07 TMP86FS27 2. Serial PROM Mode 2.1 Outline The TMP86FS27 has a 2-Kbyte BOOT ROM for programming to flash memory. This BOOT ROM is a mask ROM that contains a program to write the flash memory on-board. The BOOT ROM is available in a serial PROM mode and it is controlled by TEST pin and RESET pin and P00 and P01 pin, and is communicated with UART. There are four operation modes in a serial PROM mode: flash memory writing mode, RAM loader mode, flash memory SUM output mode and product discrimination code output mode. Operating area of serial PROM mode differs from that of MCU mode. The operating area of serial PROM mode shows in Table 2.1.1. Table 2.1.1 Operating Area of Serial PROM Mode 2.2 Parameter Symbol Min Max Operating voltage VDD 4.5 5.5 Unit High frequency fc 2, 4, 8, 16 MHz Temperature Topr 25 ± 5 °C V Memory Mapping The BOOT ROM is mapped in address F800H to FFFFH. The BOOT ROM can’t be accessed in MCU mode. The Figure 2.2.1 shows a memory mapping. 0000H SFR 0000H SFR 64 bytes 003FH 0040H RAM 64 bytes 003FH 0040H RAM 1024 bytes 0423H 1024 bytes 0423H 0F80H DBR 128 bytes 0FFFH 1000H 61440 bytes Flash memory F800H BOOT ROM 2048 bytes FFFFH FFFFH MCU Serial PROM mode Figure 2.2.1 Memory Address Maps 86FS27-8 2007-08-07 TMP86FS27 2.3 Serial PROM Mode Setting 2.3.1 Serial PROM Mode Control Pins To execute on-board programming, start the TMP86FS27 in serial PROM mode. Setting of a serial PROM mode is shown in Table 2.3.1. Table 2.3.1 Serial PROM Mode Setting Pin Setting TEST pin High BOOT1 (RXD) (Note) High BOOT2 (TXD) (Note) High RESET pin Note: BOOT1 is RXD pin and BOOT2 is TXD pin during a serial PROM mode. 2.3.2 Pin Function In the serial PROM mode, TXD (P01) and RXD (P00) pins are used as a serial interface pin. Therefore, if the programming is executed on-board after mounting, these pins should be released from the other devices for communication in serial PROM mode. Pin Name (Serial PROM mode) Input/ Output Functions BOOT1/RXD Input/Input Fix “High” during reset. This pin is used as RXD pin after releasing reset. P00 BOOT2/TXD Input/Output Fix “High” during reset. This pin is used as TXD pin after releasing reset. P01 TEST Input RESET I/O VDD, AVDD VSS Fix to “High”. Reset signal input or an internal error reset output. 5V Power supply VAREF P07 to P02, P17 to P10, P22 to P20, P37 to P30, P43 to P40, P57 to P50, P67 to P60, P77 to P70 0V Leave open or apply reference voltage. I/O Open SEG7 to SEG0 Output 0 V output (Open) COM3 to COM0 Output 0 V output (Open) C0, C1, V1, V2, V3 XIN XOUT Pin Name (MCU mode) LCD power supply Input Output Not use Self oscillation with resonator (2 MHz, 4 MHz, 8 MHz, 16 MHz) Note: When the device is used as on-board writing and other parts are already mounted in place, be careful not to affect these communication control pins. 86FS27-9 2007-08-07 TMP86FS27 To set a serial PROM mode, connect device pins as shown in Figure 2.3.1. TMP86FS27 VDD(4.5 V to 5.5 V) VDD AVDD TEST XIN P00 BOOT1/RXD P01 BOOT2/TXD RESET VAREF XOUT OPEN or analog reference voltage. VSS : Pull up Figure 2.3.1 Serial PROM Mode Port Setting 2.3.3 Activating Serial PROM Mode The following is a procedure of setting of serial PROM mode. Figure 2.3.2 shows a serial PROM mode timing. (1) Turn on the power to the VDD pin. (2) Set the RESET to low level. (3) Set the TEST, BOOT1 and BOOT2 pin to high level. (4) Wait until the power supply and clock sufficiently stabilize. (5) Release the RESET (Set to high level). (6) Input a matching data (5AH) to BOOT1/RXD pin after waiting for setup sequence. For details of the setup timing, refer to 2.14 “UART Timing”. VDD TEST (Input) RESET (Input) Program Indeterminate Reset mode BOOT1 (Input)/ RXD (Input) Serial PROM mode Setup time for serial PROM mode (Rxsup) Fixed to high level by pull up Matching data input BOOT2 (Input)/ TXD (Output) Figure 2.3.2 Serial PROM Mode Timing 86FS27-10 2007-08-07 TMP86FS27 2.4 Interface Specifications for UART The following shows the UART communication format used in serial PROM mode. Before on-board programming can be executed, the communication format on the external controller side must also be setup in the same way as for this product. Note that although the default baud rate is 9,600 bps, it can be changed to other values as shown in Table 2.4.1. The Table 2.4.2 shows an operating frequency and baud rate in serial PROM mode. Except frequency which is not described in Table 2.4.2 can not use in serial PROM mode. Baud rate (Default): 9,600 bps Data length: 8 bits Parity addition: None Stop bit length: 1 bit Table 2.4.1 Baud Rate Modification Data Baud rate modification data Baud rate (bps) 04H 05H 07H 0AH 18H 28H 76800 62500 38400 31250 19200 9600 Table 2.4.2 Operating Frequency and Baud Rate in Serial PROM Mode Reference Baud 76800 Rate (Baud) Baud Rate 04H Modification Data Reference Frequency (bps) (%) (MHz) 2 4 8 16 Note: 2.5 – – – 76923 – – – +0.16 62500 38400 31250 19200 9600 05H 07H 0AH 18H 28H (bps) (%) (bps) (%) (bps) (%) (bps) – – 62500 62500 – – 0.00 0.00 – – 38462 38462 – – +0.16 +0.16 – 31250 31250 31250 – 0.00 0.00 0.00 – 19231 19231 19231 (%) (bps) (%) – 9615 9615 9615 9615 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 “Reference Frequency” shows the high-frequency area supported in serial PROM mode. Except the above frequency can not be supported in serial PROM mode. Command There are five commands in serial PROM mode. After reset release, the TMP86FS27 waits a matching data (5AH). Table 2.5.1 Command in Serial PROM Mode Command Data Operation Mode Remarks 5AH 30H 60H Setup Flash memory writing RAM loader 90H Flash memory SUM output C0H Product discrimination code output Matching data. Always start with this command after reset release. Writing to area from 1000H to FFFFH is enable. Writing to area from 0050H to 0430H is enable. The checksum of entire flash memory area (from 1000H to FFFFH) is output in order of the upper byte and the lower byte. Product discrimination code, that is expressed by 13 bytes data, is output. 86FS27-11 2007-08-07 TMP86FS27 2.6 Operation Mode There are four operating modes in serial PROM mode: Flash memory writing mode, RAM loader mode, flash memory SUM output mode and product discrimination code output mode. For details about these modes, refer to (1) Flash memory writing mode through (4) Product discrimination code output mode. (1) Flash memory writing mode The data are written to the specified flash memory addresses. The controller should send the write data in the Intel Hex format (Binary). For details of writing data format, refer to 2.7 “Flash Memory Writing Data Format”. If no errors are encountered till the end record, the SUM of 60 Kbytes of flash memory is calculated and the result is returned to the controller. To execute the flash memory writing mode, the TMP86FS27 checks the passwords except a blank product. If the passwords did not match, the program is not executed. (2) RAM loader mode The RAM loader transfers the data into the internal RAM that has been sent from the controller in Intel Hex format. When the transfer has terminated normally, the RAM loader calculates the SUM and sends the result to the controller before it starts executing the user program. After sending of SUM, the program jumps to the start address of RAM in which the first transferred data has been written. This RAM loader function provides the user's own way to control on-board programming. To execute the RAM loader mode, the TMP86FS27 checks the passwords except a blank product. If the passwords did not match, the program is not executed. (3) Flash memory SUM output mode The SUM of 60 Kbytes of flash memory is calculated and the result is returned to the controller. The BOOT ROM does not support the reading function of the flash memory. Instead, it has this SUM command to use. By reading the SUM, it is possible to manage Revisions of application programs. (4) Product discrimination code output mode The product discrimination code is output as a 13-byte data, that includes the start address and the end address of ROM. (In case of TMP86FS27, the start address is 1000H and the end address is FFFFH.) Therefore, the controller can recognize the device information by using this function. 86FS27-12 2007-08-07 TMP86FS27 2.6.1 Flash Memory Writing Mode (Operation command: 30H) Table 2.6.1 shows flash memory writing mode process. Table 2.6.1 Flash Memory Writing Mode Process Transfer Data from External Controller to TMP86FS27 Number of Bytes Transferred BOOT ROM Baud Rate 1st byte 2nd byte Matching data (5AH) − 9600 bps 9600 bps 3rd byte 9600 bps 4th byte Baud rate modification data (See Table 2.4.1) − 5th byte 6th byte Operation command data (30H) − Changed new baud rate Changed new baud rate 7th byte 8th byte Address 15 to 08 in which to store Password count (Note 4) Changed new baud rate Changed new baud rate 9th byte 10th byte Address 07 to 00 in which to store Password count (Note 4) Changed new baud rate Changed new baud rate 11th byte 12th byte Address 15 to 08 in which to start Password comparison (Note 4) Address 07 to 00 in which to start Password comparison (Note 4) Password string (Note 5) Changed new baud rate Changed new baud rate − Changed new baud rate m'th + 1 byte : n'th − 2 byte n'th − 1 byte Extended Intel format (binary) (Note 2, 6) Changed new baud rate − Changed new baud rate n'th byte − Changed new baud rate n'th + 1 byte (Wait for the next operation) (Command data) Changed new baud rate 13th byte 14th byte 15th byte : m'th byte 9600 bps Changed new baud rate Changed new baud rate Changed new baud rate Transfer Data from TMP86FS2786FS27 to External Controller − (Baud rate auto set) OK: Echo back data (5AH) Error: Nothing transmitted − OK: Echo back data Error: A1H × 3, A3H × 3, 62H × 3 (Note 1) − OK: Echo back data (30H) Error: A1H × 3, A3H × 3, 63H × 3 (Note 1) − OK: Nothing transmitted Error: Nothing transmitted − OK: Nothing transmitted Error: Nothing transmitted − OK: Nothing transmitted Error: Nothing transmitted − OK: Nothing transmitted Error: Nothing transmitted − OK: Nothing transmitted Error: Nothing transmitted − OK: SUM (High) (Note 3) Error: Nothing transmitted OK: SUM (Low) (Note 3) Error: Nothing transmitted − Note 1: “xxH × 3” denotes that operation stops after sending 3 bytes of xxH. For details, refer to 2.8 “Error Code”. Note 2: Refer to 2.10 “Intel Hex Format (Binary)”. Note 3: Refer to 2.9 “Checksum (SUM)”. Note 4: Refer to 2.11 “Passwords”. Note 5: If all data of vector area are “00H” or “FFH”, the passwords comparison is not executed because the device is considered as blank product. However, it is necessary to specify the password count storage addresses and the password comparison start address even though it is a blank product. If a password error occurs, the UART function of TMP86FS27 stops without returning error code to the controller. Therefore, when a password error occurs, the TMP86FS27 should be reset by RESET pin input. Note 6: The time between data records needs over 1 ms. 86FS27-13 2007-08-07 TMP86FS27 Description of flash memory writing mode 1. The receive data in the 1st byte is the matching data. When the boot program starts in serial PROM mode, TMP86FS27 (Mentioned as “device” hereafter) waits for the matching data (5AH) to receive. Upon receiving the matching data, it automatically adjusts the UART’s initial baud rate to 9,600bps. 2. When the device has received the matching data, the device transmits the data “5AH” as an echo back to the controller. If the device can not receive the matching data, the device does not transmit the echo back data and waits for the matching data again with changing baud rate. Therefore, the controller should send the matching data continuously until the device transmits the echo back data. 3. The receive data in the 3rd byte is the baud rate modification data. The six kinds of baud rate modification data shown in Table 2.4.1 are available. Even if baud rate changing is no need, be sure to send the initial baud rate data (28H: 9,600 bps). The changing of baud rate is executed after transmitting the echo back data. 4. When the 3rd byte data is one of the baud rate modification data corresponding to the device's operating frequency, the device sends the echo back data which is the same as received baud rate modification data. Then the baud rate is changed. If the 3rd byte data does not correspond to the baud rate modification data, the device stops UART function after sending 3 bytes of baud rate modification error code: (62H). 5. The receive data in the 5th byte is the command data (30H) to write the flash memory. 6. When the 5th byte is one of the operation command data shown in Table 2.5.1, the device sends the echo back data which is the same as received operation command data (in this case, 30H). If the 5th byte data does not correspond to the operation command data, the device stops UART function after sending 3 bytes of operation command error code: (63H). 7. The 7th byte is used as an upper bit (Bit15 to bit8) of the password count storage address. When the receiving is executed correctly (No error), the device does not send any data. If the receiving error or password error occur, the device does not send any data and stops UART function. 8. The 9th byte is used as a lower bit (Bit7 to bit0) of the password count storage address. When the receiving is executed correctly (No error), the device does not send any data. If the receiving error or password error occur, the device does not send any data and stops UART function. 9. The 11th byte is used as an upper bit (Bit15 to bit8) of the password comparison start address. When the receiving is executed correctly (No error), the device does not send any data. If the receiving error or password error occur, the device does not send any data and stops UART function. 10. The 13th byte is used as a lower bit (Bit7 to bit0) of the password comparison start address. When the receiving is executed correctly (No error), the device does not send any data. If the receiving error or password error occur, the device does not send any data and stops UART function. 11. The 15th through the m’th bytes are the password data. The number of passwords is the data (N) indicated by the password count storage address. The password data are compared for N entries beginning with the password comparison start address. The controller should send N bytes of password data to the device. If the passwords do not match, the device stops UART function without returning error code to the controller. If the data of vector addresses (FFE0H to FFFFH) are all “FFH”, the comparison of passwords is not executed because the device is considered as a blank product. 86FS27-14 2007-08-07 TMP86FS27 12. The receive data in the m’th + 1 through n’th − 2 byte are received as binary data in Intel Hex format. No received data are echoed back to the controller. The data which is not the start mark (3AH for “:”) in Intel Hex format is ignored and does not send an error code to the controller until the device receives the start mark. After receiving the start mark, the device receives the data record, that consists of length of data, address, record type, writing data and checksum. After receiving the checksum of data record, the device waits the start mark data (3AH) again. The data of data record is temporarily stored to RAM and then, is written to specified flash memory by page (32 bytes) writing. For details of an organization of flash memory, refer to 2. “Serial PROM Mode”. Since after receiving an end record, the device starts to calculate the SUM, the controller should wait the SUM after sending the end record. If receive error or Intel Hex format error occurs, the device stops UART function without returning error code to the controller. 13. The n’th − 1 and the n’th bytes are the SUM value that is sent to the controller in order of the upper byte and the lower byte. For details on how to calculate the SUM, refer to 2.9 “Checksum (SUM)”. The SUM calculation is performed after detecting the end record, but the calculation is not executed when receive error or Intel Hex format error has occurred. The time required to calculate the SUM of the 60 Kbytes of Flash memory area is approximately 375 ms at fc = 16 MHz. After the SUM calculation, the device sends the SUM data to the controller. After sending the end record, the controller can judge that the transmission has been terminated correctly by receiving the checksum. 14. After sending the SUM, the device waits for the next operation command data. 86FS27-15 2007-08-07 TMP86FS27 2.6.2 RAM Loader Mode (Operation command: 60H) Table 2.6.2 shows RAM loader mode process. Table 2.6.2 RAM Loader Mode Process Transfer Data from External Controller to TMP86FS27 Number of Bytes Transferred Baud Rate Transfer Data from TMP86FS27 to External Controller 1st byte Matching data (5AH) 9600 bps − (Baud rate auto set) 2nd byte − 9600 bps OK: Echo back data (5AH) 3rd byte Baud rate modification data 9600 bps Error: Nothing transmitted − 9600 bps OK: Echo back data (See Table 2.4.1) 4th byte 5th byte Operation command data (60H) 6th byte − 7th byte OK: Echo back data (60H) Error: A1H × 3, A3H × 3, 63H × 3 (Note 1) − Changed new baud rate Changed new baud rate Address 07 to 00 in which to store Password count (Note 4) Changed new baud rate Changed new baud rate Address 15 to 08 in which to start Password comparison (Note 4) Changed new baud rate Changed new baud rate 14th byte Address 07 to 00 in which to start Password comparison (Note 4) Changed new baud rate Changed new baud rate 15th byte Password string (Note 5) Changed new baud rate m'th byte − Changed new baud rate m'th + 1 byte Extended Intel format (Binary) Changed new baud rate Error: Nothing transmitted − 9th byte 10th byte 11th byte 12th byte 13th byte : : RAM Changed new baud rate Changed new baud rate Error:A1H × 3, A3H × 3, 62H × 3 (Note 1) − Address 15 to 08 in which to store Password count (Note 4) 8th byte BOOT ROM − OK: Nothing transmitted Error: Nothing transmitted − OK: Nothing transmitted Error: Nothing transmitted − OK: Nothing transmitted Error: Nothing transmitted − OK: Nothing transmitted Error: Nothing transmitted − OK: Nothing transmitted (Note 2) n'th − 2 byte n'th − 1 byte − Changed new baud rate OK: SUM (High) (Note 3) n'th byte − Changed new baud rate Error: Nothing transmitted OK: SUM (Low) (Note 3) − Error: Nothing transmitted The program jumps to the start address of RAM in which the first transferred data has been written. Note 1: “xxH × 3” denotes that operation stops after sending 3 bytes of xxH. For details, refer to 2.8 “Error Code”. Note 2: Refer to 2.10 “Intel Hex Format (Binary)”. Note 3: Refer to 2.9 “Checksum (SUM)”. Note 4: Refer to 2.11 “Passwords”. 86FS27-16 2007-08-07 TMP86FS27 Note 5: If all data of vector area are “00H” or “FFH”, the passwords comparison is not executed because the device is considered as blank product. However, it is necessary to specify the password count storage addresses and the password comparison start address even though it is a blank product. If a password error occurs, the UART function of TMP86FS27 stops without returning error code to the controller. Therefore, when a password error occurs, the TMP86FS27 should be reset by RESET pin input. Note 6: Do not send only end record after transferring of password string. If the TMP86FS27 receives the end record only after reception of password string, it does not operate correctly. Description of RAM loader mode 1. The process of the 1st byte through the 4th byte are the same as flash memory writing mode. 2. The receive data in the 5th byte is the RAM loader command data (60H) to write the user’s program to RAM. 3. When the 5th byte is one of the operation command data shown in Table 2.5.1, the device sends the echo back data which is the same as received operation command data (in this case, 60H). If the 5th byte data does not correspond to the operation command data, the device stops UART function after sending 3 bytes of operation command error code: (63H). 4. The process of the 7th byte through the m’th byte are the same as flash memory writing mode. 5. The receive data in the m’th + 1 through n’th − 2byte are received as binary data in Intel Hex format. No received data are echoed back to the controller. The data which is not the start mark (3AH for “:”) in Intel Hex format is ignored and does not send an error code to the controller until the device receives the start mark. After receiving the start mark, the device receives the data record, that consists of length of data, address, record type, writing data and checksum. After receiving the checksum of data record, the device waits the start mark data (3AH) again. The data of data record is written to specified RAM by the receiving data. Since after receiving an end record, the device starts to calculate the SUM, the controller should wait the SUM after sending the end record. If receive error or Intel Hex format error occurs, the UART function of TMP86FS27 stops without returning error code to the controller. 6. The n’th − 1 and the n’th bytes are the SUM value that is sent to the controller in order of the upper byte and the lower byte. For details on how to calculate the SUM, refer to 2.9 “Checksum (SUM)”. The SUM calculation is performed after detecting the end record, but the calculation is not executed when receive error or Intel Hex format error has occurred. The SUM is calculated by the data written to RAM, but the length of data, address, record type and checksum in Intel Hex format are not included in SUM. 7. The boot program jumps to the first address that is received as data in Intel Hex format after sending the SUM to the controller. 86FS27-17 2007-08-07 TMP86FS27 2.6.3 Flash Memory Memory SUM Output Mode (Operation command: 90H) Table 2.6.3 shows flash memory SUM output mode process. Table 2.6.3 Flash Memory Memory SUM Output Process Transfer Data from External Controller to TMP86FS27 Number of Bytes Transferred 1st byte 2nd byte Matching data (5AH) − 9600 bps 9600 bps 3rd byte Baud rate modification data (See Table 2.4.1) − 9600 bps 5th byte 6th byte Operation command data (90H) − Changed new baud rate Changed new baud rate 7th byte − Changed new baud rate 8th byte − Changed new baud rate 9th byte (Wait for the next operation) (Command data) Changed new baud rate 4th byte BOOT ROM Baud Rate 9600 bps Transfer Data from TMP86FS27 to External Controller − (Baud rate auto set) OK: Echo back data (5AH) Error: Nothing transmitted − OK: Echo back data Error: A1H × 3, A3H × 3, 62H × 3 (Note 1) − OK: Echo back data (90H) Error: A1H × 3, A3H × 3, 63H × 3 (Note 1) OK: SUM (High) (Note 2) Error: Nothing transmitted OK: SUM (Low) (Note 2) Error: Nothing transmitted − Note 1: “xxH × 3” denotes that operation stops after sending 3 bytes of xxH. For details, refer to 2.8 “Error Code”. Note 2: Refer to 2.9 “Checksum (SUM)” Description of flash memory SUM output mode 1. The process of the 1st byte through the 4th byte are the same as flash memory writing mode. 2. The receive data in the 5th byte is the flash memory SUM command data (90H) to calculate the entire flash memory. 3. When the 5th byte is one of the operation command data shown in Table 2.5.1, the device sends the echo back data which is the same as received operation command data (in this case, 90H). If the 5th byte data does not correspond to the operation command data, the device stops UART function after sending 3 bytes of operation command error code: (63H). 4. The 7th and the 8th bytes are the SUM value that is sent to the controller in order of the upper byte and the lower byte. For details on how to calculate the SUM, refer to 2.9 “Checksum (SUM)”. 5. After sending the SUM, the device waits for the next operation command data. 86FS27-18 2007-08-07 TMP86FS27 2.6.4 Product Discrimination Code Output Mode (Operation command: C0H) Table 2.6.4 shows product discrimination code output mode process. Table 2.6.4 Product Discrimination Code Output Process Number of Bytes Transferred Baud Rate 1st byte 2nd byte Matching data (5AH) − 9600 bps 9600 bps 3rd byte Baud rate modification data (See Table 2.4.1) − 9600 bps 4th byte 5th byte 6th byte BOOT ROM Transfer Data from External Controller to TMP86FS27 Operation (C0H) − command 9600 bps data Changed new baud rate Changed new baud rate 7th byte 8th byte Changed new baud rate Changed new baud rate 9th byte 10th byte 11th byte 12th byte 13th byte 14th byte Changed new baud rate Changed new baud rate Changed new baud rate Changed new baud rate Changed new baud rate Changed new baud rate 15th byte Changed new baud rate 16th byte Changed new baud rate 17th byte Changed new baud rate 18th byte Changed new baud rate 19th byte Changed new baud rate 20th byte (Wait for the next operation) (Command data) Changed new baud rate Transfer Data from TMP86FS27 to External Controller − (Baud rate auto set) OK: Echo back data (5AH) Error: Nothing transmitted − OK: Echo back data Error: A1H × 3, A3H × 3, 62H × 3 (Note 1) − OK: Echo back data (C0H) Error: A1H × 3, A3H × 3, 63H × 3 (Note 1) 3AH Start mark 0AH The number of transfer data (from 9th to 18th byte) 02H Length of address (2 bytes) 03H Reserved data 00H Reserved data 00H Reserved data 00H Reserved data 01H The number of ROM block (1 block) 10H First address of ROM (Upper 8 bits) 00H First address of ROM (Lower 8 bits) FFH End address of ROM (Upper 8 bits) FFH End address of ROM (Lower 8 bits) ECH Checksum of transferred data (from 9th to 18th byte) − Note: “xxH × 3” denotes that operation stops after sending 3 bytes of xxH. For details, refer to 2.8 “Error Code”. Description of product discrimination code output mode 1. The process of the 1st byte through the 4th byte are the same as flash memory writing mode. 2. The receive data in the 5th byte is the product discrimination code output command data (C0H). 3. When the 5th byte is one of the operation command data shown in Table 2.5.1, the device sends the echo back data which is the same as received operation command data (in this case, C0H). If the 5th byte data does not correspond to the operation command data, the device stops UART function after sending 3 bytes of operation command error code: (63H). 4. The 9th and the 19th bytes are the product discrimination code. For details, refer to 2.12 “Product Discrimination Code”. 5. After sending the SUM, the device waits for the next operation command data. 86FS27-19 2007-08-07 TMP86FS27 2.7 Flash Memory Writing Data Format Flash memory area of TMP86FS27 consists of 1919 pages and one page size is 32 bytes. Writing to flash memory is executed by page writing. Therefore, it is necessary to send 32 bytes data (for one page) even though only a few bytes data are written. Figure 2.7.1 shows an organization of flash memory area. When the controller sends the writing data to the device, be sure to keep the format described below. 1. The address of data after receiving the flash memory writing command should be the first address of page. For example, in case of page 2, the first address should be 1040H. 2. If the last data’s address of data record is not end address of page, the address of the next data record should be the address + 1 and the last data’s address must point to the last address of this page. For example, if the last data’s address is 100FH (Page0), the address of the next data record should be 1010H (Page0) and the address of the last data should be 101FH (Page0). 3. The last data’s address of data record immediately before sending the end record should be the last address of page. For example, in case of page 1, the last data’s address of data record should be 103FH. Note: Do not write only the vector area (FFF0H to FFFFH) when all data of flash memory are the same data. If the vector area is only written, the next operation can not be executed because of password error. Address 0 1000H 1010H 1020H 1030H 1040H 1050H F 1060H 1070H 1080H 1090H 10A0H 10B0H 10C0H F F F F F 1 2 3 4 5 6 7 8 9 A B Page 0 Page 1 Page 2 Page 3 Page 4 Page 5 C D E F E E E E E E F E FF70H FF80H F FF90H FFA0H FFB0H F FFC0H FFD0H F FFE0H FFF0H F Page 1916 Page 1917 Page 1918 Page 1919 E E E E Note: “F” shows the first address of each page and “E” shows the last address of each page. Figure 2.7.1 Organization of Flash Memory Area 86FS27-20 2007-08-07 TMP86FS27 2.8 Error Code When the device detects an error, the error codes are sent to the controller. Table 2.8.1 Error Code Transmit Data 62H, 62H, 62H 63H, 63H, 63H A1H, A1H, A1H A3H, A3H, A3H 2.9 Meaning of Transmit Data Baud rate modification error occurred. Operating command error occurred. Framing error in received data occurred. Overrun error in received data occurred. Checksum (SUM) (1) Calculation method SUM consists of byte + byte.... + byte, the checksum of which is returned in word as the result. Namely, data is read out in byte and checksum of which is calculated, with the result returned in word. Example: A1H B2H C3H D4H If the data to be calculated consists of the four bytes shown to the left, SUM of the data is A1H + B2H + C3H + D4H = 02EAH = 02H SUM (HIGH) = EAH SUM (LOW) The SUM returned when executing the flash memory write command, RAM loader command, or flash memory SUM command is calculated in the manner shown above. (2) Calculation data The data from which SUM is calculated are listed in Table 2.9.1 below. Table 2.9.1 Checksum Calculation Data Operating Mode Calculation Data Remarks Even when written to part of the flash memory area, Flash memory writing mode data in the entire memory area (60 Kbytes) is Data in the entire area (60 Kbytes) of flash calculated. Flash memory Checksum output memory The length of data, address, record type and mode checksum in Intel Hex format are not included in SUM. The length of data, address, record type and RAM loader mode Data written to RAM checksum in Intel Hex format are not included in SUM. Product discrimination code out- Checksum of transferred data (from 9th to For details, refer to “2.6.4 Product Discrimination put mode 18th byte) Code Output Mode”. 86FS27-21 2007-08-07 TMP86FS27 2.10 Intel Hex Format (Binary) 1. After receiving the SUM of a record, the device waits for the start mark data (3AH for “:”) of the next record. Therefore, the device ignores the data, which does not match the start mark data after receiving the SUM of a record. 2. Make sure that once the controller program has finished sending the SUM of the end record, it does not send anything and waits for two bytes of data to be received (Upper and lower bytes of SUM). This is because after receiving the SUM of the end record, the boot program calculates the SUM and returns the calculated SUM in two bytes to the controller. 3. If a receive error or Intel Hex format error occurs, the UART function of TMP86FS27 stops without returning error code to the controller. In the following cases, an Intel Hex format error occurs: • When the record type is not 00H, 01H, or 02H • When a SUM error occurred • When the data length of an extended record (Type = 02H) is not 02H • When the address of an extended record (Type = 02H) is larger than 1000H and after that, receives the data record • When the data length of the end record (Type = 01H) is not 00H 2.11 Passwords The area in which passwords can be specified is located at addresses 1000H to FF9FH. The vector area (from FFA0H to FFFFH) can not be specified as passwords area. The device compares the stored passwords with the passwords, which are received from the controller. If all data of vector area are “00H” or “FFH”, the passwords comparison is not executed because the device is considered as blank product. It is necessary to specify the password count storage addresses and the password comparison start address even though it is a blank product. Table 2.11.1 Password Setting in the Blank Product and Non Blank Product Password Blank Product(Note 1) Non Blank Product PNSA (Password count storage addresses) PCSA (Password comparison start address) N (Password count) Setting of password 1000H ≤ PNSA ≤ FF9FH 1000H ≤ PNSA ≤ FF9FH 1000H ≤ PCSA ≤ FF9FH 1000H ≤ PCSA ≤ FFA0−N * 8≤N No need Need (Note 2) Note 1: When all data of addresses from FFE0H to FFFFH area are “00H” or “FFH”, the device is judged as blank product. Note 2: The same three or more bytes consecutive data can not be used as password. When the password includes the same consecutive data (three or more bytes), the password error occurs. If the password error occured, the UART function of device stops without returning error code. Note 3: *: Don’t care. Note 4: When the password doesn’t match the above condition, the password error occurs. If the password error occured, the UART function of device stops without returning error code. Note 5: In case of the blank product, the device receives Intel Hex Format immediately after receiving PCSA without receiving password strings. In this time, because the device ignores the data 86FS27-22 2007-08-07 TMP86FS27 except the start mark data (3AH for “:”) as Intel Hex Format data, even if external controller transmitted dummy password strings, process operates correctly. However, if the dummy password strings contain data “3AH”, the device detects it as start mark data mistakenly, and device stops process without returning error doce. Therefore, if these process becomes issue, the external controller should not transmit the dummy password strings. UART RXD pin F0H 12H F1H 07H 01H 02H 03H 04H 05H 06H 07H PNSA 08H Password string PCSA Flash memory F012H Example) PNSA = F012H PCSA = F107H Password string = 01H,02H,03H,04H,05H, 06H,07H,08H 08H F107H 01H F108H 02H F109H 03H F10AH 04H F10BH 05H F10CH 06H F10DH 07H F10EH 08H "08H" is treated as the number of password. Comparison 8 bytes Figure 2.11.1Password Comparison Example 86FS27-23 2007-08-07 TMP86FS27 3. Password string A password string sent from the controller is compared with the specified data in the flash memory. If the password string does not match the specified data in the flash memory, a password error occurs and the TMP86FS27 stops operating. 4. Handling of password error If a password error occurs, the UART function of TMP86FS27 stops without returning error code to the controller. Therefore, when a password error occurs, the TMP86FS27 should be reset by RESET pin input. 2.12 Product Discrimination Code The product discrimination code is a 13-byte data, that includes the start address and the end address of ROM. Table 2.12.1 shows the product discrimination code format. Table 2.12.1 Product Discrimination Code Format Data The Meaning of Data In Case of TMP86FS27 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 12th 13th Start mark (3AH) The number of transfer data (from 3rd to 13th byte) Length of address Reserved data Reserved data Reserved data Reserved data The number of ROM block The upper byte of the first address of ROM The lower byte of the first address of ROM The upper byte of the end address of ROM The lower byte of the end address of ROM Checksum of transferred data (from 3rd to 12th byte) 3AH 0AH 02H 03H 00H 00H 00H 01H 10H (Depends on the product) 00H (Depends on the product) FFH (Depends on the product) FFH (Depends on the product) ECH (Depends on the product) 86FS27-24 2007-08-07 TMP86FS27 2.14 UART Timing Table 2.14.1 UART Timing-1 (VDD = 4.5 V to 5.5 V, fc = 2 MHz, 4 MHz, 8 MHz, 16 MHz, Topr = 20 to 30°C) Parameter Time from the reception of a matching data until the output of an echo back Time from the reception of a baud rate modification data until the output of an echo back Time from the reception of an operation command until the output of an echo back Calculation time of checksum Required Minimum Time At fc = 16 At fc = 2 MHz MHz Symbol The Number of Clock (fc) CMeb1 Approx. 600 300 µs 37.5 µs CMeb2 Approx. 500 250 µs 31.3 µs CMeb3 Approx. 500 250 µs 31.3 µs CKsm Approx. 1573000 786.5 ms 98.3 ms Table 2.14.2 UART Timing-2 (VDD = 4.5 V to 5.5 V, fc = 2 MHz, 4 MHz, 8 MHz, 16 MHz, Topr = 20 to 30°C) Required Minimum Time At fc = 16 At fc = 2 MHz MHz Parameter Symbol The Number of Clock (fc) Time from reset release until acceptance of start bit of RXD pin Time between a matching data and the next matching data Time from the echo back of matching data until the acceptance of baud rate modification data Time from the output of echo back of baud rate modification data until the acceptance of an operation command Time from the output of echo back of operation command until the acceptance of Password count storage addresses RXsup CMtr1 25000 28500 12.5 ms 14.3 ms 1.56 ms 1.8 ms CMtr2 400 200 µs 25 µs CMtr3 500 250 µs 31.3 µs CMtr4 2600 1.3 ms 163 µs Table 2.14.3 UART Timing-3 (VDD = 4.5 V to 5.5 V, fc = 2 MHz, 4 MHz, 8 MHz, 16 MHz, Topr = 20 to 30°C) Parameter Symbol Min. Max. Unit Time from the stop bit of the previous data record to start bit of the next data record tSU; ST 1 − ms CMtr2 RXsup CMtr3 CMtr4 RESET pin (TMP86FS27) (28H) (5AH) (30H) RXD pin (TMP86FS27) (5AH) (28H) (30H) TXD pin (TMP86FS27) CMeb1 (5AH) CMeb2 (5AH) CMeb3 (5AH) RXD pin (TMP86FS27) TXD pin (TMP86FS27) CMtr1 STOP bit The end byte of a data record START bit RXD pin (TMP86FS27) TXD pin (TMP86FS27) tSU; ST 86FS27-26 2007-08-07 TMP86FS27 Electrical Characteristics Absolute Maximum Ratings Parameter (VSS = 0 V) Symbol Pins Rating Unit Supply voltage VDD −0.3 to 6.5 Input voltage VIN −0.3 to VDD + 0.3 Output voltage VOUT1 −0.3 to VDD + 0.3 Output current (Per 1 pin) Output current (Total) Power dissipation [Topr = 70°C] Soldering temperature (time) Storage temperature Operating temperature IOUT1 P0, P1, P3, P4, P6 ports −1.8 IOUT2 P0, P1, P2, P4, P5, P6, P7 ports 3.2 IOUT3 P3 port 30 ΣIOUT1 P0, P1, P3, P4, P6 ports −30 ΣIOUT2 P0, P1, P2, P4, P5, P6, P7 ports 60 ΣIOUT3 P3 port V mA 80 PD Tsld Tstg Topr 250 260 (10 s) −55 to 125 −40 to 70 mW °C Note: The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded. Recommended Operating Condition 1) MCU mode (VSS = 0 V, Topr = −40 to 70ºC) Parameter Supply voltage Input high level Symbol Pins NORMAL1, 2 mode fc = 16 MHz IDLE0, 1, 2 mode NORMAL1, 2 mode fc = 8 MHz IDLE0, 1, 2 mode SLOW1, 2 mode fs = 32.768 kHz SLEEP0, 1, 2 mode STOP mode VDD VIH1 Except hysteresis input VIH2 Hysteresis input VIL1 Input low level Except hysteresis input Hysteresis input VDD ≥ 4.5 V Min fc XIN, XOUT fs XTIN, XTOUT VDD = 4.5 to 5.5 V VDD = 2.7 to 5.5 V 2.7 Unit 5.5 2.0 VDD × 0.70 VDD × 0.75 V VDD VDD × 0.90 VDD × 0.30 0 VDD × 0.25 VDD × 0.10 1.0 30.0 86FS27-27 Max 4.5 VDD < 4.5 V VIL3 Clock frequency VDD ≥ 4.5 V VDD < 4.5 V VIH3 VIL2 Condition 16.0 8.0 34.0 MHz kHz 2007-08-07 TMP86FS27 (VSS = 0 V, Topr = −40 to 70°C) DC Characteristics Parameter Min Typ. Max Unit − 0.9 − V − − ±2 µA TEST pull down − 70 − RIN2 RESET pull up 100 200 450 Rfx1 XIN-XOUT − 1.2 − Rfxt XTIN-XTOUT − 6 − Output leakage current ILO1 Sink open drain VDD = 5.5 V, VOUT = 5.5 V − − 2 ILO2 Tri-state VDD = 5.5 V, VOUT = 5.5/0 V − − ±2 Output high voltage VOH1 Tri-state VDD = 4.5 V, lOH = −0.7 mA 4.1 − − Except XOUT and P3 ports Except XOUT and P3 ports VDD = 4.5 V, IOL = 1.6 mA − − 0.4 VDD = 4.5 V, VOL = 0.4 V − 1.6 − P3 (High current port) VDD = 4.5 V, VOL = 1.0 V Hysteresis voltage Input current Input resistance High frequency feedback resistor Low frequency feedback resistor Output low voltage Output low current Symbol Hysteresis input IIN1 TEST IIN2 Sink open drain, tri-state IIN3 RESET, STOP RIN1 Condition VDD = 5.5 V, VIN = 5.5/0 V VOL IOL Supply current in NORMAL 1, 2 mode Supply current in IDLE1, 2 mode Supply current in IDLE0 mode IDD VDD = 3.0 V VIN = 2.8 V/0.2 V 20 − 8 15 − 6 12.5 When a program operates on flash memory − 1200 2400 When a program operates on RAM − 12 23 − 8 20 − 6 17 − 0.5 10 fs = 32.768 kHz Supply current in SLEEP0 mode VDD = 5.0 V VIN = 5.3 V/0.2 V V mA 13 fc = 16 MHz fs = 32.768 kHz µA 20 − VDD = 5.5 V VIN = 5.3 V/0.2 V Supply current in SLEEP1 mode Supply current in STOP mode kΩ MΩ IOL2 Supply current in SLOW1 mode Pins VHS mA µA Note 1: Typical values show those at Topr = 25°C, VDD = 5 V. Note 2: Input current (IIN1, IIN3); The current through pull-down or pull-up resistor is not included. Note 3: IDD does not include IREF current. Note 4: The supply currents of SLOW2 and SLEEP2 modes are equivalent to IDLE1, 2. 86FS27-28 2007-08-07 TMP86FS27 AD Conversion Characteristics Parameter Analog reference voltage Power supply voltage of analog control circuit Analog reference voltage range (Note 4) Symbol (VSS = 0 V, 4.5 V ≤ VDD ≤ 5.5 V, Topr = −40 to 70°C) Condition VAREF Min Typ. Max AVDD − 1.0 − AVDD AVDD Unit VDD V ∆VAREF 3.5 − VDD Analog input voltage VAIN VSS − VAREF Power supply current of analog reference voltage IREF − 0.6 1.0 mA − − − − − − − − ±2 ±2 ±2 ±4 LSB Non linearity error Zero point error Full scale error Total error (Note 1) VDD = AVDD = VAREF = 5.5 V VSS = AVSS = 0.0 V VDD = AVDD = 5.0 V VSS = AVSS = 0.0 V VAREF = 5.0 V (VSS = 0 V, 2.7 V ≤ VDD < 4.5 V, Topr = −40 to 70°C) Parameter Analog reference voltage Power supply voltage of analog control circuit Analog reference voltage range (Note 4) Analog input voltage Power supply current of analog reference voltage Non linearity error Zero point error Full scale error Total error (Note 1) Symbol Condition VAREF Min Typ. Max AVDD − 1.0 − AVDD Unit VDD AVDD V ∆VAREF VAIN IREF VDD = AVDD = VAREF = 4.5V VSS = AVSS = 0.0 V VDD = AVDD = 2.7 V VSS = 0.0 V VAREF = 2.7 V 2.5 − VDD VSS − VAREF − 0.5 0.8 mA − − − − − − − − ±2 ±2 ±2 ±4 LSB Note 1: The total error includes all errors except a quantization error, and is defined as a maximum deviation from the ideal conversion line. Note 2: Conversion time is different in recommended value by power supply voltage. Note 3: Please use input voltage to AIN input pin in limit of VAREF − VSS. When voltage of range outside is input, conversion value becomes unsettled and gives affect to other channel conversion value. Note 4: Analog reference voltage range: ∆VAREF = VAREF − VSS 86FS27-29 2007-08-07 TMP86FS27 Recommended Oscillating Conditions XIN C1 XOUT C2 High-frequency oscillation XTIN C1 XTOUT C2 Low-frequency oscillation Note 1: A quartz resonator can be used for high-frequency oscillation only when VDD is 2.7 V or above. If VDD is below 2.7 V, use a ceramic resonator. Note 2: To ensure stable oscillation, the resonator position, load capacitance, etc. must be appropriate. Because these factors are greatly affected by board patterns, please be sure to evaluate operation on the board on which the device will actually be mounted. Note 3: For the resonators to be used with Toshiba microcontrollers, we recommend ceramic resonators manufactured by Murata Manufacturing Co., Ltd. For details, please visit the website of Murata at the following URL: http://www.murata.com Handling Precaution • The solderability test conditions for lead-free products (indicated by the suffix G in product name) are shown below. 1. When using the Sn-63Pb solder bath Solder bath temperature = 230 °C Dipping time = 5 seconds Number of times = once R-type flux used 2. When using the Sn-3.0Ag-0.5Cu solder bath Solder bath temperature = 245 °C Dipping time = 5 seconds Number of times = once R-type flux used The pass criteron of the above test is as follows: Solderability rate until forming ≥ 95 % • When using the device (oscillator) in places exposed to high electric fields such as cathoderay tubes, we recommend electrically shielding the package in order to maintain normal operating condition. 86FS27-31 2007-08-07 TMP86FS27 Package Dimensions Unit: mm P-QFP80-1420-0.80M 23.8 0.2 20.0 0.1 40 80 25 14.0 0.1 65 24 0.35 0~10 0.15 0.08 0.04 0.1 0.16 M 3.05MAX 0.8 0.8 TYP 0.1 0.06 2.7 0.2 1 17.8 0.2 41 0.19 0.1 1.0 TYP 64 0.8 0.2 86FS27-32 2007-08-07