TLC5942 www.ti.com SBVS096B – OCTOBER 2007 – REVISED OCTOBER 2007 16-Channel, 12-Bit PWM LED Driver with 7-Bit Dot Correction • FEATURES 1 • 16 Channels, Constant Current Sink Output • 50-mA Capability (Constant Current Sink) • 12-Bit (4096 Steps) Grayscale Control with PWM • 7-Bit (128 Steps) Dot Correction with Sink Current • LED Power-Supply Voltage up to 17 V • Constant Current Accuracy: – Channel-to-Channel = ±1.5% – Device-to-Device = ±3% • VCC = 3.0 V to 5.5 V • CMOS Level I/O • 30-MHz Data Transfer Rate • 30-MHz Grayscale Control Clock • Dedicated Ports for Grayscale and Dot Correction • Continuous Base LED Open Detection (LOD) • Thermal Shutdown (TSD): – Automatic shutdown at high temperature conditions – Restart under normal temperature 23 • • APPLICATIONS • • • The TLC5942 is a 16-channel, constant current sink driver. Each channel is individually adjustable with 4096 pulse-width modulated (PWM) steps and 128 constant current sink steps for dot correction. Dot correction adjusts the brightness variations between LEDs. Both grayscale control and dot correction are accessible via separate, dedicated serial interface ports. The maximum current value of all 16 channels can be set by a single external resistor. VLED VLED ¼ OUT0 GSSIN GSSCLK Controller for Grayscale XGSLAT (Outside of BLANK LED module) Monochrome, Multicolor, Full-Color LED Displays LED Signboards Display Backlighting DESCRIPTION VLED GSDATA Readable Error Information: – LED Open Detection – Thermal Error Flag (TEF) Noise Reduction: – 4-Channel grouped delay to prevent inrush current Operating Temperature: –40°C to +85°C ¼ ¼ OUT15 OUT0 GSSOUT GSSIN GSSCLK XGSLAT DCSIN TLC5942 IC1 IREF RIREF OUT15 GSSOUT XGSLAT TLC5942 ICn BLANK DCSOUT DCSIN VCC DCSCLK XDCLAT ¼ GSSCLK BLANK ERROR READ VLED ¼ GND VCC DCSCLK XDCLAT VCC IREF RIREF VCC GND Controller for DCDATA Dot Correction DCSCLK with XDCLAT Correction Data ROM (Inside of LED module) Typical Application Circuit (Multiple Daisy-Chained TLC5942s) 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated TLC5942 www.ti.com SBVS096B – OCTOBER 2007 – REVISED OCTOBER 2007 DESCRIPTION, CONTINUED The TLC5942 has two error detection circuits for LED open detection (LOD) and a thermal error flag (TEF). LOD detects a broken or disconnected LED during the display period. TEF indicates an over-temperature condition; when a TEF is set, all output drivers are turned off. When the TEF is cleared, all output drivers are restarted. blank This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION (1) PRODUCT PACKAGE-LEAD TLC5942 HTSSOP-28 PowerPAD™ 5 mm × 5 mm QFN-32 TLC5942 (1) ORDERING NUMBER TRANSPORT MEDIA, QUANTITY TLC5942PWPR Tape and Reel, 2000 TLC5942PWP Tube, 50 TLC5942RHBR Tape and Reel, 3000 TLC5942RHBT Tape and Reel, 250 For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) (2) Over operating free-air temperature range, unless otherwise noted. PARAMETER VCC Supply voltage, VCC IOUT Output current (dc): OUT0 to OUT15 VIN Input voltage range: GSSIN, GSSCLK, XGSLAT, DCSIN, DCSCLK, XDCLAT, BLANK, IREF VOUT Output voltage range TJ(max) Maximum operating junction temperature TSTG Storage temperature range ESD rating (1) (2) 2 TLC5942 UNIT –0.3 to +6.0 V 60 mA –0.3 to VCC + 0.3 V GSSOUT, DCSOUT –0.3 to VCC + 0.3 OUT0 to OUT15 –0.3 to +18 +150 –55 to +150 Human body model (HBM) Charged device model (CDM) V °C 2 kV 500 V Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. All voltage values are with respect to network ground terminal. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TLC5942 TLC5942 www.ti.com SBVS096B – OCTOBER 2007 – REVISED OCTOBER 2007 RECOMMENDED OPERATING CONDITIONS At TA= –40°C to +85°C, unless otherwise noted. TLC5942 PARAMETER TEST CONDITIONS MIN NOM MAX UNIT DC Characteristics: VCC = 3 V to 5.5 V VCC Supply voltage VO Voltage applied to output 3.0 5.5 V 17 VIH High-level input voltage V 0.7 × VCC VCC V VIL Low-level input voltage IOH High-level output current GSSOUT, DCSOUT GND 0.3 × VCC –1 mA IOL Low-level output current GSSOUT, DCSOUT 1 mA IOLC Constant output sink current 50 mA TA Operating free-air temperature –40 +85 °C TJ Operating junction temperature –40 +125 °C OUT0 to OUT15 OUT0 to OUT15 V AC Characteristics: VCC = 3 V to 5.5 V fCLK (dcsclk) Data shift clock frequency DCSCLK 30 MHz fCLK (gssclk) Data shift/grayscale control clock frequency GSSCLK 30 MHz GSSCLK (see Figure 9), DCSCLK (see Figure 10) 10 ns TWH1 XGSLAT, BLANK (see Figure 9), XDCLAT (see Figure 10) 30 ns TSU0 GSSIN–GSSCLK ↑ (see Figure 9), DCSIN–DCSCLK ↑ (see Figure 10) 3 ns TSU1 BLANK ↓– GSSCLK ↑ (see Figure 9) 10 ns TSU2 XGSLAT ↑ – GSSCLK↑ (see Figure 9), XDCLAT ↑ – DCSCLK↑ (see Figure 10) 100 ns TSU3 XGSLAT ↓ – GSSCLK↑ (see Figure 9 and Figure 11) 15 ns TH0 GSSIN–GSSCLK ↑ (see Figure 9), DCSIN–DCSCLK ↑ (see Figure 10) 3 ns XGSLAT ↑ – GSSCLK↑ (see Figure 9), XDCLAT ↑ – DCSCLK↑ (see Figure 10) 30 ns TWH0 / TWL0 Pulse duration Setup time Hold time TH1 DISSIPATION RATINGS PACKAGE DERATING FACTOR ABOVE TA = +25°C TA < +25°C POWER RATING TA = +70°C POWER RATING TA = +85°C POWER RATING HTSSOP-28 with PowerPAD soldered (1) 31.67 mW/°C 3958 mW 2533 mW 2058 mW HTSSOP-28 with PowerPAD not soldered (2) 16.21 mW/°C 2026 mW 1296 mW 1053 mW 27.86 mW/°C 3482 mW 2228 mW 1811 mW QFN-32 (1) (2) (3) (3) With PowerPAD soldered onto copper area on printed circuit board (PCB); 2 oz. copper. For more information, see SLMA002 (available for download at www.ti.com). With PowerPAD not soldered onto copper area on PCB. The package thermal impedance is calculated in accordance with JESD51-5. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TLC5942 3 TLC5942 www.ti.com SBVS096B – OCTOBER 2007 – REVISED OCTOBER 2007 ELECTRICAL CHARACTERISTICS At VCC = 3.0 V to 5.5 V, and TA = –40°C to +85°C. Typical values at VCC = 3.3 V and TA = +25°C, unless otherwise noted. TLC5942 PARAMETER TEST CONDITIONS MIN VOH High-level output voltage IOH = –1 mA at GSSOUT, DCSOUT VOL Low-level output voltage IOL = 1 mA at GSSOUT, DCSOUT Input current VIN = VCC or GND at GSSIN, GSSCLK, XGSLAT, DCSIN, DCSCLK, XDCLAT, BLANK IIN MAX UNIT VCC – 0.4 TYP VCC V 0 0.4 V –1 1 µA ICC1 No data transfer, all OUTn = OFF, DCn = 7Fh, VOUTn = 1 V, RIREF = 10 kΩ 1 3 ICC2 No data transfer, all OUTn = OFF, DCn = 7Fh, VOUTn = 1 V, RIREF = 2 kΩ 4 8 Supply current mA ICC3 Data transfer 30 MHz, all OUTn = ON, DCn = 7Fh, VOUTn = 1 V, RIREF = 2 kΩ 14 30 ICC4 Data transfer 30 MHz, all OUTn = ON, DCn = 7Fh, VOUTn = 1 V, RIREF = 1 kΩ 27 50 49 55 mA 0.1 µA IO(LC) Constant output current All OUTn = ON, DCn = 7Fh, VOUTn = 1 V, VOUTfix = 1 V, RIREF = 1 kΩ IO(LKG) Leakage output current All OUTn = OFF, DCn = 7Fh, VOUTn = 17 V, RIREF = 1 kΩ ΔIO(LC) Constant current error (channel-to-channel) (1) All OUTn = ON, DCn = 7Fh, VOUTn = 1 V, VOUTfix = 1 V, RIREF = 1 kΩ ±1.5 ±5 % ΔIO(LC1) Constant current error (device-to-device) (2) All OUTn = ON, DCn = 7Fh, VOUTn = 1 V, VOUTfix = 1 V, RIREF = 1 kΩ ±3 ±8 % ΔIO(LC2) Line regulation (3) All OUTn = ON, DCn = 7Fh, VOUTn = 1 V, VOUTfix = 1 V, RIREF = 1 kΩ, VCC = 3 V to 5.5 V ±1 ±4 %/V ΔIO(LC3) Load regulation (4) All OUTn = ON, DCn = 7Fh, VOUTn = 1 V to 3 V, VOUTfix = 1 V, RIREF = 1 kΩ ±1 ±3 %/V 43 T(TEF) Thermal error flag threshold Junction temperature +150 +162 +175 °C T(HYS) Thermal error hysteresis Junction temperature (5) +5 +10 +20 °C VLOD LED open detection threshold All OUTn = ON 0.2 0.3 0.4 V VIREF Reference voltage output RIREF = 1 kΩ 1.16 1.20 1.24 V (1) (5) The deviation of each output from the average of OUT0–OUT15 constant current. Deviation is calculated by the formula: D (%) = IOUTn -1 ´ 100 (IOUT0 + IOUT1 + ... + IOUT15) (2) 16 . The deviation of the OUT0–OUT15 constant current average from the ideal constant current value. (IOUT0 + IOUT1 + ... IOUT14 + IOUT15) 16 D (%) = - (Ideal Output Current) ´ 100 Ideal Output Current Deviation is calculated by the following formula: IOUT(IDEAL) = 41 ´ Ideal current is calculated by the formula: D (%/V) = (3) Line regulation is calculated by this equation: 4 Load regulation is calculated by the equation: Not tested; specified by design. (IOUTn at VCC = 5.5 V) - (IOUTn at VCC = 3.0 V) 100 ´ (IOUTn at VCC = 3.0 V) D (%/V) = (4) (5) 1.20 RIREF 5.5 V - 3 V (IOUTn at VOUTn = 3 V) - (IOUTn at VOUTn = 1 V) 100 ´ (IOUTn at VOUTn = 1 V) Submit Documentation Feedback 3V-1V Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TLC5942 TLC5942 www.ti.com SBVS096B – OCTOBER 2007 – REVISED OCTOBER 2007 SWITCHING CHARACTERISTICS At VCC = 3.0 V to 5.5 V, TA = –40°C to +85°C, CL = 15 pF, RL = 82 Ω, RIREF = 1 kΩ, and VLED = 5.0 V. Typical values at VCC = 3.3 V and TA = +25°C, unless otherwise noted. TLC5942 PARAMETER tR0 Rise time tR1 tF0 TEST CONDITIONS MIN 10 GSSOUT (see Figure 9) DCSOUTn (see Figure 10) tF1 OUTn, DCn = 7Fh (see Figure 9) tD0 GSSCLK ↑ – GSSOUT (see Figure 9) DCSCLK ↑ – DCSOUT (see Figure 10) tD1 BLANK ↑ – OUT0 current sink off (see Figure 9) tD2 GSSCLK ↑ – OUT0, 4, 8, 12 (see Figure 9) tD3 MAX 16 OUTn, DCn = 7Fh (see Figure 9) Fall time TYP GSSOUT (see Figure 9) DCSOUT (see Figure 10) ns 30 16 10 UNIT ns 30 25 ns 20 40 ns 5 18 40 ns GSSCLK ↑ – OUT1, 5, 9, 13 (see Figure 9) 20 42 73 ns tD4 GSSCLK ↑ – OUT2, 6, 10, 14 (see Figure 9) 35 66 106 ns tD5 GSSCLK ↑ – OUT3, 7, 11, 15 (see Figure 9) 50 90 140 ns 10 ns Propagation delay time tON_ERR Output on-time error tOUTON – TGSSCLK, GSn = 001h, GSSCLK = 30 MHz (see Figure 9) –20 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TLC5942 5 TLC5942 www.ti.com SBVS096B – OCTOBER 2007 – REVISED OCTOBER 2007 FUNCTIONAL BLOCK DIAGRAM VCC 33rd GSSCLK Signal After BLANK Goes Low LED Open Detection Data Latch (16 LOD) VCC 16 LSB MSB GSSIN Grayscale Shift Register (12 Bits x 16 Channels) GSSOUT 0 191 192 GSSCLK LSB MSB Grayscale Data Latch (12 Bits x 16 Channels) XGSLAT 0 191 LSB MSB DCSIN Dot Correction Shift Register (7 Bits x 16 Channels) 0 DCSOUT 111 112 DCSCLK LSB MSB 192 16 Dot Correction Data Latch (7 Bits x 16 Channels) XDCLAT 111 0 112 Grayscale Counter 12-Bit PWM Timing Control 12 16 Thermal Detection Output Switching Delay (4-Channel Unit) BLANK 16 Constant Current Driver with Dot Correction (16 Channels) Reference Current Control IREF LED Open Detection (LOD, 16 Channels) GND GND ¼ OUT0 6 OUT1 Submit Documentation Feedback OUT14 OUT15 Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TLC5942 TLC5942 www.ti.com SBVS096B – OCTOBER 2007 – REVISED OCTOBER 2007 DEVICE INFORMATION PWP PACKAGE (Top View) DCSIN DCSCLK GND NC NC VCC IREF XDCLAT 32 31 30 29 28 27 26 25 RHB PACKAGE (Top View) GND 1 28 VCC DCSCLK 2 27 IREF DCSIN 3 26 XDCLAT GSSCLK 4 25 DCSOUT GSSCLK 1 24 DCSOUT GSSIN 5 24 GSSOUT GSSIN 2 23 GSSOUT XGSLAT 6 23 BLANK XGSLAT 3 22 BLANK OUT7 7 22 OUT15 OUT7 4 21 OUT15 OUT6 8 21 OUT14 OUT6 5 20 OUT14 OUT5 9 20 OUT13 OUT5 6 19 OUT13 OUT4 10 19 OUT12 OUT4 7 18 OUT12 OUT3 11 18 OUT11 OUT3 8 17 OUT11 OUT2 12 17 OUT10 OUT1 13 16 OUT9 OUT0 14 15 OUT8 11 12 13 14 15 16 OUT0 NC NC OUT8 OUT9 OUT10 OUT2 OUT1 10 Thermal Pad 9 Thermal Pad NC = No connection. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TLC5942 7 TLC5942 www.ti.com SBVS096B – OCTOBER 2007 – REVISED OCTOBER 2007 TERMINAL FUNCTIONS TERMINAL NAME GSSIN PWP RHB I/O 5 2 I Serial data input for grayscale. DESCRIPTION GSSCLK 4 1 I Serial data shift clock for grayscale and reference clock for Grayscale PWM control. Data present on the GSSIN pin are shifted into the Grayscale Shift Register with each rising edge of the GSSCLK pin. Data are shifted into the LSB of the register with each rising edge. The MSB of the register is shifted to the GSSOUT pin with each rising edge. If BLANK is low, then each rising edge of GSSCLK increments the grayscale counter for PWM control. XGSLAT 6 3 I Data in the shift register are moved to the grayscale data latch with a low-to-high transition of this pin. GSSOUT 24 23 O Serial data output for Grayscale/Status information data. This signal is connected to MSB of Grayscale Shift Register. DCSIN 3 32 I Serial data input for Dot Correction. DCSCLK 2 31 I Serial data shift clock for dot correction. Data present on the DCSIN pin are shifted into the dot correction shift register with each rising edge of the DCSCLK pin. Data are shifted into the LSB of the register with each rising edge. The MSB of the register is shifted to the DCSOUT pin with each rising edge. XDCLAT 26 25 I Data in the shift register are moved to the dot correction data latch with a low-to-high transition of this pin. DCSOUT 25 24 O Serial data output for dot correction. This signal is connected to the MSB of the Dot Correction Shift Register. BLANK 23 22 I Blank (all constant current outputs off). When BLANK is high, all constant current outputs (OUT0 through OUT15) are forced off, the Grayscale counter is reset to '0', and the Grayscale PWM timing controller is initialized. When BLANK is low, all constant current outputs are controlled by the Grayscale PWM timing controller. IREF 27 26 I/O Constant current value setting. OUT0 through OUT15 sink constant current is set to desired value by connecting an external resistor between IREF and GND. OUT0 14 11 O Constant current output OUT1 13 10 O Constant current output OUT2 12 9 O Constant current output OUT3 11 8 O Constant current output OUT4 10 7 O Constant current output OUT5 9 6 O Constant current output OUT6 8 5 O Constant current output OUT7 7 4 O Constant current output OUT8 15 14 O Constant current output OUT9 16 15 O Constant current output OUT10 17 16 O Constant current output OUT11 18 17 O Constant current output OUT12 19 18 O Constant current output OUT13 20 19 O Constant current output OUT14 21 20 O Constant current output OUT15 22 21 O Constant current output VCC 28 27 — Power-supply voltage GND 1 30 — Power ground — 12, 13, 28, 29 — No internal connection NC 8 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TLC5942 TLC5942 www.ti.com SBVS096B – OCTOBER 2007 – REVISED OCTOBER 2007 PARAMETER MEASUREMENT INFORMATION PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS VCC VCC INPUT SOUT GND GND Figure 1. GSSIN, GSSCLK, XGSLAT, DCSIN, DCSCLK, XDCLAT, BLANK Figure 2. SOUT OUTn GND Figure 3. OUT0 Through OUT15 TEST CIRCUITS RL VCC VCC OUTn IREF RIREF VCC CL GND VLED (1) GSSOUT/ DCSOUT VCC GND (1) CL includes measurement probe and jig capacitance. Figure 4. Rise Time and Fall Time Test Circuit for OUTn VCC (1) (1) CL CL includes measurement probe and jig capacitance. Figure 5. Rise Time and Fall Time Test Circuit for GSSOUT/DCSOUT OUT0 ¼ VCC IREF OUTn ¼ RIREF GND OUT15 VOUTn VOUTFIX Figure 6. Test Circuit for OUTn Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TLC5942 9 TLC5942 www.ti.com SBVS096B – OCTOBER 2007 – REVISED OCTOBER 2007 TIMING DIAGRAMS TWH0, TWH1, TWL0 VCC INPUT (1) 50% GND TWL TWH TSU0, TSU1, TSU2, TSU3, TH0, TH1 VCC CLOCK INPUT (1) 50% GND TSU TH VCC DATA/CONTROL INPUT (1) 50% GND (1) Input pulse rise and fall time is 1 ns to 3 ns. Figure 7. Input Timing tR0, tR1, tF0, tF1, tD0, tD1, tD2, tD3, tD4, tD5: VCC INPUT (1) 50% GND tD VOH or VOUTnH 90% (2) OUTPUT 50% 10% VOL or VOUTnL tR or tF (1) Input pulse rise and fall time is 1 ns to 3 ns. (2) Input pulse high level is VCC and low level is GND. Figure 8. Output Timing 10 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TLC5942 TLC5942 www.ti.com GSSIN SBVS096B – OCTOBER 2007 – REVISED OCTOBER 2007 GS0 0A GS15 11B GS15 10B GS15 9B GS15 8B GS0 3B GS15 7B GS0 2B TH0 TSU0 GS0 0B GS0 1B GS15 11C GS15 10C GS15 9C TWH0 GS15 8C GS15 7C GS15 6C GS15 5C TGSSCLK TSU2 GSSCLK 1 2 3 4 5 189 190 191 TWL0 192 TH1 TWH1 TSU3 TSU1 XGSLAT TWH1 BLANK Shift Register Data are Transferred to Data Latch Latched Data for Grayscale (Internal) GSSOUT TSU1 Previous Data GS15 11A tD0 GS15 GS15 10A 9A Latest Data tD0 GS15 8A GS15 7A GS15 6A GS0 3A GS0 2A GS0 1A GS0 0A LOD 15 GS15 11B tR0/tF0 tD1 LOD 13 LOD 14 LOD 12 LOD 11 LOD 10 LOD 9 SID Load Timing to GS Data Shift Register Turning off outputs with the BLANK signal (all GS data are greater than 006h): (VOUTnH) OUT 0, 4, 8, 12 OFF ON (VOUTnL) tD2 tF1 OUT OFF 1, 5, 9, 13 ON tD3 OUT OFF 2, 6, 10, 14 ON tD4 OUT OFF 3, 7, 11, 15 ON tD5 tR1 Turning off outputs with GSCLK (all GS data are set to 001h): OUT 0, 4, 8, 12 OFF ON OUT OFF 1, 5, 9, 13 ON OUT OFF 2, 6, 10, 14 ON OUT OFF 3, 7, 11, 15 ON tD2 tD3 tD4 tD5 tOUTON tOUTON tOUTON tOUTON tON_ERR = tOUTON - TGSSCLK Figure 9. Grayscale Data Write Timing Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TLC5942 11 TLC5942 www.ti.com SBVS096B – OCTOBER 2007 – REVISED OCTOBER 2007 DC0 0A DCSIN DC15 6B DC15 5B DC15 3B DC15 4B DC0 3B DC15 2B DC0 2B DC0 0B DC0 1B DC15 6C DC15 5C DC15 4C DC15 3C DC15 2C DC15 1C DC15 0C TH0 TSU0 TSU2 TWH0 DCSCLK 1 2 3 4 5 109 110 111 TWL0 112 TH1 TWH1 XDCLAT Latched Data for Dot Correction (Internal) Previous Data DC15 6A DCSOUT tD0 DC15 DC15 5A 4A DC15 3A DC15 2A DC15 1A DC0 3A DC0 2A DC15 6B DC0 0A DC0 1A Latest Data DC15 5B DC15 4B DC15 3B DC15 2B DC15 1B DC15 0B DC14 6B tR0/tF0 Figure 10. Dot Correction Data Write Timing The SCLK falling edge must be prior to the XGSLAT rising edge in case SID is read. GSSIN GS0 0 GS0 1 191 192 GS15 11A GS15 10A GS15 9A GS15 8A GS15 7A 1 2 3 4 5 TSU2 GS14 9A GS14 8A 14 15 13 GS14 6A GS14 7A 16 GS14 5A 17 GS14 3A GS14 4A 18 19 20 GS0 0A GS0 1A 190 191 192 GSSCLK TH1 TWH1 TSU3 XGSLAT tD0 GSSOUT GS15 11 LOD 15 LOD 14 LOD 13 LOD 12 LOD 3 LOD 2 LOD 1 LOD 0 TEF SID 16 SID 15 SID 14 SID 13 SID 4 SID 3 SID 2 SID 1 SID 0 GS14 6 GS14 5 GS0 1 GS0 0 GS15 11A SID are entered in the GS shift register at the first rising edge of GSSCLK after XGSLAT goes low. The SID readout consists of the saved LOD result at the 33rd GSSCLK rising edge in the previous display period and the TEF data at the rising edge of the first GSCLK after XGSLAT goes low. Figure 11. Status Information Data Read Timing 12 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TLC5942 TLC5942 www.ti.com SBVS096B – OCTOBER 2007 – REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS At VCC = 3.3 V and TA = +25°C, unless otherwise noted. REFERENCE RESISTOR vs OUTPUT CURRENT 10000 POWER DISSIPATION RATE vs FREE-AIR TEMPERATURE 4000 Power Dissipation Rate (mW) Reference Resistor (W) 9840 4920 3280 2460 1968 1640 1406 1230 1093 TLC5942PWP PowerPAD Soldered TLC5942RHB 3000 2000 TLC5942PWP PowerPAD Not Soldered 1000 984 0 1000 0 30 20 10 40 50 -40 -20 Output Current (mA) 60 Figure 13. OUTPUT CURRENT vs OUTPUT VOLTAGE OUTPUT CURRENT vs OUTPUT VOLTAGE 55 53 40 IO = 30 mA 30 IO = 20 mA 20 IO = 10 mA 10 0 2.0 2.5 TA = +85°C 51 50 49 TA = -40°C TA = +25°C 48 46 45 0 3.0 0.5 1.5 1.0 2.0 Output Voltage (V) Output Voltage (V) Figure 14. Figure 15. ΔIOLC vs AMBIENT TEMPERATURE ΔIOLC vs OUTPUT CURRENT 5 IO = 50 mA DCn = 7Fh 3 3 2 2 1 0 3.0 1 0 -1 -1 -2 -2 -3 2.5 TA = +25°C DCn = 7Fh 4 DIOLC (%) DIOLC (%) 1.5 1.0 0.5 52 47 IO = 5 mA 0 4 100 IO = 50 mA DCn = 7Fh 54 IO = 50 mA Output Current (mA) Output Current (mA) Figure 12. IO = 40 mA 5 80 60 40 Free-Air Temperature (°C) TA = +25°C DCn = 7Fh 50 20 0 -3 VCC = 3.3 V -4 VCC = 3.3 V -4 VCC = 5 V -5 VCC = 5 V -5 -40 -20 0 20 40 60 80 100 0 10 20 30 Ambient Temperature (°C) Output Current (mA) Figure 16. Figure 17. 40 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TLC5942 50 13 TLC5942 www.ti.com SBVS096B – OCTOBER 2007 – REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (continued) At VCC = 3.3 V and TA = +25°C, unless otherwise noted. DOT CORRECTION LINEARITY DOT CORRECTION LINEARITY 60 60 TA = +25°C IOLCMax = 50 mA 50 IOLCMax = 50 mA Output Current (mA) Output Current (mA) 50 40 30 20 IOLCMax = 30 mA 10 40 30 20 TA = -40°C TA = +25°C 10 IOLCMax = 5 mA TA = +85°C 0 0 0 20 40 60 80 100 120 0 140 20 40 60 80 100 Dot Correction Data (dec) Dot Correction Data (dec) Figure 18. Figure 19. 120 140 CONSTANT CURRENT OUTPUT VOLTAGE WAVEFORM CH1-GSCLK (30 MHz) CH1 (2 V/div) CH2 (2 V/div) CH3 (2 V/div) CH2-OUT0 (GSData = 0x001h) IOLCMax = 50 mA, DCn = 7Fh TA = +25°C,RL = 82 W CL = 15 pF, VLED = 5 V CH3-OUT15 (GSData = 0x001h) Time (25 ns/div) Figure 20. 14 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TLC5942 TLC5942 www.ti.com SBVS096B – OCTOBER 2007 – REVISED OCTOBER 2007 DETAILED DESCRIPTION Setting for the Maximum Constant Sink Current Value On the TLC5942, the maximum constant current sink value for each channel, IOLCMax, is determined by an external resistor, RIREF, placed between the IREF and GND pins. The RIREF resistor value is calculated with Equation 1: RIREF (kW) = VIREF (V) ´ 41 IOLCMax (mA) (1) Where: VIREF = the internal reference voltage on the IREF pin (typically 1.20 V) IOLCMax is the largest current for all outputs. Each output sinks the IOLCMax current when it is turned on and its dot correction is set to the maximum value of 7Fh (127d). The sink current for each output can be reduced by lowering the respective output dot correction value. RIREF must be between 984 Ω (typ) and 9.84 kΩ (typ) in order to keep IOLCMax between 5 mA and 50 mA. The output may become unstable when IOLCMax is set lower than 5 mA. However, output currents lower than 5 mA can be achieved by setting IOLCMax to 5 mA or higher, and then using dot correction to lower the output current. Figure 12 in the Typical Characteristics and Table 1 show the characteristics of the constant sink current versus external resistor, RIREF. Table 1. Maximum Constant Current Output versus External Resistor Value IOLCMax (mA, typical) RIREF (Ω) 50 984 45 1093 40 1230 35 1406 30 1640 25 1968 20 2460 15 3280 10 4920 5 9840 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TLC5942 15 TLC5942 www.ti.com SBVS096B – OCTOBER 2007 – REVISED OCTOBER 2007 Dot Correction (DC) Function The TLC5942 is able to individually adjust the output current of each channel (OUT0 to OUT15). This function is called dot correction (DC). The DC function allows users to individually adjust the brightness and color deviations of LEDs connected to the outputs OUT0 to OUT15. Each respective channel output current can be adjusted in 128 steps from 0% to 100% of the maximum output current, IOLCMax. The dot correction data are entered into the TLC5942 via the serial interface. Equation 2 determines the sink current for each output (OUTn): IOUTn (mA) = IOLCMax (mA) ´ ( DCn ) 127d (2) Where: IOLCMax = the maximum channel current for each channel determined by RIREF DCn = the programmed dot correction value for OUTn (DCn = 0 to 127d) When the IC is powered on, the data in the Dot Correction Shift Register and data latch are not set to any default values. Therefore, DC data must be written to the DC latch before turning on the constant current output. Table 2 summarizes the DC data versus current ratio and set current value. Table 2. DC Data versus Current Ratio and Set Current Value 16 DC DATA (Binary) DC DATA (Decimal) DC DATA (Hex) SET CURRENT RATIO TO MAX CURRENT (%) OUTPUT CURRENT (mA, typical) AT IOLCMax = 50 mA OUTPUT CURRENT (mA, typical) AT IOLCMax = 5 mA 000 0000 0 00 0.0 0.0 0.00 000 0001 1 01 0.8 0.4 0.04 000 0010 2 02 1.6 0.8 0.08 ... ... ... ... ... ... ... ... ... ... ... ... 111 1101 125 7D 98.4 49.2 4.92 111 1110 126 7E 99.2 49.6 4.96 111 1111 127 7F 100.0 50.0 5.00 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TLC5942 TLC5942 www.ti.com SBVS096B – OCTOBER 2007 – REVISED OCTOBER 2007 Grayscale (GS) Function (PWM Operation) The pulse width modulation (PWM) operation is controlled by a 12-bit grayscale counter that is clocked on each rising edge of the grayscale reference clock, GSSCLK. The counter is reset to zero when the BLANK signal is set high. The counter value is held at zero while BLANK is high, even if the GSSCLK input toggles high and low. After the falling edge of BLANK, the counter increments with each rising edge of GSSCLK. Any constant current sink output (OUT0 through OUT15) with a nonzero value in its corresponding grayscale latch starts to sink current after the first rising edge of GSSCLK following a high-to-low transition of BLANK. The internal counter keeps track of the number of GSSCLK pulses. Each output channel stays on as long as the internal counter is equal to or less than the respective output GSSCLK. Each channel turns off at the rising edge of GSSCLK when the grayscale counter value is larger than the grayscale latch value. For example, an output that has a grayscale latch value of '1' turns on at the first rising edge of GSSCLK after BLANK goes low. It turns off at the second rising edge of GSSCLK. Figure 21 shows the PWM timing diagram. BLANK 2049 2048 2050 1 2 3 4 GSSCLK 4095 4094 4096 ¼ (VOUTnH) ¼ GSSCLK counter starts to count GSSCLK after BLANK goes low. OFF OUTn Drivers do not turn on when grayscale data are zero. ON (GSDATA = 0d) T = GSSCLK ´ 1 (VOUTnH) OFF OUTn ON (GSDATA = 1d) OFF OUTn ON (GSDATA = 2d) (VOUTnL) (VOUTnH) T = GSSCLK ´ 2 (VOUTnL) (VOUTnH) T = GSSCLK ´ 3 OFF (VOUTnL) ¼ (VOUTnH) ON (GSDATA = 2047d) (VOUTnL) (VOUTnH) OFF OUTn ON (GSDATA = 2048d) OFF OUTn ON (GSDATA = 4093d) (VOUTnL) (VOUTnH) (VOUTnH) OUTn OFF ON (GSDATA = 4095d) T = GSSCLK ´ 4093 (VOUTnL) OFF ON (GSDATA = 4094d) ¼ ¼ OFF T = GSSCLK ´ 2049 ¼ ON (GSDATA = 2049d) T = GSSCLK ´ 2048 (VOUTnL) (VOUTnH) OUTn T = GSSCLK ´ 2047 OFF OUTn OUTn ¼ ¼ OUTn ON (GSDATA = 3d) T = GSSCLK ´ 4094 (VOUTnL) (VOUTnH) T = GSSCLK ´ 4095 (VOUTnL) OUTn turns on at first rising edge of GSSCLK after BLANK goes low except when grayscale data are zero. OUTn does not turn on again until BLANK goes high to reset the grayscale clock and then goes low to enable all OUTn. Figure 21. PWM Operation Timing Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TLC5942 17 TLC5942 www.ti.com SBVS096B – OCTOBER 2007 – REVISED OCTOBER 2007 When the IC is powered on, the data in the Grayscale Shift Register and latch are not set to any default value. Therefore, Grayscale data must be written to the Grayscale latch before turning the constant current output on. Additionally, BLANK should be high when the device turns on, to prevent the outputs from turning on before the proper grayscale and dot correction values can be written. All constant current outputs are always off when BLANK is high. Equation 3 determines each output (OUTn) on time (tOUTON): tOUTON (ns) = TGSSCLK (ns) ´ GSn (3) Where: TGSSCLK = the period of GSSCLK GSn = the programmed grayscale value for OUTn (GSn = 0 to 4095d) If there are any unconnected output LED lamps (including connection failures or short-circuits), the grayscale data corresponding to the unconnected output should be set to '0' before turning on the LEDs. Otherwise, the supply current (IVCC) increases while the LEDs are on. If GS data changes during a GS period because XLAT goes high, and latches new GS data, the internal data latch registers are immediately updated. This action can cause the outputs to turn on or off unexpectedly. For proper operation, GS data should only be latched into the IC at the end of a GS period when BLANK is high. Table 3 summarizes the GS data versus OUTn on duty and on time. Table 3. GS Data versus OUTn On Duty and OUTn On Time 18 GS DATA (Binary) GS DATA (Decimal) GS DATA (Hex) OUTn ON DUTY (%) OUTn ON TIME (ns, typical) AT 30 MHz GSSCLK 0000 0000 0000 0 000 0.00 0 0000 0000 0001 1 001 0.02 33 0000 0000 0010 2 002 0.05 67 0000 0000 0011 3 003 0.07 100 ... ... ... ... ... ... ... ... ... ... 0111 1111 1111 2047 7FF 49.99 68263 1000 0000 0000 2048 800 50.01 68267 1000 0000 0001 2049 801 50.04 68300 ... ... ... ... ... ... ... ... ... ... 1111 1111 1101 4093 FFD 99.95 136433 1111 1111 1110 4094 FFE 99.98 135467 1111 1111 1111 4095 FFF 100.00 136500 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TLC5942 TLC5942 www.ti.com SBVS096B – OCTOBER 2007 – REVISED OCTOBER 2007 Grayscale Shift Register and Data Latch The Grayscale (GS) Shift Registers and data latches are each 192 bits in length, and are used to set the PWM timing for each constant current driver. See Table 3 for the ON time duty of each GS data bit. Figure 22 shows the shift register and latch configuration. Refer to Figure 9 for the timing diagram for writing data into the GS shift register and latch. The driver on time is set by the data in the GS data latch. GS data present on the GSSIN pin are clocked into the GS Shift Register with each rising edge of the GSSCLK pin. Data are shifted in MSB first. Data are latched from the shift register into the GS data latch with a rising edge on the XGSLAT pin. When the IC is powered on, the data in Grayscale Shift Register and data latch are not set to any default value. Therefore, grayscale data must be written to the GS latch before turning on the constant current output. Also, BLANK should be high when powered on because the constant current may also turn on. All constant current outputs are off when BLANK is high. The Status Information Data (SID) byte is overwritten on the most significant 17 bits of the Grayscale Shift Register at the rising edge of the first GSSCLK after XGSLAT goes low. Grayscale Shift Register (12 Bits ´ 16 Channels) GS Data for OUT15 MSB 191 GSSOUT OUT15-Bit11 (LOD-OUT15) ¼ GS Data for OUT14 180 179 OUT15-Bit0 (LOD-OUT4) OUT14-Bit11 (LOD-OUT3) ¼ GS Data for OUT1 175 ¼ OUT14-Bit7 (TEF) ¼ GS Data for OUT0 LSB 0 7 6 OUT1-Bit0 OUT0-Bit11 ¼ OUT0-Bit0 GSSIN GSSCLK SID Data are Overwritten Between Bits 191 and 175 ¼ ¼ GS Data for OUT15 GS Data for OUT14 MSB 191 OUT15-Bit11 ¼ 180 179 OUT15-Bit0 OUT14-Bit11 ¼ Grayscale Data Latch (12 Bits ´ 16 Channels) ¼ ¼ ¼ GS Data for OUT1 OUT14-Bit7 ¼ GS Data for OUT0 12 11 OUT1-Bit0 OUT0-Bit11 LSB 0 ¼ OUT0-Bit0 XGSLAT 192 Bits To PWM Timing Control Block Figure 22. Grayscale Shift Register and Data Latch Configuration Dot Correction Shift Register and Data Latch The Dot Correction (DC) Shift Registers and latches are each 112 bits in length and are used to individually adjust the constant current values for each constant current driver. Each channel can be adjusted from 0% to 100% of the maximum LED current with 7-bit resolution. Table 2 describes the percentage of the maximum current for each dot correction data. See Figure 23 for the Dot Correction Shift Register and data latch configuration. Figure 10 illustrates the timing chart for writing data into the DC Shift Registers and latches. Each channel LED current is dot-corrected by the percentage corresponding to the data in its DC data latch. DC data present on the DCSIN pin are clocked into the DC Shift Register with each rising edge of the DCSCLK pin. Data are shifted in MSB first. The data are latched from the shift register into the DC data latch with a rising edge on the XDCLAT pin. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TLC5942 19 TLC5942 www.ti.com SBVS096B – OCTOBER 2007 – REVISED OCTOBER 2007 Dot Correction Shift Register (7 Bits ´ 16 Channels) DC Data for OUT15 MSB 111 DCSOUT OUT15-Bit6 ¼ DC Data for OUT14 105 104 OUT15-Bit0 OUT14-Bit6 ¼ DC Data for OUT1 ¼ DC Data for OUT0 LSB 0 7 6 OUT1-Bit0 OUT0-Bit6 ¼ OUT0-Bit0 DCSIN DCSCLK ¼ ¼ DC Data for OUT15 MSB 111 OUT15-Bit6 ¼ DC Data for OUT14 105 104 OUT15-Bit0 OUT14-Bit6 ¼ ¼ DC Data for OUT1 ¼ Dot Correction Data Latch (7 Bits ´ 16 Channels) DC Data for OUT0 LSB 0 7 6 OUT1-Bit0 OUT0-Bit6 ¼ OUT0-Bit0 XDCLAT 112 Bits To Constant Current Driver Block Figure 23. Dot Correction Shift Register and Latch Configuration When the IC is powered on, the data in the Dot Correction Shift Register and data latch are not set to a specific default value. Therefore, dot correction data must be written to the DC latch before turning on the constant current output. Status Information Data (SID) Status information data (SID) are 17-bit, read-only data. Both the LED open detection (LOD) error and the thermal error flag (TEF) are shifted out of the GSSOUT pin with each rising edge of the grayscale clock, GSSCLK. The 16 LOD bits for each channel and the TEF bit are written into the 17 most significant bits of the Grayscale Shift Register at the rising edge of the first GSSCLK after XGSLAT goes low. As a result, the previous data in the 17 most significant bits are lost at the same time. No data are loaded into the other 175 bits. Figure 24 shows the bit assignments. Figure 11 illustrates the read timing for the status information data. Status Information Data (SID) Configuration LOD Data of OUT15 to OUT0 (16 Bits) MSB 16 OUT15 LOD Data TEF (1 Bit) 15 ¼ 2 1 OUT14 LOD Data ¼ OUT1 LOD Data OUT0 LOD Data LSB 0 TEF Data The 16 LOD bits for each channel and the TEF bit overwrite the most significant 17 bits of the grayscale shift register at the rising edge of the first GSSCLK after XGSLAT goes low. ¼ GS Data for OUT15 MSB 191 GSSOUT OUT15-Bit11 (LOD-OUT15) ¼ GS Data for OUT14 180 179 OUT15-Bit0 (LOD-OUT4) OUT14-Bit11 (LOD-OUT3) ¼ GS Data for OUT1 175 ¼ OUT14-Bit7 (TEF) ¼ GS Data for OUT0 12 11 OUT1-Bit0 OUT0-Bit11 LSB 0 ¼ OUT0-Bit0 GSSIN GSSCLK Grayscale Shift Register (12 Bits ´ 16 Channels) Figure 24. Status Information Data Configuration 20 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TLC5942 TLC5942 www.ti.com SBVS096B – OCTOBER 2007 – REVISED OCTOBER 2007 The LOD data are updated at the rising edge of the 33rd GSSCLK pulse after BLANK goes low; the LOD data are retained until the next 33rd GSSCLK. LOD data are only checked for outputs that are turned on during the rising edge of the 33rd GSSCLK pulse. A '1' in an LOD bit indicates an open LED condition for the corresponding channel. A '0' indicates normal operation. It is possible for LOD data to show a '0' even if the LED is open when the grayscale data are less than 20h (32d). Therefore, the GS data must be set to 21h (33d) or higher to get updated LOD data beyond 20h (32d). The TEF bit indicates that the IC temperature is too high. The flag also indicates that the IC has turned off all drivers to avoid damage by overheating the device. A '1' in the TEF bit means that the IC temperature has exceeded the detect temperature threshold (TTEF) and the driver is turned off. A '0' in the TEF bit indicates normal operating temperature conditions. The IC automatically turns the drivers back on when the IC temperature decreases to less than TTEF-THYS. When the IC is powered on, LOD data do not show correct values. Therefore, LOD data must be read from the 33rd GSSCLK pulse input after BLANK goes low. Table 4 shows a truth table for both LOD and TEF. Table 4. LOD and TEF Truth Table CONDITION SID DATA LED OPEN DETECTION (LODn) THERMAL ERROR FLAG (TEF) 0 LED is connected (VOUTn > VIOD) Device temperature is low (temp ≤ TTEF–THYS) 1 LED is open or shorted to GND (VOUTn ≤ VIOD) Device temperature is high (temp > TTEF) Continuous Base LED Open Detection The LED Open Detection (LOD) circuit checks the voltage of each active (that is, on) constant current sink output (OUT0 through OUT15) at the rising edge of the 33rd GSSCLK after the falling edge of BLANK to detect open and short LEDs to GND. The channels corresponding to the LOD bit in the Status Information Data register (SID) are set to a '1' if the voltage of the OUTn pin is less than the LED open detection threshold (VLOD = 0.3 VTYP). This status information can be read from the GSSOUT pin. No special test sequence is required for LED open detection. The LOD function automatically checks for open and short LEDs to GND during each grayscale PWM cycle. The SID information of the LOD is latched into the LED Open Detection data latch and does not change until the rising edge of the 33rd GSSCLK pulse following the next falling edge of BLANK. To eliminate false detection of open LEDs, the LED driver design must ensure that the TLC5942 output voltage is greater than VLOD when the outputs are on. The GS data must be 21h (33d) or more to get the LOD result. BLANK 1 2 3 4 ¼ 28 29 30 31 32 33 34 35 36 37 38 39 ¼ 4086 4088 4090 4093 4094 4096 4085 4087 4089 4091 4093 4095 GSSCLK If the OUTn voltage (VOUT) is less than VLOD (0.3 V, typ) at the rising edge of the 33rd GSSCLK after the falling edge of BLANK, the LOD sets the SID bit corresponding to the output channel in which LED is open or shorted to GND equal to ‘1’. OUTn OFF OUTn OUTn ON VOUTn This LED Open Detection (LOD) data are kept until the next 33rd rising edge of GSSCLK after BLANK goes low. GND Internal SID Register Value Old LED Open Detection Data New LED Open Detection Data Figure 25. LED Open Detection (LOD) Timing Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TLC5942 21 TLC5942 www.ti.com SBVS096B – OCTOBER 2007 – REVISED OCTOBER 2007 Thermal Shutdown and Thermal Error Flag The Thermal Shutdown (TSD) function turns off all of the constant current outputs on the IC when the junction temperature (TJ) exceeds the threshold (TTEF = +162°C, typ) and sets the thermal error flag (TEF) to '1'. All outputs are latched off when TEF is set to '1' and remain off until the next grayscale cycle after the junction temperature drops below (T(TEF) – T(HYS)). TEF is set to '0' once the junction temperature drops below (T(TEF) – T(HYS)), but the outputs do not turn on until the first GSSCLK after BLANK goes low while TEF is set to '0'. BLANK 4094 4096 4093 4095 1 2 3 4 1 2 3 GSSCLK IC Junction Temperature (TJ) TJ < T(TEF) (Normal Temperature) TJ ³ T(TEF) TJ ³ T(TEF) TJ < T(TEF) - T(HYS) (Normal Temperature) (High Temp) (High Temp) '1' '1' TEF (Internal) '0' '0' OFF OUTn ON If TJ ³ T(TEF) at this time, then OUTn is not turned on. Figure 26. TEF/TSD Timing Noise Reduction Large surge currents may flow through the IC and the board on which the device is mounted if all 16 LED channels turn on simultaneously at the start of each grayscale cycle. These large current surges could introduce detrimental noise and electromagnetic interference (EMI) into other circuits. The TLC5942 turns on the LED channels in a series delay, to provide a current soft-start feature. The output current sinks are grouped into four groups of four channels each. The first group is OUT0, 4, 8, 12; the second group is OUT1, 5, 9, 13; the third group is OUT2, 6, 10, 14; and the fourth group is OUT3, 7, 11, 15. Each group turns on sequentially with a small delay between groups; see Figure 9. Both turn-on and turn-off are delayed. POWER DISSIPATION CALCULATION The device power dissipation must be below the power dissipation rate of the device package illustrated in Figure 13 to ensure correct operation. Equation 4 calculates the power dissipation of the device: PD = (VCC ´ ICC) + VOUT ´ IMAX ´ N ´ DCn ´ dPWM 127d (4) Where: VCC = device supply voltage ICC = device supply current VOUT = OUTn voltage when driving LED current IMAX = LED current adjusted by R(IREF) resistor DCn = maximum dot correction value for OUTn (decimal) N = number of OUTn driving LED at the same time dPWM = duty ratio defined by BLANK pin or GS PWM value 22 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TLC5942 TLC5942 www.ti.com SBVS096B – OCTOBER 2007 – REVISED OCTOBER 2007 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (October 2007) to Revision B ............................................................................................... Page • Changed Figure 11. ............................................................................................................................................................. 12 Changes from Original (October 2007) to Revision A .................................................................................................... Page • Changed release date for QFN package ............................................................................................................................... 2 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TLC5942 23 PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TLC5942PWP ACTIVE HTSSOP PWP 28 TLC5942PWPR ACTIVE HTSSOP PWP TLC5942RHBR ACTIVE QFN TLC5942RHBT ACTIVE QFN 50 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR RHB 32 250 CU NIPDAU Level-2-260C-1 YEAR Green (RoHS & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 30-Oct-2007 TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLC5942PWPR PWP 28 SITE 60 330 16 6.9 10.2 1.8 12 16 Q1 TLC5942RHBR RHB 32 SITE 41 330 12 5.3 5.3 1.5 8 12 Q2 TLC5942RHBT RHB 32 SITE 41 180 12 5.3 5.3 1.5 8 12 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 30-Oct-2007 Device Package Pins Site Length (mm) Width (mm) Height (mm) TLC5942PWPR PWP 28 SITE 60 346.0 346.0 33.0 TLC5942RHBR RHB 32 SITE 41 346.0 346.0 29.0 TLC5942RHBT RHB 32 SITE 41 190.0 212.7 31.75 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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