CY24212 PRELIMINARY MediaClock™ MPEG Clock Generator with VCXO Features Benefits • Integrated phase-locked loop (PLL) Highest-performance PLL tailored for multimedia applications • Low jitter, high-accuracy outputs Meets critical timing requirements in complex system designs • VCXO with analog adjust Large ±150-ppm range, better linearity • 3.3V operation Enables application compatibility Part Number Outputs Input Frequency Range CY24212-1 1 13.5 MHz/27 MHz (selectable) 27 MHz Output Frequencies CY24212-2 2 13.5 MHz/27 MHz (selectable) Two copies of 27 MHz CY24212-3 2 27 MHz 27 MHz/27.027 MHz (-1 ppm) CY24212-5 2 27 MHz 27 MHz/27.027 MHz (0 ppm) Logic Block Diagram OUTPUT DIVIDERS XIN OSC Q XOUT Φ CLKA (27 MHz) VCO 27 MHz (-2) 27/27.027 MHz (-3) P VCXO PLL FSEL VDD VSS Pin Configurations CY24212-1 8-pin SOIC CY24212-3,-5 8-pin SOIC CY24212-2 8-pin SOIC XIN 1 8 XOUT VDD VCXO 2 7 VSS 3 6 VSS 4 5 FSEL CLKA 27 MHz XIN 1 8 XOUT VDD VCXO 2 7 CLKB 27 MHz 3 6 VSS 4 5 FSEL CLKA 27 MHz XIN 1 VDD VCXO 2 8 7 3 6 VSS 4 5 XOUT CLKB (27/27.027 MHz) FSEL CLKA 27 MHz Table 1. CY24212 (-1, -2) Frequency Select Option FSEL Reference CLKA/CLKB 0 13.5 MHz 27 MHz 1 27 MHz 27 MHz Table 2. CY24212 (-3, -5) Frequency Select Option FSEL Reference 0 27 MHz 27 MHz 27 MHz 1 27 MHz 27 MHz 27.027 MHz Cypress Semiconductor Corporation Document #: 38-07402 Rev. *B CLKA • 3901 North First Street CLKB • San Jose, CA 95134 • 408-943-2600 Revised February 18, 2003 CY24212 PRELIMINARY Pin Description Name Pin Number Description XIN 1 Reference Input. VDD 2 Voltage Supply. VCXO 3 Input Analog Control for VCXO. VSS 4 Ground. CLKA 5 27-MHz Clock Output. FSEL (-1,-2) 6 Input Frequency Select, Weak Internal Pull-up. FSEL = 0, XIN = 13.5 MHz FSEL = 1, XIN = 27 MHz FSEL (-3,-5) 6 Output Frequency Select, Weak Internal Pull-up. FSEL = 0, CLKA = 27 MHz, CLKB = 27 MHz FSEL = 1, CLKA = 27 MHz, CLKB = 27.027 MHz VSS (-1) 7 Ground. CLKB (-2) 7 27 MHz. CLKB (-3,-5) 7 27 MHz/27.027 MHz. 8 Reference Output. XOUT [1] Pullable Crystal Specifications Parameter CRload Name Min Crystal Load Capacitance Typ Max 14 Unit pF C0/C1 240 ESR Equivalent Series Resistance To Operating Temperature 35 0 50 Ω 70 °C Crystal Accuracy Crystal Accuracy + 20 ppm TTs Stability over Temperature and Aging + 50 ppm Absolute Maximum Conditions Parameter Description Min Max Unit VDD Supply Voltage –0.5 7.0 V TS Storage Temperature[2] –65 125 °C 125 °C VSS – 0.3 VDD + 0.3 V Junction Temperature TJ Digital Inputs Electrostatic Discharge 2 kV Recommended Operating Conditions Parameter Description VDD Operating Voltage TA Ambient Temperature CLOAD Max. Load Capacitance fREF Reference Frequency Min Typ Max 3.135 3.3 3.465 V 70 °C 0 13.5 Unit 15 pF 27 MHz Notes: 1. Float XOUT if XIN is externally driven. 2. Rated for ten years. Document #: 38-07402 Rev. *B Page 2 of 6 CY24212 PRELIMINARY DC Electrical Specifications Min Typ IOH Parameter Output High Current Name VOH = VDD – 0.5, VDD = 3.3V (source) Description 12 24 VOL = 0.5, VDD = 3.3V (sink) 12 24 Max Unit mA IOL Output Low Current CIN Input Capacitance mA IIH Input High Current VIH = VDD – 5 10 µA IIL Input Low Current VIL = 0V – – 50 µA 7 f∆XO VCXO Pullability Range VVCXO VCXO Input Range IDD Supply Current Sum of Core and Output Current VIH Input High Voltage CMOS levels, 70% of VDD VIL Input Low Voltage CMOS levels, 30% of VDD RUP Pull-up resistor on inputs VDD = 3.14 to 3.47V, measured VIN = 0V pF +150 ppm 0 VDD 35 0.7 V mA VDD 100 0.3 VDD 150 kΩ AC Electrical Specifications (VDD = 3.3V) Parameter[3] Name Description Min Typ Max 55 Unit DC Output Duty Cycle Duty Cycle is defined in Figure 1, 50% of VDD 45 50 ER Rising Edge Rate Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF. See Figure 2. 0.8 1.4 V/ns EF Falling Edge Rate Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF. See Figure 2. 0.8 1.4 V/ns t9 Clock Jitter Peak-to-peak period jitter 300 ps t10 PLL Lock Time 3 % ms Test and Measurement Set-up VDDs Outputs 0.1 µF DUT CLOAD GND Note: 3. Not 100% tested. Document #: 38-07402 Rev. *B Page 3 of 6 CY24212 PRELIMINARY Voltage and Timing Definitions t1 t2 VDD 50% of VDD Clock Output 0V Figure 1. Duty Cycle Definition t4 t3 V DD 80% of V DD 20% of VDD Clock Output 0V Figure 2. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4 Ordering Information Ordering Code Package Name Package Type Operating Range Operating Voltage CY24212SC-1 S8 8-Pin SOIC Commercial 3.3V CY24212SC-1T S8 8-Pin SOIC -Tape and Reel Commercial 3.3V CY24212SC-2 S8 8-Pin SOIC Commercial 3.3V CY24212SC-2T S8 8-Pin SOIC -Tape and Reel Commercial 3.3V CY24212SC-3 S8 8-Pin SOIC Commercial 3.3V CY24212SC-3T S8 8-Pin SOIC -Tape and Reel Commercial 3.3V CY24212SC-5 S8 8-Pin SOIC Commercial 3.3V CY24212SC-5T S8 8-Pin SOIC -Tape and Reel Commercial 3.3V Document #: 38-07402 Rev. *B Page 4 of 6 CY24212 PRELIMINARY Package Drawing and Dimensions 8-Lead (150-Mil) SOIC S8 51-85066-*A MediaClock is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07402 Rev. *B Page 5 of 6 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY CY24212 Document History Page Document Title: CY24212 MediaClock™ MPEG Clock Generator with VCXO Document Number: 38-07402 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 117089 09/09/02 CKN New Data Sheet *A 120888 12/06/02 CKN Added -3 *B 123064 02/19/03 CKN Added -5 Document #: 38-07402 Rev. *B Page 6 of 6