74F161A, 74F163A
Synchronous Presettable Binary Counter
tm
Features
General Description
■ Synchronous counting and loading
The 74F161A and 74F163A are high-speed synchronous modulo-16 binary counters. They are synchronously presettable for application in programmable
dividers and have two types of Count Enable inputs plus
a Terminal Count output for versatility in forming
synchronous multi-stage counters. The 74F161A has an
asynchronous Master-Reset input that overrides all other
inputs and forces the outputs LOW. The 74F163A has a
Synchronous Reset input that overrides counting and
parallel loading and allows the outputs to be simultaneously reset on the rising edge of the clock. The
74F161A and 74F163A are high-speed versions of the
74F161 and 74F163.
■ High-speed synchronous expansion
■ Typical count frequency of 120MHz
Ordering Information
Order
Number
Package
Number
Package Description
74F161ASC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74F161ASJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F161APC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
74F163ASC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74F163ASJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F163APC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Connection Diagrams
74F161A
©1988 Fairchild Semiconductor Corporation
74F161A, 74F163A Rev. 1.0.2
74F163A
www.fairchildsemi.com
74F161A, 74F163A Synchronous Presettable Binary Counter
April 2007
74F161A, 74F163A Synchronous Presettable Binary Counter
Logic Symbols
74F161A
74F163A
IEEE/IEC
IEEE/IEC
74F161A
74F163A
Unit Loading/Fan Out
Pin Names
Description
U.L.
HIGH / LOW
Input IIH / IIL
Output IOH / IOL
CEP
Count Enable Parallel Input
1.0 / 1.0
20µA / -0.6mA
CET
Count Enable Trickle Input
1.0 / 2.0
20µA / -1.2mA
CP
Clock Pulse Input (Active Rising Edge)
1.0 / 1.0
20µA / -0.6 mA
MR (74F161A)
Asynchronous Master Reset Input (Active LOW)
1.0 / 1.0
20µA / -0.6 mA
SR (74F163A)
Synchronous Reset Input (Active LOW)
1.0 / 2.0
20µA / -1.2 mA
P0–P3
Parallel Data Inputs
1.0 / 1.0
20µA / -0.6 mA
PE
Parallel Enable Input (Active LOW)
1.0 / 2.0
20µA / -1.2mA
Q0–Q3
Flip-Flop Outputs
50 / 33.3
-1mA / 20mA
TC
Terminal Count Output
50 / 33.3
-1mA / 20mA
©1988 Fairchild Semiconductor Corporation
74F161A, 74F163A Rev. 1.0.2
www.fairchildsemi.com
2
Logic Equations:
The 74F161A and 74F163A count in modulo-16 binary
sequence. From state 15 (HHHH) they increment to
state 0 (LLLL). The clock inputs of all flip-flops are driven
in parallel through a clock buffer. Thus all changes of the
Q outputs (except due to Master Reset of the 74F161A)
occur as a result of, and synchronous with, the LOW-toHIGH transition of the CP input signal. The circuits have
four fundamental modes of operation, in order of precedence: asynchronous reset (74F161A), synchronous
reset (74F163A), parallel load, count-up and hold. Five
control inputs—Master Reset (MR, 74F161A), Synchronous Reset (SR, 74F163A), Parallel Enable (PE), Count
Enable Parallel (CEP) and Count Enable Trickle (CET)—
determine the mode of operation, as shown in the Mode
Select Table. A LOW signal on MR overrides all other
inputs and asynchronously forces all outputs LOW. A
LOW signal on SR overrides counting and parallel loading and allows all outputs to go LOW on the next rising
edge of CP. A LOW signal on PE overrides counting and
allows information on the Parallel Data (Pn) inputs to be
loaded into the flip-flops on the next rising edge of CP.
With PE and MR ('F161A) or SR (74F163A) HIGH, CEP
and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits
counting.
Count Enable = CEP • CET • PE
TC = Q0 • Q1 • Q2 • Q3 • CET
Mode Select Table
Action on the Rising
Clock Edge ( )
SR(1)
PE
L
X
X
X
Reset (Clear)
H
L
X
X
Load (Pn→Qn)
H
H
H
H
Count (Increment)
H
H
L
X
No Change (Hold)
H
H
X
L
No Change (Hold)
CET CEP
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Note:
1. For 74F163A only
State Diagram
The 74F161A and 74F163A use D-type edge triggered
flip-flops and changing the SR, PE, CEP and CET inputs
when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with
respect to the rising edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is
HIGH and the counter is in state 15. To implement synchronous multi-stage counters, the TC outputs can be
used with the CEP and CET inputs in two different ways.
Please refer to the 74F568 data sheet. The TC output is
subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a
clock or asynchronous reset for flip-flops, counters or
registers.
©1988 Fairchild Semiconductor Corporation
74F161A, 74F163A Rev. 1.0.2
www.fairchildsemi.com
3
74F161A, 74F163A Synchronous Presettable Binary Counter
Functional Description
74F161A, 74F163A Synchronous Presettable Binary Counter
Figure 1.
Block Diagram
©1988 Fairchild Semiconductor Corporation
74F161A, 74F163A Rev. 1.0.2
www.fairchildsemi.com
4
Symbol
TSTG
Parameter
Rating
Storage Temperature
–65°C to +150°C
TA
Ambient Temperature Under Bias
–55°C to +125°C
TJ
Junction Temperature Under Bias
–55°C to +150°C
VCC
VCC Pin Potential to Ground Pin
–0.5V to +7.0V
VIN
Input Voltage(2)
–0.5V to +7.0V
IIN
Input Current(2)
–30mA to +5.0mA
VO
Voltage Applied to Output in HIGH State (with VCC = 0V)
Standard Output
–0.5V to VCC
3-STATE Output
–0.5V to +5.5V
Current Applied to Output in LOW State (Max.)
twice the rated IOL (mA)
ESD Last Passing Voltage (Min.)
4000V
Note:
2. Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
TA
VCC
Parameter
Rating
Free Air Ambient Temperature
0°C to +70°C
Supply Voltage
©1988 Fairchild Semiconductor Corporation
74F161A, 74F163A Rev. 1.0.2
+4.5V to +5.5V
www.fairchildsemi.com
5
74F161A, 74F163A Synchronous Presettable Binary Counter
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
VCC
Conditions
VIH
Input HIGH Voltage
Recognized as a HIGH Signal
VIL
Input LOW Voltage
Recognized as a LOW Signal
VCD
Input Clamp Diode Voltage
Min.
VOH
Output HIGH
Voltage
10% VCC
Min.
Output LOW
Voltage
10% VCC
VOL
Min.
Typ.
Max. Units
2.0
V
0.8
IIN = –18mA
–1.2
2.5
V
V
V
2.7
5% VCC
Min.
IOL = 20mA
0.5
V
IIH
Input HIGH Current
Max.
VIN = 2.7V
5.0
µA
IBVI
Input HIGH Current
Breakdown Test
Max.
VIN = 7.0V
7.0
µA
ICEX
Output HIGH Leakage
Current
Max.
VOUT = VCC
50
µA
VID
Input Leakage Test
0.0
IID = 1.9µA, All Other Pins
Grounded
IOD
Output Leakage Circuit
Current
0.0
VIOD = 150mV, All Other Pins
Grounded
3.75
µA
IIL
Input LOW Current
Max.
VIN = 0.5V (CEP, CP, MR, P0–P3)
–0.6
mA
IOS
Output Short-Circuit
Current
Max.
ICC
Power Supply Voltage
Max.
4.75
V
VIN = 0.5V (CET, PE, SR)
©1988 Fairchild Semiconductor Corporation
74F161A, 74F163A Rev. 1.0.2
VOUT = 0.0V
–1.2
–60
37
–150
mA
55
mA
www.fairchildsemi.com
6
74F161A, 74F163A Synchronous Presettable Binary Counter
DC Electrical Characteristics
TA = –55°C to +125°C, TA = 0°C to 70°C,
VCC = +5.0V,
VCC = +5.0V,
CL = 50pF
CL = 50pF
Typ. Max.
Min.
Max.
Min.
Max. Units
TA = +25°C,
VCC = +5.0V,
CL = 50pF
Symbol
Parameter
Min.
fMAX
Maximum Count Frequency
tPLH
Propagation Delay,
CP to Qn (PE Input HIGH)
3.5
5.5
7.5
3.5
9.0
3.5
8.5
3.5
7.5
10.0
3.5
11.5
3.5
11.0
Propagation Delay,
CP to Qn (PE Input LOW)
4.0
6.0
8.5
4.0
10.0
4.0
9.5
4.0
6.0
8.5
4.0
10.0
4.0
9.5
Propagation Delay,
CP to TC
5.0
10.0
14.0
5.0
16.5
5.0
15.0
5.0
10.0
14.0
5.0
15.5
5.0
15.0
Propagation Delay,
CET to TC
2.5
4.5
7.5
2.5
9.0
2.5
8.5
2.5
4.5
7.5
2.5
9.0
2.5
8.5
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
100
MHz
ns
ns
ns
ns
tPHL
Propagation Delay,
MR to Qn (74F161A)
5.5
9.0
12.0
5.5
14.0
5.5
13.0
ns
tPHL
Propagation Delay,
MR to TC (74F161A)
4.5
8.0
10.5
4.5
12.5
4.5
11.5
ns
AC Operating Requirements
TA = +25°C,
VCC = +5.0V
Symbol
Parameter
Min.
Max.
TA = –55°C to +125°C, TA = 0°C to 70°C,
VCC = +5.0V
VCC = +5.0V
Min.
Max.
Min.
Max.
Units
Setup Time, HIGH or LOW,
Pn to CP
5.0
5.5
5.0
5.0
5.5
5.0
Hold Time, HIGH or LOW,
Pn to CP
2.0
2.5
2.0
2.0
2.5
2.0
Setup Time, HIGH or LOW,
PE or SR to CP
11.0
13.5
11.5
8.5
10.5
9.5
Hold Time, HIGH or LOW,
PE or SR to CP
2.0
3.6
2.0
0
0
0
Setup Time, HIGH or LOW,
CEP or CET to CP
11.0
13.0
11.5
5.0
6.0
5.0
Hold Time, HIGH or LOW,
CEP or CET to CP
0
0
0
0
0
0
Clock Pulse Width (Load),
HIGH or LOW
5.0
5.0
5.0
5.0
5.0
5.0
Clock Pulse Width (Count),
HIGH or LOW
4.0
5.0
4.0
6.0
8.0
7.0
tW(L)
MR Pulse Width, LOW
(74F161A)
5.0
5.0
5.0
ns
tREC
Recovery Time, MR to CP
(74F161A)
6.0
6.0
6.0
ns
tS(H)
tS(L)
tH(H)
tH(L)
tS(H)
tS(L)
tH(H)
tH(L)
tS(H)
tS(L)
tH(H)
tH(L)
tW(H)
tW(L)
tW(H)
tW(L)
©1988 Fairchild Semiconductor Corporation
74F161A, 74F163A Rev. 1.0.2
ns
ns
ns
ns
ns
ns
ns
ns
www.fairchildsemi.com
7
74F161A, 74F163A Synchronous Presettable Binary Counter
AC Electrical Characteristics
74F161A, 74F163A Synchronous Presettable Binary Counter
Physical Dimensions
Dimensions are in inches (millimeters) unless otherwise noted.
Figure 2. 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
©1988 Fairchild Semiconductor Corporation
74F161A, 74F163A Rev. 1.0.2
www.fairchildsemi.com
8
74F161A, 74F163A Synchronous Presettable Binary Counter
Physical Dimensions (Continued)
Dimensions are in millimeters unless otherwise noted.
Figure 3. 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
©1988 Fairchild Semiconductor Corporation
74F161A, 74F163A Rev. 1.0.2
www.fairchildsemi.com
9
74F161A, 74F163A Synchronous Presettable Binary Counter
Physical Dimensions (Continued)
Dimensions are in inches (millimeters) unless otherwise noted.
Figure 4. 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N16E
©1988 Fairchild Semiconductor Corporation
74F161A, 74F163A Rev. 1.0.2
www.fairchildsemi.com
10
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DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER
ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
2. A critical component in any component of a life support,
device, or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Advance Information
Formative or In Design
This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Definition
Preliminary
First Production
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
design.
Obsolete
Not In Production
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I24
©1988 Fairchild Semiconductor Corporation
74F161A, 74F163A Rev. 1.0.2
www.fairchildsemi.com
11
74F161A, 74F163A Synchronous Presettable Binary Counter
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