ComLink™ Series CY2DP818 1:8 Clock Fanout Buffer Features • • • • • • • • • • • • Description Low-voltage operation VDD = 3.3V 1:8 fanout Single-input-configurable for LVDS, LVPECL, or LVTTL 8 pair of LVPECL outputs Drives a 50-ohm load Low input capacitance Low output skew Low propagation delay Typical (tpd < 4 ns) Industrial versions available Package available include: TSSOP Does not exceed Bellcore 802.3 standards Operation at ⇒ 350 MHz–700 Mbps This Cypress series of network circuits are produced using advanced 0.35-micron CMOS technology, achieving the industry’s fastest logic. The Cypress CY2DP818 fanout buffer features a single LVDS or a single-ended LVTTL-compatible input and eight LVPECL output pairs. Designed for data-communications clock-management applications, the large fanout from a single input reduces loading on the input clock. The CY2DP818 is ideal for both level translations from single-ended to LVPECL and/or for the distribution of LVPECL-based clock signals. The Cypress CY2DP818 has configurable input functions. The input is user configurable via the Inconfig pin for single ended or differential input. Pin Configuration Block Diagram Q1A Q1B Q3A Q3B INPUT (LVPECL / LVDS / LVTTL) Q4A INPUT A INPUT B Q4B Q5A InConfig Q5B Q6A Q6B Q7A Q7B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CY2DP818 Q2A Q2B GND VDD VDD VDD VDD VDD InConfig VDD GND INPUT A INPUT B GND VDD VDD VDD VDD VDD GND GND 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 GND Q1A Q1B Q2A Q2B Q3A Q3B Q4A Q4B VDD Q5A Q5B Q6A Q6B Q7A Q7B Q8A Q8B GND 38-pin TSSOP Q8A Q8B OUTPUT (LVPECL) Cypress Semiconductor Corporation Document #: 38-07061 Rev. *A • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised July 9, 2002 ComLink™ Series CY2DP818 Pin Description Pin Number Pin Name Pin Standard Interface Description 1, 9,12,18,19,20,38 GND POWER Ground 2,3,4,5,6,8, 13,14,15,16,17,29 VDD POWER Power Supply 10,11 Input A, Input B Default: LVPECL/LDVS Optional: LVTTL/LVCMOS single pin Differential input pair or single line. LVPECL/LVDS default. See InConfig, below. 37, 36,35,34, 33,32,31, 30, 28,27,26,25, 24,23,22,21 Q1(A,B), Q2(A,B) Q3(A,B), Q4(A,B) Q5(A,B), Q6(A,B) Q7(A,B), Q8(A,B) LVPECL Differential Outputs 7 InConfig LVTTL/LVCMOS Converts inputs from the default LVPECL/LVDS (logic = 0) To LVTTL/LVCMOS (logic = 1) See Figure 4 and Figure 5 for additional Information Maximum Ratings[1] Ambient Temperature:................................... –40°C to +85°C Supply Voltage to Ground Potential (Outputs only) ........................................ –0.3V to VDD + 0.3V Supply Voltage to Ground Potential DC Input Voltage ................................... –0.3V to VDD + 0.3V (Inputs and VCC only)....................................... –0.3V to 4.6V DC Output Voltage................................. –0.3V to VDD + 0.9V Storage Temperature: ................................–65°C to + 150°C Power Dissipation........................................................ 0.75W Table 1. Power Supply Characteristics Parameter Description Test Conditions ICCD Dynamic Power Supply Current VDD = Max. Input toggling 50% Duty Cycle, Outputs Open IC Total Power Supply Current VDD = Max. Input toggling 50% Duty Cycle, Outputs 50 ohms fL=100 MHz IC Core Core current when output loads are VDD = Max. Input toggling 50% Duty Cycle, Outputs disabled Disabled, not connected to VTT fL=100 MHz Min. Typ. Max. Unit 1.5 2.0 mA/MHz 350 mA 50 mA Table 2. Input Receiver Configuration for Differential or LVTTL/LVCMOS INCONFIG Pin 7 Binary Value Input Receiver Family Input Receiver Type 1 LVTTL in LVCMOS Single-ended, non-inverting, inverting, void of bias resistors 0 LVDS Low-voltage differential signaling LVPECL Low-voltage pseudo (positive) emitter coupled logic Notes: 1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Document #: 38-07061 Rev. *A Page 2 of 8 ComLink™ Series CY2DP818 Table 3. Function Control of the TTL Input Logic used to Accept or Invert the Input Signal LVTTL/LVCMOS Input Logic Input Condition Ground Input Logic Output Logic Q Pins, Q1A or Q1 Input True Input Invert Input Invert Input True Input B (–) Pin 11 Input A (+) Pin 10 VCC Input B (–) Pin 11 Ground Input A (+) Pin 10 Input A (+) Pin 10 Input B (–) Pin 11 VCC Input A (+) Pin 10 Input B (–) Pin 11 Table 4. DC Electrical Characteristics: 3.3V–LVDS Input Parameter Description Conditions Min. Typ. Max. Unit 600 mV VID Magnitude of Differential Input Voltage VIC Common-mode of Differential Input VoltageIVIDI (min. and max.) 100 VIH Input High Voltage VIL Input Low Voltage Guaranteed Logic Low Level 0.8 V IIH Input High Current VDD = Max. VIN = VDD ±10 ±20 µA IIL Input Low Current VDD = Max. VIN = VSS ±10 ±20 µA II Input High Current VDD = Max., VIN = VDD(Max.) ±20 µA IVIDI/2 2.4–(IVIDI/2) Guaranteed Logic High Level V 2 V Table 5. DC Electrical Characteristics: 3.3V–LVPECL Input Parameter Description Conditions Min. Typ. Max. Unit VID Differential Input Voltage p-p Guaranteed Logic High Level 400 2600 mV VIH Input High Voltage Guaranteed Logic High Level 2.15 2.4 V VIL Input Low Voltage Guaranteed Logic Low Level IIH Input High Current VDD = Max. VIN = VDD ±10 IIL Input Low Current VDD = Max. VIN = VSS ±10 II Input High Current VDD = Max., VIN = VDD(Max.) VCM Common-mode Voltage 1.5 1.8 V ±20 µA ±20 µA ±20 µA 225 mV Max. Units 0.8 V Table 6. DC Electrical Characteristics: 3.3V–LVTTL/LVCMOS Input Parameter Description Conditions VIH Input High Voltage Guaranteed Logic High Level VIL Input Low Voltage Guaranteed Logic Low Level Min. Typ. 2 V IIH Input High Current VDD = Max VIN = 2.7V 1 µA IIL Input Low Current VDD = Max VIN = 0.5V –1 µA 20 µA –1.2 V II Input High Current VDD = Max., VIN = VDD(Max) VIK Clamp Diode Voltage VDD = Min., IIN = –18mA VH Input Hysteresis Document #: 38-07061 Rev. *A –0.7 80 mV Page 3 of 8 ComLink™ Series CY2DP818 Table 7. DC Electrical Characteristics: 3.3V–LVPECL Output Parameter Description Conditions Min. VOD Driver Differential Output VDD = Min., VIN = VIH or VIL voltage p-p RL = 50 ohm VOC Driver common-mode p-p VDD = Min., VIN = VIH or VIL RL = 50 ohm Rise Time Differential 20% to 80% Typ. 1000 Max. Unit 3600 mV 300 mV 1200 ps CL–10 pF RL and CL to GND RL = 50 ohm 300 2.1 3.0 V 0.8 1.3 V –125 –150 mA Fall Time VOH Output High Voltage VDD = Min., VIN = VIH or VIL VOL Output Low Voltage VDD = Min., VIN = VIH or VIL User defined by VTT RTT. IOS Short Circuit Current VDD = Max, VOUT = GND IOH = –12 mA Driver Design Table 8. AC Switching Characteristics @ 3.3 V (VDD = 3.3V ±5%, Temperature = –40°C to +85°C) Parameter Description tPLH Propagation Delay – Low to High tPHL Propagation Delay – High to Low TPE Enable (EN) to functional operation TPD Functional operation to Disable tSK(0) Output Skew: Skew between outputs of the same package (in phase) tSK(p) Pulse Skew: Skew between opposite transitions of the same output (tPHL–tPLH) tSK(t) Package Skew: Skew between outputs of different packages at the same power supply voltage, temperature and package type. Same input signal level and output load. Conditions Min. VOD = 100 mV 3 Typ. Max. Unit 4 5 ns 3 4 5 ns 6 ns 5 ns 0.2 ns 0.2 ns VID = 100 mV 1 ns Table 9. High-frequency Parametrics Parameter Fmax Description Maximum frequency VDD = 3.3V Document #: 38-07061 Rev. *A Conditions 45%–55% duty cycle Standard load circuit Min. Typ. Max. Unit 350 MHz Page 4 of 8 ComLink™ Series CY2DP818 A TPA 150 Pulse 50 10pF Generator B 150 TPC VDD-2V 50 GND TPB Standard Termination V1A 1.4 V 1 .2 V C M 0 V D iffe re n tia l V1B 1.0 V V0Y 1.4 V 1 .2 V C M 0 V D iffe re n tia l 1.0 V V0Z T P LH T PHL 80% 0 V D iffe re n tia l V0Y V0Z 20% t R t F Figure 1. Differential Receiver to Driver Propagation Delay and Driver Transition Time[2,3,4,5] A TPA 150 Pulse Generator 50 TPC B 150 50 GND TPB VOC Standard Termination VI(A) 2.0V VI(B) 1.6V VOD Next Device Figure 2. Test Circuit and Voltage Definitions for the Driver Common-Mode Output Voltage[2,3,4,5] Notes: 2. All input pulses are supplied by a frequency generator with the following characteristics: tR and tF ≤ 1 ns; pulse rerate = 50 Mpps; pulse width = 10 ± 0.2 ns. 3. RL = 50 ohm ± 1%; Zline = 50 ohm 6”. 4. CL includes instrumentation and fixture capacitance within 6 mm of the UT. 5. TPA and B are used for prop delay and Rise/Fall measurements. TPC is used for VOC measurements only and is otherwise connected to VDD – 2. Document #: 38-07061 Rev. *A Page 5 of 8 ComLink™ Series CY2DP818 A TPA 150 Pulse 50 10pF Generator B 150 TPC VDD-2V 50 GND TPB Standard Termination VI(A) 1.4V VI(B) 1.0V 100% 80% 0.0V 20% 0% tF tR Figure 3. Test Circuit and Voltage Definitions for the Differential Output Signal[2,3,4,5] INPUT A LVPECL & LVDS LVCM OS / LVTTL INPUT B GND In C o n fig InConfig 0 1 L V D S /L V P E C L LVTTL/LVCMOS Figure 4. [6] Figure 5. [7] Notes: 6. See Table 3. 7. LVPECL or LVDS differential input value. Document #: 38-07061 Rev. *A Page 6 of 8 ComLink™ Series CY2DP818 Ordering Information Part Number Package Type Product Flow CY2DP818ZI 38-pin TSSOP Industrial, –40° to 85°C CY2DP818ZIT 38-pin TSSOP–Tape and Reel Industrial, –40° to 85°C CY2DP818ZC 38-pin TSSOP Commercial, 0°C to 70°C CY2DP818ZCT 38-pin TSSOP–Tape and Reel Commercial, 0°C to 70°C Package Drawing and Dimensions 38-lead TSSOP (4.40 mm Body) Z38 51-85151-** ComLink is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07061 Rev. *A Page 7 of 8 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. ComLink™ Series CY2DP818 Document Title: CY2DP818 1:8 Clock Fanout Buffer Document Number: 38-07061 REV. ECN NO. Issue Date Orig. of Change ** 107086 06/07/01 IKA New Data Sheet *A 115913 07/11/02 CTK IC, VCM, VOC, Rise/Fall Time Fmax (20) Document #: 38-07061 Rev. *A Description of Change Page 8 of 8