AKM AK4396VF

ASAHI KASEI
[AK4396]
AK4396
Advanced Multi-Bit 192kHz 24-Bit ∆Σ DAC
GENERAL DESCRIPTION
The AK4396 is a high performance stereo DAC for the 192kHz sampling mode of DVD-Audio including a
24bit digital filter. Using AKM's multi bit architecture for its modulator the AK4396 delivers a wide dynamic
range while preserving linearity for improved THD+N performance. The AK4396 has full differential SCF
outputs, removing the need for AC coupling capacitors and increasing performance for systems with
excessive clock jitter. The AK4396 accepts 192kHz PCM data and 1-bit DSD data, ideal for a wide range
of applications including DVD-Audio and SACD. The AK4396 has a fully functional compatibility with the
AK4393/4/5 and lower power dissipation.
FEATURES
• 128x Oversampling
• Sampling Rate: 30kHz ∼ 216kHz
• 24Bit 8x Digital Filter (Slow-roll-off option)
Ripple: ±0.005dB, Attenuation: 75dB
• High Tolerance to Clock Jitter
• Low Distortion Differential Output
• DSD data input available
• Digital de-emphasis for 32, 44.1, 48kHz sampling
• Soft Mute
• Digital Attenuator (Linear 256 steps)
• THD+N: −100dB
• DR, S/N: 120dB
• I/F format :
MSB justified, 16/20/24bit LSB justified, I2S
• Master Clock: Normal Speed: 256fs, 384fs, 512fs, 768fs or 1152fs
Double Speed: 128fs, 192fs, 256fs or 384fs
Quad Speed: 128fs or 192fs
DSD:
512fs or 768fs
• Power Supply: 5V ± 5% (Analog), 3.0 ∼ 5.25V (Digital)
• CMOS or TTL Level Digital I/F
• Package: 28pin VSOP
• Pin Compatible with AK4393/4/5
MS0336-E-00
2004/08
-1-
ASAHI KASEI
[AK4396]
„ Block Diagram
AVDD AVSS DVDD DVSS
VCOM
PDN TTL SMUTE DFS0
ACKS
DZFL
BICK/DCLK
LRCK/DSDR
PCM
Data
Interface
SDATA/DSDL
8X
Interpolator
∆Σ
Modulator
SCF
8X
Interpolator
∆Σ
Modulator
SCF
AOUTLAOUTR+
AOUTRDZFR
DIF0/DCLK
DSD
Data
Interface
DIF1/DSDL
DIF2/DSDR
CAD0
CAD1
AOUTL+
Control Register
CSN CCLK CDTI P/S
Clock Divider
MCLK
De-emphasis
Control
DEM0 DEM1 VREFH VREFL
Block Diagram
MS0336-E-00
2004/08
-2-
ASAHI KASEI
[AK4396]
„ Ordering Guide
AK4396VF
AKD4396
−40 ∼ +85°C
28pin VSOP (0.65mm pitch)
Evaluation Board for AK4396
„ Pin Layout
DVSS
1
28
ACKS/DZFR
DVDD
2
27
TST2/CAD1
MCLK
3
26
TST1/DZFL
PDN
4
25
P/S
BICK/DCLK
5
24
VCOM
SDATA/DSDL
6
23
AOUTL+
LRCK/DSDR
7
22
AOUTL-
SMUTE/CSN
8
21
AOUTR+
DFS0/CAD0
9
20
AOUTR-
DEM0/CCLK
10
19
AVSS
DEM1/CDTI
11
18
AVDD
DIF0/DCLK
12
17
VREFH
DIF1/DSDL
13
16
VREFL
DIF2/DSDR
14
15
TTL
Top
View
MS0336-E-00
2004/08
-3-
ASAHI KASEI
[AK4396]
„ Compatibility with AK4393/4/5
1. Function & Performance
fs (max)
DVDD
Power Dissipation
Digital Input Level
DF Stopband Attenuation
Digital Volume
µP I/F Address Pin
De-emphasis Filter
Optional DF
Zero Detection Pin
DSD Mode
Pin #15
Pin #26 (Serial mode)
Pin #28 (Serial mode)
AK4393
108kHz
3~5.25V
310mW
CMOS
75dB
AK4394
216kHz
4.75~5.25V
325mW
TTL
75dB
Not available
Not available
Not available
Not available
32k, 44.1k, 48k, 96k 32k, 44.1k, 48k, 96k
Not available
Slow Roll-off
Not available
DZFL/R
No
No
BVSS
BVSS
CKS0
DZFL
CKS2
DZFR
AK4395
216kHz
4.75~5.25V
335mW
TTL
110dB
256 levels,
0.5dB
CAD0/1
32k, 44.1k, 48k
Slow Roll-off
DZFL/R
No
BVSS
DZFL
DZFR
AK4396
216kHz
3~5.25V
200mW
CMOS/TTL
75dB
256 levels,
Linear
CAD0/1
32k, 44.1k, 48k
Slow Roll-off
DZFL/R
Yes
TTL
DZFL
DZFR
2. Pin Configuration
Pin# AK4393
AK4394
1
DVSS
DVSS
2
DVDD
DVDD
3
MCLK
MCLK
4
PDN
PDN
5
BICK
BICK
6
SDATA
SDATA
7
LRCK
LRCK
8
SMUTE/CSN
SMUTE/CSN
9
DFS0
DFS0
10
DEM0/CCLK
DEM0/CCLK
11
DEM1/CDTI
DEM1/CDTI
12
DIF0
DIF0
13
DIF1
DIF1
14
DIF2
DIF2
15
BVSS
BVSS
16
VREFL
VREFL
17
VFEFH
VFEFH
18
AVDD
AVDD
19
AVSS
AVSS
20
AOUTRAOUTR21
AOUTR+
AOUTR+
22
AOUTLAOUTL23
AOUTL+
AOUTL+
24
VCOM
VCOM
25
P/S
P/S
26
CKS0
CKS0/DZFL
27
CKS1
CKS1
28
CKS2
CKS2/DZFR
TST1-2: Don’t care at parallel mode.
AK4395
DVSS
DVDD
MCLK
PDN
BICK
SDATA
LRCK
SMUTE/CSN
DFS0/CAD0
DEM0/CCLK
DEM1/CDTI
DIF0
DIF1
DIF2
BVSS
VREFL
VFEFH
AVDD
AVSS
AOUTRAOUTR+
AOUTLAOUTL+
VCOM
P/S
CKS0/DZFL
CKS1/CAD1
ACKS/DZFR
MS0336-E-00
AK4396
DVSS
DVDD
MCLK
PDN
BICK
SDATA
LRCK
SMUTE/CSN
DFS0/CAD0
DEM0/CCLK
DEM1/CDTI
DIF0
DIF1
DIF2
TTL
VREFL
VFEFH
AVDD
AVSS
AOUTRAOUTR+
AOUTLAOUTL+
VCOM
P/S
TST1/DZFL
TST2/CAD1
ACKS/DZFR
2004/08
-4-
ASAHI KASEI
[AK4396]
3. Compatibility of master clock select in parallel mode
AK4393/4/5
CKS2
0
0
0
0
1
1
1
1
CKS1
0
0
1
1
0
0
1
1
CKS0
0
1
0
1
0
1
0
1
DFS0=0
256fs
256fs
384fs
384fs
512fs
512fs
768fs
768fs
AK4396
DFS0=1
ACKS
DFS0=0 DFS0=1
128fs
0
256fs
128fs
256fs
0
256fs
256fs
192fs
0
384fs
192fs
384fs
0
384fs
384fs
256fs
1
512fs
256fs
N/A
1
512fs
N/A
384fs
1
768fs
384fs
N/A
1
768fs
N/A
: The setting of DFS0 is ignored.
4. Register map
Addr
00H
01H
02H
03H
04H
Register Name
Control 1
Control 2
Control 3
Lch ATT Control
Rch ATT Control
D7
ACKS
DZFE
D/P
ATT7
ATT7
D6
0
DZFM
DSDM
ATT6
ATT6
D5
0
SLOW
DCKS
ATT5
ATT5
D4
0
DFS1
DCKB
ATT4
ATT4
D3
DIF2
DFS0
0
ATT3
ATT3
D2
DIF1
DEM1
DZFB
ATT2
ATT2
D1
DIF0
DEM0
0
ATT1
ATT1
D0
RSTN
SMUTE
0
ATT0
ATT0
: Changing points from AK4393’s register.
Italic means the default value differs from AK4393.
Addr
Register Name
00H
01H
02H
03H
04H
Control 1
Control 2
Control 3
Lch ATT Control
Rch ATT Control
D7
D6
D5
D4
D3
D2
D1
D0
ACKS
DZFE
D/P
ATT7
ATT7
0
DZFM
DSDM
ATT6
ATT6
0
SLOW
DCKS
ATT5
ATT5
0
DFS1
DCKB
ATT4
ATT4
DIF2
DFS0
0
ATT3
ATT3
DIF1
DEM1
DZFB
ATT2
ATT2
DIF0
DEM0
0
ATT1
ATT1
RSTN
SMUTE
0
ATT0
ATT0
D1
DIF0
DEM0
0
ATT1
ATT1
D0
RSTN
SMUTE
0
ATT0
ATT0
: Changing points from AK4394’s register.
Italic means the default value differs from AK4394.
Addr
00H
01H
02H
03H
04H
Register Name
Control 1
Control 2
Control 3
Lch ATT Control
Rch ATT Control
D7
ACKS
DZFE
D/P
ATT7
ATT7
D6
D5
D4
D3
D2
0
0
0
DIF2
DIF1
DZFM SLOW
DFS1
DFS0
DEM1
DSDM DCKS
DCKB
0
DZFB
ATT6
ATT5
ATT4
ATT3
ATT2
ATT6
ATT5
ATT4
ATT3
ATT2
: Changing points from AK4395’s register.
Italic means the default value differs from AK4395.
MS0336-E-00
2004/08
-5-
ASAHI KASEI
[AK4396]
PIN/FUNCTION
No.
Pin Name
I/O
1
2
3
DVSS
DVDD
MCLK
I
4
PDN
I
BICK
DCLK
SDATA
DSDL
LRCK
DSDR
I
I
I
I
I
I
SMUTE
I
CSN
DFS0
CAD0
DEM0
CCLK
DEM1
CDTI
DIF0
DCLK
DIF1
DSDL
DIF2
DSDR
I
I
I
I
I
I
I
I
I
I
I
I
I
5
6
7
8
9
10
11
12
13
14
Function
Digital Ground Pin
Digital Power Supply Pin, 3.3V or 5.0V
Master Clock Input Pin
Power-Down Mode Pin
When at “L”, the AK4396 is in power-down mode and is held in reset.
The AK4396 should always be reset upon power-up.
Audio Serial Data Clock Pin in PCM mode
DSD Clock Pin in DSD mode
Audio Serial Data Input Pin in PCM mode
DSD Lch Data Input Pin in DSD mode
L/R Clock Pin in PCM mode
DSD Rch Data Input Pin in DSD mode
Soft Mute Pin in parallel mode
When this pin goes “H”, soft mute cycle is initiated.
When returning “L”, the output mute releases.
Chip Select Pin in serial mode
Sampling Speed Mode Select Pin in parallel mode (Internal pull-down pin)
Chip Address 0 Pin in serial mode
(Internal pull-down pin)
De-emphasis Enable 0 Pin in parallel mode
Control Data Clock Pin in serial mode
De-emphasis Enable 1 Pin in parallel mode
Control Data Input Pin in serial mode
Digital Input Format 0 Pin in PCM mode
DSD Clock Pin in DSD mode
Digital Input Format 1 Pin in PCM mode
DSD Lch Data Input Pin in DSD mode
Digital Input Format 2 Pin in PCM mode
DSD Rch Data Input Pin in DSD mode
Note: All input pins except internal pull-up/down pins should not be left floating.
MS0336-E-00
2004/08
-6-
ASAHI KASEI
[AK4396]
15
TTL
I
16
17
18
19
20
21
22
23
24
VREFL
VREFH
AVDD
AVSS
AOUTR−
AOUTR+
AOUTL−
AOUTL+
VCOM
I
I
O
O
O
O
O
25
P/S
I
TST1
DZFL
TST2
CAD1
ACKS
DZFR
O
O
I
I
I
O
26
27
28
CMOS/TTL Level Select Pin
(Internal pull-up pin)
“L” : CMOS Level, “H” : TTL Level
Low Level Voltage Reference Input Pin
High Level Voltage Reference Input Pin
Analog Power Supply Pin, 5.0V
Analog Ground Pin
Rch Negative Analog Output Pin
Rch Positive Analog Output Pin
Lch Negative Analog Output Pin
Lch Positive Analog Output Pin
Common Voltage Output Pin, AVDD/2
Parallel/Serial Select Pin
(Internal pull-up pin)
“L”: Serial Mode, “H”: Parallel Mode
Test 1 Pin in parallel mode
(Don’t Care)
Lch Zero Input Detect Pin in serial mode
Test 2 Pin in parallel mode
(Internal pull-down pin)
Chip Address 1 Pin in serial mode
(Internal pull-down pin)
Master Clock Auto Setting Mode Pin in parallel mode
Rch Zero Input Detect Pin in serial mode
Note: All input pins except internal pull-up/down pins should not be left floating.
Note: TST1 pin outputs Hi-Z in parallel mode.
MS0336-E-00
2004/08
-7-
ASAHI KASEI
[AK4396]
„ Handling of Unused Pin
The unused I/O pins should be processed appropriately as below.
(1) Parallel mode (PCM mode only)
Classification
Pin Name
Setting
These pins should be open.
AOUTL+, AOUTL−
AOUTR+, AOUTR−
SMUTE
TST1
TST2
Analog
Digital
These pins should be open.
This pin should be connected to DVSS.
This pin should be open.
This pin should be connected to DVSS.
(2) Serial mode
1. PCM mode
Classification
Analog
Digital
Pin Name
Setting
These pins should be open.
AOUTL+, AOUTL−
AOUTR+, AOUTR−
DIF2, DIF1, DIF0
DZFL, DZFR
These pins should be open.
These pins should be connected to DVSS.
These pins should be open.
2. DSD mode
• In case of using #5(DCLK), #6(DSDL) and #7(DSDR) pins
Classification
Analog
Digital
Pin Name
Setting
These pins should be open.
AOUTL+, AOUTL−
AOUTR+, AOUTR−
DCLK(#12), DSDL(#13), DSDR(#14)
DZFL, DZFR
These pins should be open.
These pins should be connected to DVSS.
These pins should be open.
• In case of using #12(DCLK), #13(DSDL) and #14(DSDR) pins
Classification
Analog
Digital
Pin Name
AOUTL+, AOUTL−
AOUTR+, AOUTR−
DCLK(#5), DSDL(#6), DSDR(#7)
DZFL, DZFR
MS0336-E-00
Setting
These pins should be open.
These pins should be open.
These pins should be connected to DVSS.
These pins should be open.
2004/08
-8-
ASAHI KASEI
[AK4396]
ABSOLUTE MAXIMUM RATINGS
(AVSS, DVSS = 0V; Note 1)
Parameter
Symbol
min
Power Supplies:
Analog
AVDD
−0.3
Digital
DVDD
−0.3
|AVSS − DVSS|
(Note 2)
∆ GND
Input Current, Any pin Except Supplies
IIN
Input Voltage
VIND
−0.3
Ambient Operating Temperature
Ta
−40
Storage Temperature
Tstg
−65
max
6.0
6.0
0.3
±10
DVDD+0.3
85
150
Units
V
V
V
mA
V
°C
°C
Note 1. All voltages with respect to ground.
Note 2. AVSS and DVSS must be connected to the same analog ground plane.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS, DVSS=0V; Note 1)
Parameter
Symbol
min
typ
Power Supplies:
Analog
AVDD
4.75
5.0
(Note 3)
Digital
DVDD
3.0
5.0
Voltage Reference
“H” voltage reference
VREFH
AVDD-0.5
(Note 4)
“L” voltage reference
VREFL
AVSS
VREFH-VREFL
3.0
∆ VREF
max
5.25
5.25
AVDD
AVDD
Units
V
V
V
V
V
Note 1. All voltages with respect to ground.
Note 3. The power up sequence between AVDD and DVDD is not critical.
Note 4. Analog output voltage scales with the voltage of (VREFH − VREFL).
AOUT ([email protected]) = (AOUT+) − (AOUT−) = ±2.8Vpp×(VREFH − VREFL)/5.
* AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
MS0336-E-00
2004/08
-9-
ASAHI KASEI
[AK4396]
ANALOG CHARACTERISTICS
(Ta=25°C; AVDD=DVDD=5.0V; AVSS=DVSS=0V; VREFH=AVDD, VREFL=AVSS; Input data=24bit; RL ≥ 1kΩ;
BICK=64fs; Input Signal Frequency = 1kHz; Sampling frequency = 44.1kHz; Measurement bandwidth = 20Hz ~ 20kHz;
External Circuit: Figure 17; unless otherwise specified.)
Parameter
min
typ
max
Units
Resolution
24
Bits
Dynamic Characteristics
(Note 5)
0dBFS
−100
−90
dB
fs=44.1kHz
THD+N
BW=20kHz
−57
dB
−60dBFS
0dBFS
−97
dB
fs=96kHz
BW=40kHz
−54
dB
−60dBFS
0dBFS
−97
dB
fs=192kHz
BW=40kHz
−60dBFS
−54
dB
BW=80kHz
−51
dB
−60dBFS
Dynamic Range (−60dBFS with A-weighted)
(Note 6)
114
120
dB
S/N (A-weighted)
(Note 7)
114
120
dB
Interchannel Isolation (1kHz)
100
120
dB
DC Accuracy
Interchannel Gain Mismatch
0.15
0.3
dB
Gain Drift
(Note 8)
20
ppm/°C
Output Voltage
(Note 9)
±2.65
±2.8
±2.95
Vpp
Load Capacitance
25
pF
Load Resistance
(Note 10)
1
kΩ
Power Supplies
Power Supply Current
Normal operation (PDN pin = “H”)
AVDD
DVDD (fs ≤ 96kHz)
DVDD (fs = 192kHz)
Power down (PDN pin = “L”)
AVDD+DVDD
Power Supply Rejection
(Note 11)
32
8
13
47
19
mA
mA
mA
10
50
100
µA
dB
(Note 12)
(Note 13)
Note 5. Measured by Audio Precision, System Two. Averaging mode. Refer to the evaluation board manual.
Note 6. By Figure 17. External LPF Circuit Example 2.101dB at 16bit data and 118dB at 20bit data.
Note 7. By Figure 17. External LPF Circuit Example 2. S/N does not depend on input bit length.
Note 8. The voltage on (VREFH − VREFL) is held +5V externally.
Note 9. Full-scale voltage(0dB). Output voltage scales with the voltage of (VREFH − VREFL).
AOUT ([email protected]) = (AOUT+) − (AOUT−) = ±2.8Vpp × (VREFH − VREFL)/5.
Note 10. For AC-load. 1.5kΩ for DC-Load
Note 11. typ. 5mA (@ DVDD=3.3V, fs ≤ 96kHz), typ. 8mA (@ DVDD=3.3V, fs = 192kHz)
Note 12. In the power-down mode. P/S pin = TTL pin = DVDD, and all other digital input pins including clock pins
(MCLK, BICK and LRCK) are held DVSS.
Note 13. PSR is applied to AVDD, DVDD with 1kHz, 100mVpp. VREFH pin is held +5V.
MS0336-E-00
2004/08
- 10 -
ASAHI KASEI
[AK4396]
SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 44.1kHz)
(Ta=25°C; AVDD=4.75 ~ 5.25V, DVDD=3.0 ~ 5.25V; Normal Speed Mode; DEM=OFF; SLOW bi =“0”)
Parameter
Symbol
min
typ
max
Digital Filter
Passband
(Note 15) ±0.01dB
PB
0
20.0
−6.0dB
22.05
Stopband
(Note 14)
SB
24.1
Passband Ripple
PR
±0.005
Stopband Attenuation
SA
75
Group Delay
(Note 15)
GD
28
Digital Filter + SCF
Frequency Response : 0 ∼ 20.0kHz
±0.2
-
SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 96kHz)
(Ta=25°C; AVDD=4.75 ∼ 5.25V, DVDD=3.0 ∼ 5.25V; Double Speed Mode; DEM=OFF; SLOW bit=“0”)
Parameter
Symbol
min
typ
max
Digital Filter
PB
0
43.5
Passband
(Note 14) ±0.01dB
−6.0dB
48.0
Stopband
(Note 14)
SB
52.5
Passband Ripple
PR
±0.005
Stopband Attenuation
SA
75
Group Delay
(Note 15)
GD
28
Digital Filter + SCF
Frequency Response : 0 ∼ 40.0kHz
±0.3
-
SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 192kHz)
(Ta=25°C; AVDD=4.75 ∼ 5.25V, DVDD=3.0 ∼ 5.25V; Quad Speed Mode; DEM=OFF; SLOW bit=“0”)
Parameter
Symbol
min
typ
max
Digital Filter
Passband
(Note 14) ±0.01dB
PB
0
87.0
−6.0dB
96.0
Stopband
(Note 14)
SB
105
Passband Ripple
PR
±0.005
Stopband Attenuation
SA
75
Group Delay
(Note 15)
GD
28
Digital Filter + SCF
Frequency Response : 0 ∼ 80.0kHz
+0/−1
-
Units
kHz
kHz
kHz
dB
dB
1/fs
dB
Units
kHz
kHz
kHz
dB
dB
1/fs
dB
Units
kHz
kHz
kHz
dB
dB
1/fs
dB
Note 14. The passband and stopband frequencies scale with fs. For example, PB = 0.4535×fs (@±0.01dB), SB =
0.546×fs.
Note 15. The calculating delay time which occurred by digital filtering. This time is from setting the 16/20/24bit data of
both channels to input register to the output of analog signal.
MS0336-E-00
2004/08
- 11 -
ASAHI KASEI
[AK4396]
SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 44.1kHz)
(Ta=25°C; AVDD=4.75 ∼ 5.25V, DVDD=3.0 ∼ 5.25V; Normal Speed Mode; DEM=OFF; SLOW bit=“1”)
Parameter
Symbol
min
typ
max
Digital Filter
Passband
(Note 16) ±0.04dB
PB
0
8.1
−3.0dB
18.2
Stopband
(Note 16)
SB
39.2
Passband Ripple
PR
±0.005
Stopband Attenuation
SA
72
Group Delay
(Note 15)
GD
28
Digital Filter + SCF
Frequency Response: 0 ∼ 20.0kHz
+0/−5
-
SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 96kHz)
(Ta=25°C; AVDD=4.75 ∼ 5.25V, DVDD=3.0 ∼ 5.25V; DEM=OFF; SLOW bit=“1”)
Parameter
Symbol
min
typ
max
Digital Filter
PB
0
17.7
Passband
(Note 16) ±0.04dB
−3.0dB
39.6
Stopband
(Note 15)
SB
85.3
Passband Ripple
PR
±0.005
Stopband Attenuation
SA
72
Group Delay
(Note 14)
GD
28
Digital Filter + SCF
Frequency Response: 0 ∼ 40.0kHz
+0/−4
-
SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 192kHz)
(Ta=25°C; AVDD=4.75 ∼ 5.25V, DVDD=3.0 ∼ 5.25V; Quad Speed Mode; DEM=OFF; SLOW bit=“1”)
Parameter
Symbol
min
typ
max
Digital Filter
Passband
(Note 16) ±0.04dB
PB
0
35.5
−3.0dB
79.1
Stopband
(Note 16)
SB
171
Passband Ripple
PR
±0.005
Stopband Attenuation
SA
72
Group Delay
(Note 15)
GD
28
Digital Filter + SCF
Frequency Response: 0 ∼ 80.0kHz
+0/−5
-
Units
kHz
kHz
kHz
dB
dB
1/fs
dB
Units
kHz
kHz
kHz
dB
dB
1/fs
dB
Units
kHz
kHz
kHz
dB
dB
1/fs
dB
Note 16. The passband and stopband frequencies scale with fs. For example, PB = 0.185×fs (@±0.04dB), SB = 0.888×fs.
MS0336-E-00
2004/08
- 12 -
ASAHI KASEI
[AK4396]
DC CHARACTERISTICS (CMOS Level Mode)
(Ta=25°C; AVDD=4.75 ~ 5.25V, DVDD=3.0 ~ 5.25V; TTL pin = “L”)
Parameter
Symbol
min
typ
High-Level Input Voltage
VIH
70%DVDD
Low-Level Input Voltage
VIL
High-Level Output Voltage (Iout = −100µA)
VOH
DVDD−0.5
Low-Level Output Voltage (Iout = 100µA)
VOL
Input Leakage Current
(Note 17)
Iin
-
max
30%DVDD
0.5
±10
Units
V
V
V
V
µA
DC CHARACTERISTICS (TTL Level Mode)
(Ta=25°C; AVDD=4.75 ~ 5.25V, DVDD=4.75 ~ 5.25V; TTL pin = “H”)
Parameter
Symbol
min
typ
High-Level Input Voltage
(TTL pin)
VIH
70%DVDD
(All pins except TTL pin)
VIH
2.2
Low-Level Input Voltage
(TTL pin)
VIL
(All pins except TTL pin)
VIL
VOH
DVDD-0.5
High-Level Output Voltage (Iout = −100µA)
VOL
Low-Level Output Voltage (Iout = 100µA)
Input Leakage Current
(Note 17)
Iin
-
max
30%DVDD
0.8
0.5
± 10
Units
V
V
V
V
V
V
µA
Note 17. DFS0, TTL, P/S and TST2 pins have internal pull-down or pull-up devices, nominally 100kΩ.
MS0336-E-00
2004/08
- 13 -
ASAHI KASEI
[AK4396]
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD=4.75 ∼ 5.25V, DVDD=3.0 ∼ 5.25V)
Parameter
Symbol
min
Master Clock Timing
Frequency
fCLK
7.7
Duty Cycle
dCLK
40
LRCK Frequency
(Note 18)
Normal Speed Mode
fsn
30
Double Speed Mode
fsd
54
Quad Speed Mode
fsq
108
Duty Cycle
Duty
45
PCM Audio Interface Timing
BICK Period
Normal Speed Mode
tBCK
1/128fn
Double Speed Mode
tBCK
1/64fd
Quad Speed Mode
tBCK
1/64fq
BICK Pulse Width Low
tBCKL
30
BICK Pulse Width High
tBCKH
30
BICK “↑” to LRCK Edge
(Note 19)
tBLR
20
LRCK Edge to BICK “↑”
(Note 19)
tLRB
20
SDATA Hold Time
tSDH
20
SDATA Setup Time
tSDS
20
DSD Audio Interface Timing
DCLK Period
tDCK
1/64fs
DCLK Pulse Width Low
tDCKL
160
DCLK Pulse Width High
tDCKH
160
DCLK Edge to DSDL/R
(Note 20)
tDDD
−20
Control Interface Timing
CCLK Period
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTI Setup Time
tCDS
50
CDTI Hold Time
tCDH
50
CSN High Time
tCSW
150
CSN “↓” to CCLK “↑”
tCSS
50
CCLK “↑” to CSN “↑”
tCSH
50
Reset Timing
PDN Pulse Width
(Note 21)
tPD
150
typ
max
Units
41.472
60
MHz
%
54
108
216
55
kHz
kHz
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 18. When the normal/double/quad speed modes are switched, AK4396 should be reset by PDN pin or RSTN bit.
Note 19. BICK rising edge must not occur at the same time as LRCK edge.
Note 20. DSD data transmitting device must meet this time.
Note 21. The AK4396 can be reset by bringing PDN pin “L” to “H”. When the states of or DFS1-0 bits change,
the AK4396 should be reset by RSTN bit.
MS0336-E-00
2004/08
- 14 -
ASAHI KASEI
[AK4396]
„ Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Clock Timing
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tSDS
tSDH
VIH
SDATA
VIL
Audio Interface Timing (PCM Mode)
MS0336-E-00
2004/08
- 15 -
ASAHI KASEI
[AK4396]
tDCK
tDCKL
tDCKH
VIH
DCLK
VIL
tDDD
VIH
DSDL
DSDR
VIL
Audio Serial Interface Timing (DSD Normal Mode, DCKB bit = “0”)
tDCK
tDCKL
tDCKH
VIH
DCLK
VIL
tDDD
tDDD
VIH
DSDL
DSDR
VIL
Audio Serial Interface Timing (DSD Phase Modulation Mode, DCKB bit = “0”)
VIH
CSN
VIL
tCSS
tCCKL tCCKH
VIH
CCLK
VIL
tCDS
CDTI
C1
tCDH
C0
R/W
A4
VIH
VIL
WRITE Command Input Timing
MS0336-E-00
2004/08
- 16 -
ASAHI KASEI
[AK4396]
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
CDTI
VIL
D3
D2
D1
D0
VIH
VIL
WRITE Data Input Timing
tPD
PDN
VIL
Power Down & Reset Timing
MS0336-E-00
2004/08
- 17 -
ASAHI KASEI
[AK4396]
OPERATION OVERVIEW
„ D/A Conversion Mode
In serial mode, the AK4396 can perform D/A conversion for either PCM data or DSD data. The D/P bit controls
PCM/DSD mode. When DSD mode, DSD data can be input from DCLK, DSDL and DSDR pins. When PCM mode,
PCM data can be input from BICK, LRCK and SDATA pins. When PCM/DSD mode changes by D/P bit, the AK4396
should be reset by RSTN bit. It takes about 2/fs to 3/fs to change the mode. In parallel mode, the AK4396 performs for
only PCM data.
D/P bit
Interface
0
PCM
1
DSD
Table 1. PCM/DSD Mode Control
„ System Clock
[1] PCM Mode
The external clocks, which are required to operate the AK4396, are MCLK, BICK and LRCK. MCLK should be
synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the
delta-sigma modulator. When external clocks are changed, the AK4396 should be reset by PDN pin or RSTN bit.
All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4396 is in normal operation
mode (PDN pin = “H”). If these clocks are not provided, the AK4396 may draw excess current because the device utilizes
dynamic refreshed logic internally. If the external clocks are not present, the AK4396 should be in the power-down mode
(PDN pin = “L”) or in the reset mode (RSTN bit = “0”). After exiting reset (PDN pin = “L” → “H”) at power-up etc., the
AK4396 is in power-down mode until MCLK is supplied.
(1) Parallel Mode (P/S pin = “H”)
1. Manual Setting Mode (ACKS pin = “L”)
MCLK frequency is detected automatically and the sampling speed is set by DFS0 pin (Table 2). The MCLK frequency
corresponding to each sampling speed should be provided (Table 3). DFS1 bit is fixed to “0”. When DFS0 pin is changed,
the AK4396 should be reset by PDN pin. Quad speed mode is not supported in this mode.
DFS0 pin
Sampling Rate (fs)
L
Normal Speed Mode
30kHz ∼ 54kHz
H
Double Speed Mode
54kHz ∼ 108kHz
Table 2. Sampling Speed (Manual Setting Mode @Parallel Mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
128fs
N/A
N/A
N/A
11.2896
12.2880
MCLK (MHz)
192fs
256fs
384fs
512fs
768fs
1152fs
N/A
8.1920
12.2880
16.3840
24.5760
36.8640
N/A
11.2896
16.9344
22.5792
33.8688
N/A
N/A
12.2880
18.4320
24.5760
36.8640
N/A
16.9344
22.5792
33.8688
N/A
N/A
N/A
18.4320
24.5760
36.8640
N/A
N/A
N/A
Table 3. System Clock Example (Manual Setting Mode @Parallel Mode)
MS0336-E-00
BICK
64fs
2.0480MHz
2.8224MHz
3.0720MHz
5.6448MHz
6.1440MHz
2004/08
- 18 -
ASAHI KASEI
[AK4396]
2. Auto Setting Mode (ACKS pin = “H”)
MCLK frequency and the sampling speed are detected automatically (Table 4) and DFS0 pin is ignored. DFS0 pin should
be fixed to DVSS or DVDD.
MCLK
1152fs
Sampling Speed
Normal (fs≤32kHz)
512fs
768fs
Normal
256fs
384fs
Double
128fs
192fs
Quad
Table 4. Sampling Speed (Auto Setting Mode @Parallel Mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
128fs
N/A
N/A
N/A
N/A
N/A
22.5792
24.5760
MCLK (MHz)
192fs
256fs
384fs
512fs
768fs
1152fs
N/A
N/A
N/A
16.3840
24.5760
36.8640
N/A
N/A
N/A
22.5792
33.8688
N/A
N/A
N/A
N/A
24.5760
36.8640
N/A
N/A
22.5792
33.8688
N/A
N/A
N/A
N/A
24.5760
36.8640
N/A
N/A
N/A
33.8688
N/A
N/A
N/A
N/A
N/A
36.8640
N/A
N/A
N/A
N/A
N/A
Table 5. System Clock Example (Auto Setting Mode @Parallel Mode)
Sampling
Speed
Normal
Double
Quad
(2) Serial Mode (P/S pin = “L”)
1. Manual Setting Mode (ACKS bit = “0”)
MCLK frequency is detected automatically and the sampling speed is set by DFS1-0 bits (Table 6). The MCLK frequency
corresponding to each sampling speed should be provided (Table 7). The AK4396 is set to Manual Setting Mode at
power-up (PDN pin = “L” → “H”). When DFS1-0 bits are changed, the AK4396 should be reset by RSTN bit.
DFS1 bit DFS0 bit
Sampling Rate (fs)
Default
0
0
Normal Speed Mode
30kHz ∼ 54kHz
0
1
Double Speed Mode
54kHz ∼ 108kHz
1
0
Quad Speed Mode
120kHz ∼ 216kHz
Table 6. Sampling Speed (Manual Setting Mode @Serial Mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
128fs
N/A
N/A
N/A
11.2896
12.2880
22.5792
24.5760
MCLK (MHz)
192fs
256fs
384fs
512fs
768fs
1152fs
N/A
8.1920
12.2880
16.3840
24.5760
36.8640
N/A
11.2896
16.9344
22.5792
33.8688
N/A
N/A
12.2880
18.4320
24.5760
36.8640
N/A
16.9344
22.5792
33.8688
N/A
N/A
N/A
18.4320
24.5760
36.8640
N/A
N/A
N/A
33.8688
N/A
N/A
N/A
N/A
N/A
36.8640
N/A
N/A
N/A
N/A
N/A
Table 7. System Clock Example (Manual Setting Mode @Serial Mode)
MS0336-E-00
BICK
64fs
2.0480MHz
2.8224MHz
3.0720MHz
5.6448MHz
6.1440MHz
11.2896MHz
12.2880MHz
2004/08
- 19 -
ASAHI KASEI
[AK4396]
2. Auto Setting Mode (ACKS bit = “1”)
MCLK frequency and the sampling speed are detected automatically (Table 8) and DFS1-0 bits are ignored. The MCLK
frequency corresponding to each sampling speed should be provided (Table 9).
MCLK
1152fs
Sampling Speed
Normal (fs≤32kHz)
512fs
768fs
Normal
256fs
384fs
Double
128fs
192fs
Quad
Table 8. Sampling Speed (Auto Setting Mode @Serial Mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
128fs
N/A
N/A
N/A
N/A
N/A
22.5792
24.5760
MCLK (MHz)
192fs
256fs
384fs
512fs
768fs
1152fs
N/A
N/A
N/A
16.3840
24.5760
36.8640
N/A
N/A
N/A
22.5792
33.8688
N/A
N/A
N/A
N/A
24.5760
36.8640
N/A
N/A
22.5792
33.8688
N/A
N/A
N/A
N/A
24.5760
36.8640
N/A
N/A
N/A
33.8688
N/A
N/A
N/A
N/A
N/A
36.8640
N/A
N/A
N/A
N/A
N/A
Table 9. System Clock Example (Auto Setting Mode @Serial Mode)
Sampling
Speed
Normal
Double
Quad
[2] DSD Mode
The external clocks, which are required to operate the AK4396, are MCLK and DCLK. MCLK should be synchronized
with DCLK but the phase is not critical. The frequency of MCLK is set by DCKS bit.
All external clocks (MCLK, DCLK) should always be present whenever the AK4396 is in the normal operation mode
(PDN pin = “H”). If these clocks are not provided, the AK4396 may draw excess current because the device utilizes
dynamic refreshed logic internally. The AK4396 should be reset by PDN pin = “L” after threse clocks are provided. If the
external clocks are not present, the AK4396 should be in the power-down mode (PDN pin = “L”). After exiting
reset(PDN pin = “L” → “H”) at power-up etc., the AK4396 is in the power-down mode until MCLK is input.
DCKS bit
0
1
MCLK Frequency
DCLK Frequency
512fs
64fs
768fs
64fs
Table 10. System Clock (DSD Mode)
MS0336-E-00
Default
2004/08
- 20 -
ASAHI KASEI
[AK4396]
„ Audio Interface Format
[1] PCM Mode
Data is shifted in via the SDATA pin using BICK and LRCK inputs. Five data formats are supported and selected by the
DIF2-0 pins (Parallel mode) or DIF2-0 bits (Serial mode) as shown in Table 11. In all formats the serial data is MSB-first,
2's compliment format and is latched on the rising edge of BICK. Mode 2 can be used for 20 and 16 MSB justified formats
by zeroing the unused LSBs.
Mode
0
1
2
3
4
DIF2
0
0
0
0
1
DIF1
0
0
1
1
0
DIF0
Input Format
BICK
0
16bit LSB justified
≥ 32fs
1
20bit LSB justified
≥ 48fs
0
24bit MSB justified
≥ 48fs
1
24bit I2S Compatible
≥ 48fs
0
24bit LSB justified
≥ 48fs
Table 11. Audio Interface Format
Figure
Figure 1
Figure 2
Figure 3
Figure 4
Figure 2
Default
LRCK
0
1
10
11
12
13
14
15
0
1
10
11
12
13
14
15
0
1
BICK
(32fs)
SDATA
Mode 0
15
0
14
6
1
5
14
4
15
3
2
16
17
1
0
31
15
0
14
6
5
14
1
4
15
3
16
2
17
1
0
31
15
14
0
1
0
1
BICK
(64fs)
SDATA
Mode 0
Don’t care
15
14
Don’t care
0
15
14
0
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 1. Mode 0 Timing
LRCK
0
1
8
9
10
11
12
31
0
1
8
9
10
11
12
31
BICK
(64fs)
SDATA
Mode 1
Don’t care
19
0
Don’t care
19
0
Don’t care
19
0
19
0
19:MSB, 0:LSB
SDATA
Mode 4
Don’t care
23
22
21
20
23
22
21
20
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 2. Mode 1, 4 Timing
MS0336-E-00
2004/08
- 21 -
ASAHI KASEI
[AK4396]
LRCK
0
1
2
22
23
24
30
31
0
1
2
22
23
24
30
31
0
1
BICK
(64fs)
SDATA
23 22
1
0
Don’t care
23 22
0
1
Don’t care
23
22
0
1
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 3. Mode 2 Timing
LRCK
0
1
2
3
23
24
25
31
0
1
2
3
23
24
25
31
BICK
(64fs)
SDATA
1
23 22
0
Don’t care
23 22
1
0
Don’t care
23
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 4. Mode 3 Timing
[2] DSD Mode
In case of DSD mode, DIF2-0 pins and DIF2-0 bits are ignored. The frequency of DCLK is fixed to 64fs. DCKB bit can
invert the polarity of DCLK.
DCLK (64fs)
DCKB=1
DCLK (64fs)
DCKB=0
DSDL,DSDR
Normal
D0
DSDL,DSDR
Phase Modulation
D0
D1
D1
D2
D1
D2
D3
D2
D3
Figure 5. DSD Mode Timing
MS0336-E-00
2004/08
- 22 -
ASAHI KASEI
[AK4396]
„ D/A conversion mode switching timing
RSTN bit
≥4/fs
D/A Mode
PCM Mode
DSD Mode
≥0
D/A Data
PCM Data
DSD Data
Figure 6. D/A Mode Switching Timing (PCM to DSD)
RSTN bit
D/A Mode
DSD Mode
PCM Mode
≥4/fs
D/A Data
DSD Data
PCM Data
Figure 7. D/A Mode Switching Timing (DSD to PCM)
Caution: In DSD mode, the signal level is ranging from 25% to 75%. Peak levels of DSD signal above this duty are not
recommended by SACD format book (Scarlet Book).
„ De-emphasis Filter
A digital de-emphasis filter is available for 32kHz, 44.1kHz or 48kHz sampling rates (tc = 50/15µs) and is enabled or
disabled with DEM1-0 pins or DEM1-0 bits. In case of double speed and quad speed mode, the digital de-emphasis filter
is always off. When DSD mode, DEM1-0 bits are ignored. The setting value is held even if PCM mode and DSD mode
are switched.
DEM1
DEM0
Mode
0
0
44.1kHz
0
1
OFF
Default
1
0
48kHz
1
1
32kHz
Table 12. De-emphasis Control (Normal Speed Mode)
„ Output Volume
The AK4396 includes channel independent digital output volumes (ATT) with 256 levels at linear step including MUTE.
These volumes are in front of the DAC and can attenuate the input data from 0dB to –48dB and mute. When changing
levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions. The transition
time of 1 level and all 256 levels is shown in Table 13.
Transition Time
1 Level
255 to 0
Normal Speed Mode
4LRCK
1020LRCK
Double Speed Mode
8LRCK
2040LRCK
Quad Speed Mode
16LRCK
4080LRCK
Table 13. ATT Transition Time
Sampling Speed
MS0336-E-00
2004/08
- 23 -
ASAHI KASEI
[AK4396]
„ Zero Detection
The AK4396 has channel-independent zeros detect function. When the input data at each channel is continuously zeros
for 8192 LRCK cycles, DZF pin of each channel goes to “H”. DZF pin of each channel immediately goes to “L” if input
data of each channel is not zero after going DZF pin “H”. If RSTN bit is “0”, DZF pins of both channels go to “H”. DZF
pins of both channels go to “L” at 4 ~ 5/fs after RSTN bit returns to “1”. If DZFM bit is set to “1”, DZF pins of both
channels go to “H” only when the input data at both channels are continuously zeros for 8192 LRCK cycles. Zero detect
function can be disabled by DZFE bit. In this case, DZF pins of both channels are always “L”. DZFB bit can invert the
polarity of DZF pin.
„ Soft Mute operation
Soft mute operation is performed at digital domain. When SMUTE pin goes to “H” or SMUTE bit goes to “1”, the output
signal is attenuated by −∞ during ATT_DATA × ATT transition time (Table 13) from the current ATT level. When
SMUTE pin is returned to “L” or SMUTE bit is returned to “0”, the mute is cancelled and the output attenuation gradually
changes to the ATT level during ATT_DATA × ATT transition time. If the soft mute is cancelled before attenuating −∞
after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle. The soft mute is
effective for changing the signal source without stopping the signal transmission.
SM U T E pin or
SM U T E bit
(1)
(1)
AT T _Level
(3)
Attenuation
-∞
GD
(2)
GD
(2)
AO U T
D ZF pin
(4)
8192/fs
Notes:
(1) ATT_DATA × ATT transition time (Table 13). For example, this time is 1020LRCK cycles (1020/fs)
at ATT_DATA=255 in Normal Speed Mode.
(2) Analog output corresponding to digital input has the group delay (GD).
(3) If the soft mute is cancelled before attenuating −∞ after starting the operation, the attenuation is discontinued
and returned to ATT level by the same cycle.
(4) When the input data at each channel is continuously zeros for 8192 LRCK cycles, DZF pin of each channel goes
to “H”. DZF pin immediately goes to “L” if input data are not zero after going DZF pin “H”.
Figure 8. Soft Mute and Zero Detection
„ System Reset
The AK4396 should be reset once by bringing PDN pin = “L” upon power-up. The analog section exits power-down
mode by MCLK input and then the digital section exits power-down mode after the internal counter counts MCLK during
4/fs.
MS0336-E-00
2004/08
- 24 -
ASAHI KASEI
[AK4396]
„ Power-Down
The AK4396 is placed in the power-down mode by bringing PDN pin “L” and the anlog outputs are floating (Hi-Z).
Figure 9 shows an example of the system timing at the power-down and power-up.
PDN
Internal
State
Normal Operation
Power-down
D/A In
(Digital)
Normal Operation
“0” data
GD
D/A Out
(Analog)
(1)
GD
(2)
(3)
(3)
(1)
(4)
Clock In
Don’t care
MCLK, BICK, LRCK
DZFL/DZFR
External
MUTE
(6)
(5)
Mute ON
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs are floating (Hi -Z) at the power-down mode.
(3) Click noise occurs at the edge (“↑ ↓”) of PDN signal. This noise is output even if “0” data is input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN pin = “L”).
(5) Please mute the analog output externally if the click noise (3) influences system application.
The timing example is shown in this figure.
(6) DZF pins are “L” in the power-down mode (PDN pin = “L”).
Other:
After exiting power-down mode (PDN pin: “L” Æ “H”), AOUT pins go to VCOM voltage (VA/2). This time is set
by a capacitor connected to VCOM pin and the internal resistor of VCOM pin.
E.g. C = 10µF
1 τ (typ) = 10µF x 0.75kΩ = 7.5ms, 5τ (typ) = 37.5ms
1 τ (max) = 10µF x 0.975kΩ = 9.75ms, 5τ (max) = 48.75ms
Figure 9. Power-down/up sequence example
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ASAHI KASEI
[AK4396]
„ Reset Function
When RSTN bit = “0”, the AK4396’s digital section is powered down but the internal register values are not initialized.
The analog outputs go to VCOM voltage and DZF pins of both channels go to “H”. Figure 10 shows the example of reset
by RSTN bit.
RSTN bit
3~4/fs (6)
2~3/fs (6)
Internal
RSTN Timing
Internal
State
Normal Operation
P
D/A In
(Digital)
d
“0” data
(1)
D/A Out
(Analog)
Normal Operation
Digital Block
GD
GD
(3)
(2)
(3)
(1)
(4)
Clock In
Don’t care
MCLK, BICK, LRCK
2/fs(5)
DZFL/DZFR
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs go to VCOM voltage.
(3) Click noise occurs at the edges (“↑ ↓”) of the internal timing of RSTN bit.
This noise is output even if “0” data is input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode (RSTN bit = “L”).
(5) DZF pins go to “H” when the RSTN bit becomes “0”, and go to “L” at 2/fs after RSTN bit becomes “1”.
(6) There is a delay, 3 ~ 4/fs from RSTN bit “0” to the internal RSTN bit “0”, and 2 ~ 3/fs from RSTN bit “1”
to the internal RSTN bit “1”.
Figure 10. Reset sequence example
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ASAHI KASEI
[AK4396]
„ Register Control Interface
Pins (parallel control mode) or registers (serial control mode) can control each functions of the AK4396. In parallel mode,
the register setting is ignored and the pin setting is ignored in serial mode. When the state of P/S pin is changed, the
AK4396 should be reset by PDN pin. The serial control interface is enabled by the P/S pin = “L”. In this mode, pin setting
must be all “L”. Internal registers may be written by 3-wire µP interface pins: CSN, CCLK and CDTI. The data on this
interface consists of Chip address (2bits, CAD0/1), Read/Write (1bit; fixed to “1”), Register address (MSB first, 5bits)
and Control data (MSB first, 8bits). The AK4396 latches the data on the rising edge of CCLK, so data should be clocked
in on the falling edge. The writing of data becomes valid by CSN “↑”. The clock speed of CCLK is 5MHz (max).
Function
Parallel mode
Serial mode
Auto Setting Mode
O
O
Manual Setting Mode
O
O
Audio Format
O
O
De-emphasis
O
O
SMUTE
O
O
DSD Mode
X
O
Zero Detection
X
O
Slow roll-off response
X
O
Digital Attenuator
X
O
Table 14. Function List (O: Available, X: Not available)
PDN pin = “L” resets the registers to their default values. In serial mode, the internal timing circuit is reset by RSTN bit,
but the registers are not initialized.
CSN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
Chip Address (C1=CAD1, C0=CAD0)
R/W:
READ/WRITE (Fixed to “1”, Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 11. Control I/F Timing
* The AK4396 does not support the read command.
* When the AK4396 is in the power down mode (PDN pin = “L”) or the MCLK is not provided, writing into the control
register is inhibited.
* The control data can not be written when the CCLK rising edge is 15times or less or 17times or more during CSN is “L”.
MS0336-E-00
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ASAHI KASEI
[AK4396]
„ Register Map
Addr
00H
01H
02H
03H
04H
Register Name
Control 1
Control 2
Control 3
Lch ATT
Rch ATT
D7
ACKS
DZFE
D/P
ATT7
ATT7
D6
0
DZFM
DSDM
ATT6
ATT6
D5
0
SLOW
DCKS
ATT5
ATT5
D4
0
DFS1
DCKB
ATT4
ATT4
D3
DIF2
DFS0
0
ATT3
ATT3
D2
DIF1
DEM1
DZFB
ATT2
ATT2
D1
DIF0
DEM0
0
ATT1
ATT1
D0
RSTN
SMUTE
0
ATT0
ATT0
Notes:
For addresses from 05H to 1FH, data must not be written.
When PDN pin goes to “L”, the registers are initialized to their default values.
When RSTN bit goes to “0”, the only internal timing is reset and the registers are not initialized to their default values.
When the state of P/S pin is changed, the AK4396 should be reset by PDN pin.
„ Register Definitions
Addr Register Name
00H Control 1
Default
D7
ACKS
0
D6
0
0
D5
0
0
D4
0
0
D3
DIF2
0
D2
DIF1
1
D1
DIF0
0
D0
RSTN
1
RSTN: Internal timing reset
0 : Reset. All registers are not initialized.
1 : Normal Operation (Default)
When the states of DFS1-0 bits change, the AK4396 should be reset by PDN pin or RSTN bit.
DIF2-0: Audio data interface modes (see Table 11)
Initial value is “010” (Mode 2: 24bit MSB justified).
ACKS: Master Clock Frequency Auto Setting Mode Enable (PCM only)
0 : Disable : Manual setting mode (Default)
1 : Enable : Auto setting mode
When ACKS bit = “1”, MCLK frequency and the sampling frequency are detected automatically.
MS0336-E-00
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ASAHI KASEI
Addr Register Name
01H Control 2
Default
[AK4396]
D7
DZFE
0
D6
DZFM
0
D5
SLOW
0
D4
DFS1
0
D3
DFS0
0
D2
DEM1
0
D1
DEM0
1
D0
SMUTE
0
SMUTE: Soft Mute Enable
0 : Normal operation (Default)
1 : DAC outputs soft-muted.
DEM1-0: De-emphasis response (Table 12)
Initial value is “01” (OFF).
DFS1-0:
Sampling Speed Control (Table 6)
Initial value is “00” (Normal speed).
When changing between Normal/Double Speed Mode and Quad Speed Mode, some click noise occurs at
that time.
SLOW:
Slow Roll-off Filter Enable
0 : Sharp roll-off filter (Default)
1 : Slow roll-off filter
DZFM:
Data Zero Detect Mode
0 : Channel separated mode (Default)
1 : Channel ANDed mode
If the DZFM bit is set to “1”, the DZF pins of both channels go to “H” only when the input data at both
channels are continuously zeros for 8192 LRCK cycles.
DZFE:
Data Zero Detect Enable
0 : Disable (Default)
1 : Enable
Zero detect function can be disabled by DZFE bit “0”. In this case, the DZF pins of both channels are
always “L”.
MS0336-E-00
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ASAHI KASEI
Addr Register Name
02H Control 3
Default
[AK4396]
D7
D/P
0
D6
DSDM
0
D5
DCKS
0
D4
DCKB
0
D3
0
0
D2
DZFB
0
D1
0
0
D0
0
0
D2
ATT2
ATT2
1
D1
ATT1
ATT1
1
D0
ATT0
ATT0
1
DZFB: Inverting Enable of DZF
0 : DZF pin goes “H” at Zero Detection (Default)
1 : DZF pin goes “L” at Zero Detection
DCKB: Polarity of DCLK (DSD Only)
0 : DSD data is output from DCLK falling edge. (Default)
1 : DSD data is output from DCLK rising edge.
DCKS: Master Clock Frequency Select at DSD mode (DSD only)
0 : 512fs (Default)
1 : 768fs
DSDM: DSD Input Select
0 : Input pin : No.5, 6, 7 (Default)
1 : Input pin : No. 12, 13, 14
When DSDM bit is changed, the AK4396 should be reset by RSTN bit.
D/P:
DSD/PCM Mode Select
0 : PCM mode (Default)
1 : DSD mode
When D/P bit is changed, the AK4396 should be reset by RSTN bit.
Addr Register Name
03H Lch ATT
04H Rch ATT
Default
D7
ATT7
ATT7
1
D6
ATT6
ATT6
1
D5
ATT5
ATT5
1
D4
ATT4
ATT4
1
D3
ATT3
ATT3
1
ATT7-0: Attenuation Level
ATT = 20 log10 (ATT_DATA / 255) [dB]
FFH : 0dB (Default)
00H : Mute
MS0336-E-00
2004/08
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ASAHI KASEI
[AK4396]
SYSTEM DESIGN
Figure 12, Figure 13 and Figure 14 show the system connection diagram. Figure 16 , Figure 17 and Figure 18 show the
analog output circuit examples. An evaluation board (AKD4396) is available which demonstrates the optimum layout,
power supply arrangements and measurement results.
Digital
Supply 3.3V
10u 0.1u
1
DVSS
DZFR
28
2
DVDD
CAD1
27
3
MCLK
DZFL
26
Reset & Power down
4
PDN
P/S
25
64fs
5
BICK
VCOM
24
24bit Audio Data
6
SDATA
AOUTL+
23
Lch
Lch
7
LRCK
AOUTL-
22
LPF
Mute
Rch
LPF
Rch
Mute
+
Master Clock
fs
AK4396
8
CSN
AOUTR+
21
Micro-
9
CAD0
AOUTR-
20
controller
10
CCLK
AVSS
11
CDTI
AVDD
12
DIF0
VREFH
13
DIF1
VREFL
14
DIF2
TTL
Digital Ground
0.1u
19
0.1u
18
10u
+
17
0.1u
16
+
10u
10u
+
Lch Out
Rch Out
Analog
Supply 5V
15
Analog Ground
Notes:
- Chip Address = “00”. LRCK = fs, BICK = 64fs.
- Power lines of AVDD and DVDD should be distributed separately from the point with low impedance of regulator
etc.
- AVSS and DVSS must be connected to the same analog ground plane.
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and
capacitive load.
- All input pins except pull-down/pull-up pins should not be left floating.
Figure 12. Typical Connection Diagram (AVDD=5V, DVDD=3.3V, Serial mode)
MS0336-E-00
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ASAHI KASEI
[AK4396]
Digital
Supply 3.3V
10u 0.1u
1
DVSS
ACKS
28
2
DVDD
TST2
27
Master Clock
3
MCLK
TST1
26
Reset & Power down
4
PDN
P/S
25
64fs
5
BICK
VCOM
24
24bit Audio Data
6
SDATA
AOUTL+
23
Lch
7
LRCK
AOUTL-
22
LPF
8
SMUTE
AOUTR+
21
9
DFS0
AOUTR-
20
Rch
LPF
10
DEM0
AVSS
11
DEM1
AVDD
12
DIF0
VREFH
13
DIF1
VREFL
14
DIF2
TTL
+
fs
Mode
setting
Digital Ground
AK4396
0.1u
19
0.1u
18
+ 10u
17
0.1u
16
+
10u
10u
+
Lch Out
Rch Out
Analog
Supply 5V
15
Analog Ground
Notes:
- BICK = 64fs, LRCK = fs.
- Power lines of AVDD and DVDD should be distributed separately from the point with low impedance of regulator
etc.
- AVSS and DVSS must be connected to the same analog ground plane.
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and
capacitive load.
- All input pins except pull-down/pull-up pins should not be left floating.
Figure 13. Typical Connection Diagram (AVDD = 5V, DVDD = 3.3V, Parallel mode, AK4393 compatible)
MS0336-E-00
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ASAHI KASEI
[AK4396]
Digital
Supply 5.0V
10u 0.1u
1
DVSS
DZFR
28
2
DVDD
CAD1
27
Master Clock
3
MCLK
DZFL
26
Reset & Power down
4
PDN
P/S
25
64fs
5
BICK
VCOM
24
24bit Audio Data
6
SDATA
AOUTL+
23
Lch
Lch
7
LRCK
AOUTL-
22
LPF
Mute
8
CSN
AOUTR+
21
Micro-
9
CAD0
AOUTR-
20
Rch
LPF
Rch
Mute
controller
10
CCLK
AVSS
11
CDTI
AVDD
12
DIF0
VREFH
13
DIF1
VREFL
14
DIF2
TTL
+
fs
Digital Ground
AK4396
0.1u
19
0.1u
18
10u
+
17
0.1u
16
+
10u
10u
+
Lch Out
Rch Out
Analog
Supply 5V
15
Analog Ground
Notes:
- TTL pin (BVSS pin in case of AK4394/5) should be open.
- Chip Address = “00”, BICK = 64fs, LRCK = fs.
- Power lines of AVDD and DVDD should be distributed separately from the point with low impedance of regulator
etc.
- AVSS and DVSS must be connected to the same analog ground plane.
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and
capacitive load.
- All input pins except pull-down/pull-up pins should not be left floating.
Figure 14. Typical Connection Diagram (AVDD=5V, DVDD=5V, Serial mode, AK4394/5 compatible)
Digital Ground
Analog Ground
System
Controller
1
DVSS
DZFR
28
2
DVDD
CAD1
27
3
MCLK
DZFL
26
4
PDN
P/S
25
5
BICK
VCOM
24
6
SDATA
AOUTL+
23
7
LRCK
AOUTL-
22
8
CSN
AOUTR+
21
9
CAD0
AOUTR-
20
10
CCLK
AVSS
19
11
CDTI
AVDD
18
12
DIF0
VREFH
17
13
DIF1
VREFR
16
14
DIF2
TTL
15
AK4396
Figure 15. Ground Layout
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ASAHI KASEI
[AK4396]
1. Grounding and Power Supply Decoupling
To minimize coupling by digital noise, decoupling capacitors should be connected to AVDD and DVDD, respectively.
AVDD is supplied from analog supply in system and DVDD is supplied from digital supply in system. Power lines of
AVDD and DVDD should be distributed separately from the point with low impedance of regulator etc. The power up
sequence between AVDD and DVDD is not critical. AVSS and DVSS must be connected to analog ground
plane. Decoupling capacitors for high frequency should be placed as near as possible.
2. Voltage Reference
The differential Voltage between VREFH and VREFL set the analog output range. VREFH pin is normally connected to
AVDD and VREFL pin is normally connected to AVSS. VREFH and VREFL should be connected with a 0.1µF ceramic
capacitor. VCOM is a signal ground of this chip. An electrolytic capacitor 10µF parallel with a 0.1µF ceramic capacitor
attached to VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from VCOM pin. All
signals, especially clocks, should be kept away from the VREFH, VREFL and VCOM pins in order to avoid unwanted
coupling into the AK4396.
3. Analog Outputs
The analog outputs are full differential outputs and 2.8Vpp (typ, VREFH − VREFL = 5V) centered around VCOM. The
differential outputs are summed externally, VAOUT = (AOUT+) − (AOUT−) between AOUT+ and AOUT−. If the
summing gain is 1, the output range is 5.6Vpp (typ, VREFH − VREFL = 5V). The bias voltage of the external summing
circuit is supplied externally. The input data format is 2's complement. The output voltage (VAOUT) is a positive full scale
for 7FFFFFH (@24bit) and a negative full scale for 800000H (@24bit). The ideal VAOUT is 0V for 000000H(@24bit).
The internal switched-capacitor filters attenuate the noise generated by the delta-sigma modulator beyond the audio
passband. Figure 16 shows an example of external LPF circuit summing the differential outputs by an op-amp.
Figure 17 shows an example of differential outputs and LPF circuit example by three op-amps.
AK4396
AOUT-
2.4k
2.4k
150
680p
+Vop
AOUT+
3.3n
2.4k
2.4k
Analog
Out
150
680p
-Vop
Figure 16. External LPF Circuit Example 1 for PCM (fc = 125kHz, Q=0.692)
Frequency Response
Gain
20kHz
−0.012dB
40kHz
−0.083dB
80kHz
−0.799dB
Table 15. Filter Response of External LPF Circuit Example 1 for PCM
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ASAHI KASEI
[AK4396]
+15
3.3n
+
AOUTL- +
10k
330
180
0.1u
7
3
2 +
4
3.9n
-15
10u
6
NJM5534D
+
10u
0.1u
620
620
3.3n
+
100u
180
3.9n
100
6
Lch
1.0n NJM5534D
10u
6
NJM5534D
1.2k
10k
330
2 - 4
+
3
7
0.1u
7
3
+
2 4
AOUTL+ +
+10u
1.0n
1.2k
680
0.1u
560
560
100u
680
+
0.1u
10u
+
10u
0.1u
Figure 17. External LPF Circuit Example 2 for PCM
2nd Stage
Total
1st Stage
Cut-off Frequency
182kHz
284kHz
Q
0.637
Gain
+3.9dB
-0.88dB
+3.02dB
20kHz
-0.025
-0.021
-0.046dB
Frequency
40kHz
-0.106
-0.085
-0.191dB
Response
80kHz
-0.517
-0.331
-0.848dB
Table 16. Filter Response of External LPF Circuit Example 2 for PCM
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ASAHI KASEI
[AK4396]
It is recommended by SACD format book (Scarlet Book) that the filter response at SACD playback is an analog low pass
filter with a cut-off frequency of maximum 50kHz and a slope of minimum 30dB/Oct. The AK4396 can achieve this filter
response by combination of the internal filter (Table 17) and an external filter (Figure 18).
Frequency
Gain
20kHz
−0.4dB
50kHz
−2.8dB
100kHz
−15.5dB
Table 17. Internal Filter Response at DSD mode
2.0k
1.8k
4.3k
AOUT1.0k
270p
2.8Vpp
2200p
+Vop
3300p
2.0k
1.8k
1.0k
AOUT+
+
2.8Vpp
4.3k
270p
Analog
Out
6.34Vpp
-Vop
Figure 18. External 3rd order LPF Circuit Example for DSD
Frequency
Gain
20kHz
−0.05dB
50kHz
−0.51dB
100kHz
−16.8dB
DC gain = 1.07dB
Table 18. 3rd order LPF (Figure 18) Response
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ASAHI KASEI
[AK4396]
PACKAGE
28pin VSOP (Unit: mm)
*9.8±0.2
1.25±0.2
0.675
28
A
7.6±0.2
*5.6±0.2
15
14
1
0.65
0.22±0.1
+0.1
0.15-0.05
0.1±0.1
0.5±0.2
Detail A
Seating Plane
| 0.10
NOTE: Dimension "*" does not include mold flash.
0-10°
„ Material & Lead finish
Package molding compound: Epoxy
Lead frame material: Cu
Lead frame surface treatment: Solder (Pb free) plate
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ASAHI KASEI
[AK4396]
MARKING
AKM
AK4396VF
XXXBYYYYC
XXXXBYYYYC: Date code identifier
XXXB:
YYYYC:
Lot number (X : Digit number, B : Alpha character )
Assembly date (Y : Digit number C : Alpha character)
Revision History
Date (YY/MM/DD)
04/08/31
Revision
00
Reason
First Edition
Page
Contents
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering
any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or
authorized distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to customs
and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to
any such use, except with the express written consent of the Representative Director of AKM. As
used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability
for and hold AKM harmless from any and all claims arising from the use of said product in the
absence of such notification.
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