PRELIMINARY CY2037 High Accuracy EPROM Programmable PLL Die for Crystal Oscillators Features Benefits • EPROM-programmable die for in-package programming of crystal oscillators Enables quick turnaround of custom oscillators Lowers inventory costs through stocking of blank parts • High resolution PLL with 12 bit multiplier and 10 bit divider Enables synthesis of highly accurate and stable output clock frequencies with zero or low PPM • EPROM-programmable capacitor tuning array Enables fine-tuning of output clock frequency by adjusting CLoad of the crystal • Twice programmable die Enables reprogramming of programmed part, to correct errors, and control excess inventory • Simple 4-wire programming interface Enables programming of output frequency after packaging • On-chip oscillator runs from 10–30 MHz crystal Lowers cost of oscillator as PLL can be programmed to a high frequency using a low-frequency, low-cost crystal • EPROM-selectable TTL or CMOS duty cycle levels Duty cycle centered at 1.5V or VDD/2 Provides flexibility to service most TTL or CMOS applications • Operating frequency — 1–200 MHz at 5V — 1–100 MHz at 3.3V — 1–66.67 MHz at 2.7V Services most PC, networking, and consumer applications • Sixteen selectable post-divide options, using either PLL or reference oscillator output Provides flexibility in output configurations and testing • Programmable PWR_DWN or OE pin Enables low-power operation or output enable function • Programmable asynchronous or synchronous OE and PWR_DWN modes Provides flexibility for system applications, through selectable instantaneous or synchronous change in outputs • Low Jitter outputs — < ±100ps (pk-pk) at 5V — < ±125ps (pk-pk) at 3.3V Suitable for most PC, consumer, and networking applications • 3.3V or 5V operation Lowers inventory cost as same die services both applications • Small Die Enables encapsulation in small-size, surface mount packages • Controlled rise and fall times and output slew rate Has lower EMI than oscillators CY2037 Logic Block Diagram Die Configuration Top View PWR_DWN or OE XG XD HIGH ACCURACY PLL CRYSTAL VDD 1 AVDD 2 XD 3 XD 4 N/C 5 XG PWR_DWN or OE CONFIGURATION EPROM OSCILLATOR XD 10 CLKOUT 6 9 AVSS 7 8 VSS MUX CLKOUT / 1, 2, 4, 8, 16, 32, 64, 128 Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 December 24, 1997 PRELIMINARY CY2037 Functional Description PLL Output Frequency The CY2037 is an EPROM programmable, high accuracy, PLL-based die designed for the crystal oscillator market. The die attaches directly to a low-cost 10-30MHz crystal and can be packaged into 4-pin through-hole or surface mount packages. The oscillator devices can be stocked as blank parts and custom frequencies programmed in-package at the last stage before shipping. This enables fast-turn manufacture of custom and standard crystal oscillators without the need for dedicated, expensive crystals. The CY2037 contains a high resolution PLL with 12 bit multiplier and 10 bit divider.The output frequency of the PLL is determined by the following formula: 2 • (P + 5 ) F PLL = --------------------------- • F REF (Q + 2) The CY2037 contains an on-chip oscillator and a unique oscillator tuning circuit for fine-tuning of the output frequency. The crystal Cload can be selectively adjusted by programming a set of seven EPROM bits. This feature can be used to compensate for crystal variations or to obtain a more accurate synthesized frequency. where P is the feedback counter value and Q is the reference counter value. P and Q are EPROM programmable values. The CY2037 uses EPROM programming with a simple 2-wire, 4-pin interface that includes V SS and VDD. Clock outputs can be generated up to 200 MHz at 5V or up to 100 MHz at 3.3V. The entire configuration can be reprogrammed one time allowing programmed inventory to be altered or reused. Power Management features The CY2037 contains EPROM programmable PWR_DWN and OE functions. If Powerdown is selected, all active circuitry on the chip is shut down when the control pin goes low. The output is forced to a hard low in this mode and the oscillator and PLL circuits must re-lock when the part leaves the Powerdown mode. If Output Enable mode is selected, the output is three-stated when the Control pin goes low. In this mode the oscillator and PLL circuits continue to operate, allowing a rapid return to normal operation when the Control input is deasserted. The CY2037 PLL die has been designed for very high resolution. It has a 12 bit feedback counter multiplier and a 10 bit reference counter divider. This enables the synthesis of highly accurate and stable output clock frequencies with zero or low PPM. The clock can be further modified by eight output divider options of 1, 2, 4, 8, 16, 32, 64 and 128. The divider input can be selected as either the PLL or crystal oscillator output providing a total of sixteen separate output options. For further flexibility, the ouput is selectable between TTL and CMOS duty cycle levels. In addition, the PWR_DWN and OE modes can be programmed to occur synchronously or asynchronously with respect to the output signal. When the asynchronous setting is used, the powerdown or output three-state occurs immediately (allowing for logic delays) irrespective of position in the clock cycle. However, when the synchronous setting is used, the part waits for a falling edge at the output before powerdown or output enable is initiated, thus preventing output glitches. The CY2037 also contains flexible power management control. The part includes both PWR_DWN and OE features with integrated pull-up resistors. The PWR_DWN and OE modes have an additional setting to determine timing (asynchronous or synchronous) with respect to the output signal. Controlled rise and fall times, unique output driver circuits, and innovative circuit layout techniques enable the CY2037 to have low jitter and accurate outputs making it suitable for most PC, networking and consumer applications Crystal Oscillator Tuning Circuit The CY2037 contains a unique tuning circuit to fine-tune the output frequency of the device. The tuning circuit consists of an array of seven load capacitors on the input side of the oscillator drive inverter. The capacitor load values are EPROM programmable and can be increased in small increments. As the capacitor load is increased the circuit is fine-tuned to a lower frequency. The capacitor load values vary from 0.17pF to 8 pF for a 100:1 total control ratio. The tuning increments are shown in the table below EPROM Configuration Block The following table summarizes the features which are configurable by EPROM. Please refer to the “CY2037 Programming Specification” for further details. The specification can be obtained from your local Cypress representative. Table 1. Crystal Tuning Increments EPROM Adjustable Features +8pF +4.2pF +2.2pF +1.2pF +0.6pF +0.3pF +0.17pF Feedback counter value (P) Reference counter value (Q) Output divider selection Oscillator Tuning (load capacitance values) Duty cycle levels (TTL or CMOS) Power management mode (OE or PWR_DWN) Power management timing (synchronous or asynchronous) 2 PRELIMINARY CY2037 Die Pad Summary Name Die Pad Description VDD 1 Digital voltage supply AVDD 2 Analog voltage supply, 3.3V or 5V VSS 8 Digital Ground AVSS 9 Analog Ground XD 3,4 Crystal connection, drain pad. Bond to crystal drain. XG 6 Crystal connection, gate pad. Bond to crystal gate. PWR_DWN / OE 7 EPROM programmable power down or output enable pad. Serves as VPP in programming mode. CLKOUT 10 Clock output. Also serves as three-state input during programming. N/C 5 No Connect. Do not connect. Device Functionality: Output Frequencies Symbol Fo Description Output frequency Condition Min. Max. Unit VDD = 4.5–5.5V 1 200 MHz VDD = 3.0–3.6V 1 100 MHz VDD = 2.7–3.6V 1 66 MHz Crystal Oscillator Tuning Circuit Rf CRYSTAL LOCATED EXTERNAL TO DIE C6 C5 C4 C3 C2 C1 C0 Cg T6 CD6 T5 CD5 Symbol T4 CD4 T3 CD3 Description T2 CD2 T1 CD1 Min T0 CD = EPROM BIT T = TRANSISTOR C = LOAD CAPACITOR CD0 Typ Max Unit Rf Feedback resistor, VDD = 4.5–5.5V Feedback resistor, VDD = 3.0–3.6V 0.5 1.0 2 4 3.5 9.0 MΩ MΩ Cg Gate capacitor 6.4 8 9.6 pF Cd Drain Capacitor 12 15 18 pF C0 Series Cap 0.14 0.17 0.20 pF C1 Series Cap 0.26 0.32 0.38 pF C2 Series Cap 0.49 0.61 0.73 pF C3 Series Cap 0.93 1.16 1.39 pF C4 Series Cap 1.77 2.21 2.65 pF C5 Series Cap 3.36 4.2 5.04 pF C6 Series Cap 6.4 8 9.6 pF 3 Cd PRELIMINARY CY2037 Absolute Maximum Ratings Storage Temperature (Non-Condensing)... –55°C to +150°C (Above which the useful life may be impaired. For user guidelines, not tested.) Junction Temperature ............................... –55°C to +150°C Supply Voltage..................................................–0.5 to +7.0V Static Discharge Voltage ........................................... >2000V (per MIL-STD-883, Method 3015) Input Voltage.............................................. –0.5V to VDD+0.5 Operating Conditions Parameter Description Min. Max. Unit AVDD, VDD Analog and Digital Supply Voltage 2.7 5.5 V TAJ  Operating Temperature, Junction –40 +100 °C CTTL Max. Capacitive Load on outputs for TTL levels VDD = 4.5–5.5V, Output frequency = 1–40 MHz VDD = 4.5–5.5V, Output frequency = 40–125 MHz VDD = 4.5–5.5V, Output frequency = 125–200 MHz 50 25 15 pF pF pF CCMOS Max. Capacitive Load on outputs for CMOS levels VDD = 4.5–5.5V, Output frequency = 1–66.6 MHz VDD = 4.5–5.5V, Output frequency = 66.6–125 MHz VDD = 4.5–5.5V, Output frequency = 125–200 MHz VDD = 3.0–3.6V, Output frequency = 1–50 MHz VDD = 3.0–3.6V, Output frequency = 50–100 MHz VDD = 2.7–3.6V, Output frequency = 1–66.6 MHz 50 25 15 30 15 15 pF pF pF pF pF pF XREF Reference Frequency, input crystal 30 MHz 10 Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Typ. Max. Unit 0.8 0.2VDD 0.2VDD V V V VIL Low-level Input Voltage VDD = 4.5–5.5V VDD = 3.0–3.6V VDD = 2.7–3.6V VIH High-level Input Voltage VDD = 4.5–5.5V VDD = 3.0–3.6V VDD = 2.7–3.6V VOL Low-level Output Voltage VDD = 4.5–5.5V, IOL= 16 mA VDD = 3.0–3.6V, IOL= 8 mA VDD = 2.7–3.6V, IOL= 8 mA VOHCMOS High-level Output Voltage, CMOS levels VDD = 4.5–5.5V, IOH= –16 mA VDD = 3.0–3.6V, IOH= –8 mA VDD = 2.7–3.6V, IOH= –8 mA VDD–0.4 VDD–0.4 VDD–0.4 V V V VOHTTL High-level Output Voltage, TTL levels VDD = 4.5–5.5V, IOH= –16 mA 2.4 V IIL Input Low Current VIN = 0V 10 µA IIH Input High Current VIN = VDD 5 µA IDD Power Supply Current, Unloaded VDD = 4.5–5.5V, Output frequency <= 200 MHz VDD = 3.0–3.6V, Output frequency <= 100 MHz VDD = 2.7–3.6V, Output frequency <= 66.6 MHz 45 25 20 mA mA mA IDDS Stand-by current VDD = 4.5–5.5V VDD = 3.0–3.6V VDD = 2.7–3.6V 10 2 2 50 20 20 µA µA µA Rup Input pull-Up resistor VDD = 4.5–5.5V, VIN = 0V VDD = 4.5–5.5V, VIN = 0.7VDD 3.0 30 8.0 100 MΩ kΩ 2.0 0.5VDD 0.5VDD Note: 1. This product is sold in die form so operating conditions are specified for the die, or junction temperature 4 V V V 0.4 0.4 0.4 1.1 15 V V V PRELIMINARY CY2037 Output Clock Switching Characteristics Over the Operating Range Max Unit t1w Symbol Output Duty Cycle at 1.4V, VDD = 4.5–5.5V t1w = t1A ÷ t1B Description 1–27 MHz, C L <= 50 pF 27–80 MHz, CL <= 15pF 27–125 MHz, CL <= 25pF 125–200 MHz, CL <= 15pF Test Conditions Min 45 45 40 40 Typ 55 55 60 60 % % % % t1x Output Duty Cycle at VDD/2, VDD = 4.5–5.5V t1x = t1A ÷ t1B 1–66.6 MHz, CL <= 50 pF 66.6–125 MHz, CL <= 25 pF 125–200 MHz, CL <= 15pF 45 40 40 55 60 60 % % % t1y Output Duty Cycle at VDD/2, VDD = 3.0–3.6 t1y = t1A ÷ t1B 1–50 MHz, C L <= 30 pF 50–100 MHz, CL <= 15pF 45 40 55 60 % % t1z Output Duty Cycle at VDD/2, VDD = 2.7–3.6V t1z = t1A ÷ t1B 1–40 MHz, C L <= 15 pF 40–66.6 MHz, C L <= 15 pF 45 40 55 60 % % t2 Output Clock Rise time Between 0.8 –2.0V, VDD = 4.5V–5.5V, CL = 50 pF Between 0.8 –2.0V, VDD = 4.5V–5.5V, CL = 25 pF Between 0.8 –2.0V, VDD = 4.5V–5.5V, CL = 15 pF Between 0.2VDD– 0.8VDD, VDD= 4.5V–5.5V, CL = 50 pF Between 0.2VDD– 0.8VDD, VDD= 3.0V–3.6V, CL = 30 pF Between 0.2VDD– 0.8VDD, VDD= 3.0V–3.6V, CL = 15 pF Between 0.2VDD– 0.8VDD, VDD= 2.7V–3.6V, CL = 15 pF 1.8 1.2 0.9 3.4 4.0 2.4 4.0 ns ns ns ns ns ns ns t3 Output Clock Fall time Between 0.8V–2.0V, VDD = 4.5V–5.5V, C L = 50 pF Between 0.8 –2.0V, VDD = 4.5V–5.5V, CL = 25 pF Between 0.8 –2.0V, VDD = 4.5V–5.5V, CL = 15 pF Between 0.2VDD– 0.8VDD, VDD= 4.5V-5.5V, C L = 50 pF Between 0.2VDD– 0.8VDD, VDD= 3.0V–3.6V, CL = 30 pF Between 0.2VDD– 0.8VDD, VDD= 3.0V–3.6V, CL = 15 pF Between 0.2VDD– 0.8VDD, VDD= 2.7V–3.6V, CL = 15 pF 1.8 1.2 0.9 3.4 4.0 2.4 4.0 ns ns ns ns ns ns ns t4 Start-up time out of power-down PWR_DWN or OE pin LOW to HIGH  1 2 ms t5a Power Down delay time PWR_DWN pin HIGH to output LOW (synchronous setting) (T=frequency oscillator period) T/2 T+10 ns t5b Power Down delay time PWR_DWN pin HIGH to output LOW (asynchronous setting) 10 15 ns t6 Power Up time From power on 1 2 ms t7a Output disable time (synchronous setting) OE pin HIGH to output Hi-Z (T=frequency oscillator period) T/2 T+10 ns t7b Output disable time (asynchronous setting) OE pin HIGH to output Hi-Z 10 15 ns t8 Output enable time PWR_DWN or OE pin LOW to HIGH 100 ns t9 Peak-to-Peak Period Jitter VDD= 4.5V–5.5V, Fo > 33 MHz, VCO > 100 MHz VDD= 3.0V–3.6V, Fo > 33 MHz, VCO >100 MHz VDD= 3.0V–5.5V, Fo <33 MHz ±100 ±125 ±250 ps ps ps ±50 ±75 ±100 Note: 2. Oscillator start time cannot be guaranteed for all crystal types. This specification is for operation with AT cut crystals with ESR < 70 ohms. 5 PRELIMINARY CY2037 Switching Waveforms Duty Cycle Timing (t1w, t1x, t1y, t1z) t1A OUTPUT t1B Output Rise/Fall Time VDD OUTPUT 0V t3 t2 Power Down Timing (synchronous and asynchronous modes) POWER DOWN VDD VIH VIL 0V t4 CLKOUT (synchronous) T t5a 1/f CLKOUT (asynchronous) t5b 1/f Power Up Timing VDD POWER UP 0V VDD-10% t6 min 2ns CLKOUT 1/f Notes: 3. In synchronous mode the powerdown or output 3-state is not initiated until the next falling edge of the output clock. 4. In asynchronous mode the powerdown or output 3-state occurs within 25ns irrespective of position in the ouput clock cycle. 6 PRELIMINARY CY2037 Switching Waveforms (continued) Output Enable Timing (synchronous and asynchronous modes) VDD OUTPUT ENABLE VIH VIL 0V T CLKOUT (synchronous) High Impedance t7a CLKOUT (asynchronous) t8 High Impedance t7b Ordering Information t8 Die Size Dimensions Ordering Code Type Operating Range x by y 1497x1105 microns CY2037WAF Wafer Industrial Wafer Thickness 14 ±0.5 mils Document #: 38–00679 © Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.