65A CYM1465A 512K x 8 PDIP Static RAM Features • • • • • • • • an automatic power-down feature that reduces power consumption by more than 99% when deselected. 4.5V–5.5V operation CMOS SRAM for optimum speed and power Low active power (165 mW max.) Low standby power (L Version)—(110 µW max) 2V data retention (L Version) JEDEC-compatible pinout 32-pin, 0.6-inch-wide DIP package TTL-compatible inputs and outputs Functional Description The CYM1465A is a high-performance CMOS static RAM organized as 512K words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE), an active LOW Output Enable (OE), and three-state drivers. This device has Writing to the SRAM is accomplished when the chip select (CS) and write enable (WE) inputs are both LOW. Data on the eight input/output pins (I/O0 through I/O7) of the device is then written into the memory location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking chip select (CE) and output enable (OE) LOW while write enable (WE) remains inactive or HIGH. Under these conditions, the contents of the memory location specified on the address pins (A0 through A18) will appear on the eight appropriate data input/output pins (I/O0 through I/O7).The eight input/output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CYM1465A is available in a 32-pin 600-mil wide body PDIP package. Logic Block Diagram Pin Configuration DIP Top View A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND I/O0 INPUT BUFFER I/O1 ROW DECODER I/O2 512 x 256 x 8 ARRAY SENSE AMPS A0 A1 A4 A5 A6 A7 A12 A14 A16 A17 I/O3 I/O4 I/O5 COLUMN DECODER CE 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 VCC A15 A17 WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 I/O6 POWER DOWN I/O7 A2 A3 A 15 A18 A13 A8 A9 A11 A 10 WE OE 1S Selection Guide CYM1465A-70 CYM1465A-85 Maximum Access Time (ns) 70 85 Maximum Operating Current (mA) 20 20 Maximum Standby Current (µA) 20 20 Cypress Semiconductor Corporation Document #: 38-05269 Rev. ** • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised March 15, 2002 CYM1465A Maximum Ratings DC Input Voltage .............................................-0.5V to +7.0V (Above which the useful life may be impaired.) Operating Range Storage Temperature ................................. –55°C to +150°C Range Ambient Temperature with Power Applied............................................... –10°C to +85°C Commercial Supply Voltage to Ground Potential ............... –0.5V to +7.0V Industrial Ambient Temperature VCC 0°C to +70°C 5V ± 10% –40°C to +85°C 5V ± 10% DC Voltage Applied to Outputs in High Z State ............................................... –0.5V to +7.0V Electrical Characteristics Over the Operating Range CYM1465A Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = – 1.0 mA VOL Output LOW Voltage VCC = Min., IOL = 2.1 mA VIH Input HIGH Voltage VIL Input LOW Voltage IIX Input Load Current GND < VI < VCC IOZ Output Leakage Current GND < VO < VCC, Output Disabled ICC VCC Operating Supply Current ISB1 ISB2 Min. Max. Unit 2.4 V 0.4 V 2.2 VCC + 0.3 V –0.3 0.8 V –1 +1 µA –1 +1 µA VCC = Max., IOUT = 0 mA, CS < VIL 20 mA Automatic CS Power-Down Current Max. VCC, CE > VIH, Min. Duty Cycle = 100% 1.5 mA Automatic CS Power-Down Current Max. VCC, CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V 20 µA Capacitance[1] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. Unit 8 pF 10 pF AC Test Loads and Waveforms 1.847 kΩ 5V 5V OUTPUT 1.847 k Ω ALL INPUT PULSES 3.0V 90% OUTPUT CL INCLUDING JIG AND SCOPE Equivalent to: [2] 1 kΩ 5 pF INCLUDING JIG AND SCOPE (a) 1 kΩ 10% GND < 10 ns 90% 10% <10 ns (b) THÉVENIN EQUIVALENT 648Ω OUTPUT 1.76V Notes: 1. Tested on a sample basis. 2. Test conditions assume signal transition times of 10 ns or less, timing reference levels of 1.5V, input levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 100-pF load capacitance for 85-, 100-, 120-, and 150-ns speeds. CL = 30 pF for 70-ns speed. Document #: 38-05269 Rev. ** Page 2 of 7 CYM1465A Switching Characteristics Over the Operating Range[2] Parameter Description CYM1465A-70 CYM1465A-85 Min. Min. Max. Max. Unit READ CYCLE tRC Read Cycle Time 70 tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to Low Z 85 70 10 85 OE HIGH to High Z tLZCS CE LOW to Low Z CE HIGH to High Z tPU CE LOW to Power Down tPD CE HIGH to Power Down ns 45 ns ns 25 [3] 85 5 10 tHZCS ns 35 [3] ns 10 70 5 tHZOE ns 30 ns 10 ns 25 30 0 ns 0 70 85 [4] WRITE CYCLE tWC Write Cycle Time 70 85 ns tSCE CE LOW to Write End 60 75 ns tAW Address Set-Up to Write End 60 75 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-Up to Write Start 0 0 ns tPWE WE Pulse Width 55 65 ns tSD Data Set-Up to Write End 30 35 ns tHD Data Hold from Write End 0 0 ns tLZWE WE HIGH to Low Z 5 tHZWE WE LOW to High Z[3] 5 ns 25 30 ns Data Retention Characteristics Over the Operating Range (L Version Only) Commercial Parameter VDR ICCDR3 tCDR tR[5] Description Test Conditions VCC for Retention Data [5] Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Min. Max. 2 No Input may exceed Vcc+0.3V VDR = 3.0V, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V Industrial Min. Max. 2 20 Unit V 20 µA 0 0 ns tRC tRC ns Notes: 3. CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage. 4. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 5. Guaranteed, not tested. Document #: 38-05269 Rev. ** Page 3 of 7 CYM1465A Data Retention Waveform DATA RETENTION MODE VCC 3.0V 3.0V VDR > 2V tCDR tR VDR VIH CE VIH Switching Waveforms Read Cycle No. 1 [6,7] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 [6,8] tRC CE tACE OE tHZOE tDOE tHZCE tLZOE HIGH IMPEDANCE DATA OUT HIGH IMPEDANCE DATA VALID tLZCS Notes: 6. WE is HIGH for read cycle. 7. Device is continuously selected, CE= VIL. 8. Address valid prior to or coincident with CE transition LOW. Document #: 38-05269 Rev. ** Page 4 of 7 CYM1465A Switching Waveforms (continued) Write Cycle No. 1 (WE Controlled) [4] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATA IN tHD DATA VALID tHZWE tLZWE HIGH IMPEDANCE DATA OUT DATA UNDEFINED [4,9] Write Cycle No. 2 (CE Controlled) tWC ADDRESS tSCE tSA CE tAW tHA tPWE WE tSD DATA IN tHD DATA VALID tHZWE DATA OUT DATA UNDEFINED HIGH IMPEDANCE Note: 9. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. Truth Table Inputs CE WE OE Output Mode H X X High Z Deselect/Power-Down L H L Data Out Read Word L L X Data In Write Word L H H High Z Deselect Document #: 38-05269 Rev. ** Page 5 of 7 CYM1465A Ordering Information Speed (ns) Ordering Code Package Name Operating Range Package Type 70 CYM1465ALPD-70C P19 32-Pin DIP Module Commercial 70 CYM1465ALPD-70I P19 32-Pin DIP Module Industrial 85 CYM1465ALPD-85C P19 32-Pin DIP Module Commercial 85 CYM1465ALPD-85I P19 32-Pin DIP Module Industrial Package Diagram 32-Lead (600-Mil) Molded DIP P19 51-85018-*A Document #: 38-05269 Rev. ** Page 6 of 7 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CYM1465A Revision History Document Title: CYM1465A 512K x 8 PDIP Static RAM Document Number: 38-05269 REV. ECN NO. ISSUE DATE ORIG. OF CHANGE ** 114171 3/19/02 DSG Document #: 38-05269 Rev. ** DESCRIPTION OF CHANGE Change from Spec number: 38-M-00036 to 38-05269 Page 7 of 7