CY7C1009V33 CY7C109V33 128K x 8 Static RAM Features memory expansion is provided by an active LOW Chip Enable (CE1), an active HIGH Chip Enable (CE2), an active LOW Output Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable one (CE1) and Write Enable (WE) inputs LOW and Chip Enable two (CE2) input HIGH. Data on the eight I/O pins (I/O 0 through I/O 7) is then written into the location specified on the address pins (A0 through A16). • High speed — tAA = 15, 20, 25ns • VCC = 3.3V ± 10% • Low active power — 432 mW (max.) — 288 mW (L version) • Low CMOS standby power — 18 mW (max.) • • • • — 7.2 mW (L version) 2.0V Data Retention Automatic power-down when deselected TTL-compatible inputs and outputs Easy memory expansion with CE1, CE2, and OE options Functional Description The CY7C109V33/CY7C1009V33 is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy Reading from the device is accomplished by taking Chip Enable one (CE1) and Output Enable (OE) LOW while forcing Write Enable (WE) and Chip Enable two (CE2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE 2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW). The CY7C109V33 is available in standard 32-pin, 400-mil-wide SOJ package. The CY7C1009V33 is available in a 32-pin, 300-mil-wide SOJ package. The CY7C1009V33 and CY7C109V33 are functionally equivalent in all other respects. Logic Block Diagram Pin Configurations SOJ Top View NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND I/O0 INPUT BUFFER I/O1 ROW DECODER I/O2 SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 512 x 256 x 8 ARRAY I/O3 A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 I/O4 I/O5 COLUMN DECODER CE1 CE2 WE I/O6 I/O7 A9 A 10 A 11 A 12 A 13 A14 A15 A16 OE POWER DOWN 109V33–1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 TSOP I Top View (not to scale) 109V33–2 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 109V33–3 Selection Guide 7C109V33-12 7C109V33-15 7C109V33-20 7C109V33-25 7C1009V33-12 7C1009V33-15 7C1009V33-20 7C1009V33-25 Maximum Access Time (ns) 12 15 20 20 Maximum Operating Current (mA) 130 120 110 110 Maximum Operating Current (mA) Low Power Version 90 80 70 70 Maximum CMOS Standby Current (mA) Standard 5 5 5 5 Maximum CMOS Standby Current (mA) Low Power Version 2 2 2 2 Shaded areas contain preliminary information. Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 September 3, 1999 CY7C1009V33 CY7C109V33 DC Input Voltage ................................. –0.5V to VCC +0.5V Maximum Ratings Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Operating Range Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied ............................................. –55°C to +125°C Range Supply Voltage on VCC to Relative GND .... –0.5V to +7.0V Commercial Ambient Temperature VCC 0°C to +70°C 3.3V ± 300mV DC Voltage Applied to Outputs in High Z State .....................................–0.5V to VCC +0.5V Electrical Characteristics Over the Operating Range Parameter Description Test Conditions 7C109V33-12 7C1009V33-12 7C1009V33-15 7C109V33–15 Min. Min. Max. VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage 2.2 VCC + 0.3 VIL Input LOW Voltage –0.3 IIX Input Load Current GND < VI < VCC IOZ Output Leakage Current GND < VI < VCC, Output Disabled ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC ISB1 Automatic CE Power-Down Current —TTL Inputs ISB2 Automatic CE Power-Down Current —CMOS Inputs 2.4 Max. 2.4 0.4 Unit V 0.4 V 2.2 VCC + 0.3 V 0.8 –0.3 0.8 V –1 +1 –1 +1 µA –5 +5 –5 +5 µA 130 120 mA 90 80 Max. V CC, CE1 > VIH or CE2 < VIL, VIN > V IH or VIN < V IL, f = fMAX 25 20 mA Max. V CC, CE1 > VCC – 0.3V, or CE2 < 0.3V, VIN > V CC – 0.3V, or V IN < 0.3V, f=0 5 5 mA 2 2 L Shaded areas contain preliminary information. Notes: 1. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 2. TA is the case temperature. 2 L CY7C1009V33 CY7C109V33 Electrical Characteristics Over the Operating Range (continued) Parameter Description Test Conditions 7C1009V33-20 7C109V33-20 7C1009V33-25 7C109V33-25 Min. Min. Max. VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage 2.2 VCC + 0.3 VIL Input LOW Voltage –0.3 IIX Input Load Current IOZ Output Leakage Current ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC ISB1 Automatic CE Power-Down Current —TTL Inputs ISB2 Automatic CE Power-Down Current —CMOS Inputs 2.4 Max. Unit 2.4 0.4 V 0.4 V 2.2 VCC + 0.3 V 0.8 –0.3 0.8 V –1 +1 –1 +1 µA –5 +5 –5 +5 µA 110 110 mA 70 70 Max. V CC, CE1 > VIH or CE2 < VIL, VIN > V IH or VIN < V IL, f = fMAX 20 20 mA Max. V CC, CE1 > VCC – 0.3V, or CE2 < 0.3V, VIN > V CC – 0.3V, or V IN < 0.3V, f=0 5 5 mA 2 2 GND < VI < VCC GND < VI < VCC, Output Disabled L L Capacitance Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max. Unit 6 pF 8 pF TA = 25°C, f = 1 MHz, VCC = 3.3V Note: 3. Tested initially and after any design or process changes that may affect these parameters. AC Test Loads and Waveforms ALL INPUT PULSES R1 480Ω R1 480Ω 3V 3.0V 3V OUTPUT 90% OUTPUT 30 pF INCLUDING JIG AND SCOPE (a) R2 255Ω R2 255Ω 5 pF INCLUDING JIG AND SCOPE (b) GND ≤ 3ns 10% 90% 10% ≤ 3 ns 109V33–4 109V33–5 THÉVENIN EQUIVALENT 167Ω 1.73V OUTPUT Equivalent to: 3 CY7C1009V33 CY7C109V33 Switching Characteristics Over the Operating Range 7C1009V33-12 7C1009V33-15 7C1009V33-20 7C1009V33-25 7C109V33-12 7C109V33-15 7C109V33-20 7C109V33-25 Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE1 LOW to Data Valid, CE2 HIGH to Data Valid 12 15 20 20 ns tDOE OE LOW to Data Valid 6 7 8 8 ns tLZOE OE LOW to Low Z tHZOE OE HIGH to High Z[5, 6] 8 ns tLZCE CE1 LOW to Low Z, CE2 HIGH to Low Z 12 15 12 3 20 15 3 0 0 3 tHZCE CE1 HIGH to High Z, CE2 LOW to High Z tPU CE1 LOW to Power-Up, CE2 HIGH to Power-Up tPD CE1 HIGH to Power-Down, CE2 LOW to Power-Down 0 12 ns 0 ns 8 7 3 ns 8 8 0 15 ns 3 3 6 0 20 0 7 3 ns 20 3 6 [5, 6] 20 ns 0 ns 20 20 ns WRITE CYCLE[7,8] tWC Write Cycle Time 12 15 20 20 ns tSCE CE1 LOW to Write End, CE2 HIGH to Write End 10 12 15 15 ns tAW Address Set-Up to Write End 10 12 15 15 ns tHA Address Hold from Write End 0 0 0 0 ns tSA Address Set-Up to Write Start 0 0 0 0 ns tPWE WE Pulse Width 10 12 15 15 ns tSD Data Set-Up to Write End 7 8 10 10 ns tHD Data Hold from Write End 0 0 0 0 ns tLZWE WE HIGH to Low Z 3 3 3 3 ns tHZWE WE LOW to High Z [5, 6] 6 7 8 8 ns Shaded areas contain preliminary information. Data Retention Characteristics Over the Operating Range (L Version Only) Parameter Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR Chip Deselect to Data Retention Time tR Operation Recovery Time Conditions No input may exceed VCC + 0.5V VCC = V DR = 2.0V, CE1 > VCC – 0.3V or CE2 < 0.3V, VIN > VCC – 0.3V or VIN < 0.3V Min. Max 2.0 Unit V 200 µA 0 ns tRC ns Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I OL/IOH and 30-pF load capacitance. 5. t HZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 8. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 4 CY7C1009V33 CY7C109V33 Switching Waveforms Read Cycle No. 1[9, 10] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID 109V33–6 Read Cycle No. 2 (OE Controlled)[10, 11] ADDRESS tRC CE1 CE2 tACE OE tHZOE tDOE DATA OUT tHZCE tLZOE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU ICC 50% 50% ISB 109V33–7 Write Cycle No. 1 (CE1 or CE2 Controlled)[12, 13] tWC ADDRESS tSCE CE1 tSA CE2 tSCE tHA tAW tPWE WE tSD DATA I/O tHD DATA VALID 109V33–8 Notes: 9. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 10. WE is HIGH for read cycle. 11. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH. 12. Data I/O is high impedance if OE = VIH. 13. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state. 5 CY7C1009V33 CY7C109V33 Switching Waveforms (continued) Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[12, 13] tWC ADDRESS tSCE CE1 CE2 tSCE tAW tHA tSA tPWE WE OE tSD DATA I/O tHD DATAIN VALID NOTE 14 tHZOE 109V33–9 Write Cycle No. 3 (WE Controlled, OE LOW) tWC ADDRESS tSCE CE1 CE2 tSCE tAW tSA tHA tPWE WE tSD DATA I/O NOTE 14 tHD DATA VALID tLZWE tHZWE 109V33–10 Note: 14. During this period the I/Os are in the output state and input signals should not be applied. 6 CY7C1009V33 CY7C109V33 Truth Table CE1 CE2 OE WE I/O 0–I/O7 Mode Power H X X X High Z Power-Down Standby (ISB) X L X X High Z Power-Down Standby (ISB) L H L H Data Out Read Active (ICC) L H X L Data In Write Active (ICC) L H H H High Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) 12 15 20 25 Ordering Code Package Name Package Type CY7C109V33-12VC V33 32-Lead (400-Mil) Molded SOJ CY7C1009V33-12VC V32 32-Lead (300-Mil) Molded SOJ CY7C1009V33L-12VC V32 32-Lead (300-Mil) Molded SOJ CY7C109V33-12ZC Z32 32-Lead TSOP Type I CY7C109V33–15VC V33 32-Lead (400-Mil) Molded SOJ CY7C1009V33-15VC V32 32-Lead (300-Mil) Molded SOJ CY7C1009V33L-15VC V32 32-Lead (300-Mil) Molded SOJ CY7C109V33-15ZC Z32 32-Lead TSOP Type I CY7C109V33–20VC V33 32-Lead (400-Mil) Molded SOJ CY7C109V33–20ZC Z32 32-Lead TSOP Type I CY7C109V33L–20VC V33 32-Lead (400-Mil) Molded SOJ CY7C109V33L–20ZC Z32 32-Lead TSOP Type I CY7C1009V33-20VC V32 32-Lead (300-Mil) Molded SOJ CY7C1009V33L-20VC V32 32-Lead (300-Mil) Molded SOJ CY7C109V33–25VC V33 32-Lead (400-Mil) Molded SOJ CY7C109V33L–25VC V33 32-Lead (400-Mil) Molded SOJ CY7C109V33L–25ZC Z32 32-Lead TSOP Type I CY7C1009V33L-25VC V32 32-Lead (300-Mil) Molded SOJ CY7C1009V33-25VC V32 32-Lead (300-Mil) Molded SOJ Shaded areas contain preliminary information. Document #: 38–00635–A 7 Operating Range Commercial Commercial Commercial Commercial CY7C1009V33 CY7C109V33 Package Diagrams 32-Lead (300-Mil) Molded SOJ V32 51-85041-A 32-Lead (400-Mil) Molded SOJ V33 51-85033-A 8 CY7C1009V33 CY7C109V33 Package Diagrams (continued) 32-Lead Thin Small Outline Package Z32 51-85056-B © Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.