NCP5080 Xenon Photoflash Capacitor Charge with Photo Sense Interface The NCP5080 product is a high voltage boost driver dedicated to the Xenon power flashes. The built-in DC/DC converter is based on a flyback structure with an external transformer to adapt any range of high voltage demand. The external feedback network makes it possible to dynamically adjust of the output voltage. http://onsemi.com MARKING DIAGRAM XXXXX XXXXX ALYWG G 1 Features LLGA12 CASE 513AD A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location) •2.7 V to 5.5 V Input Voltage Range •Xenon Function Fully Supported •Built-in Short Circuit Protection •Dedicated Photo Flash Trigger Pin •Provides IGBT drive •Embedded Photodiode Sense •Adjustable Primary Ipeak Current •This is a Pb-Free Device PHREF TRGFL IGBT VBAT PGND VSW Typical Applications •Digital Camera Photo Flash •Digital Cellular Phone Camera Photo Flash •Low Power Beacon 1 2 3 4 5 12 11 10 9 8 7 6 PHSEN VHB IPKRF AGND READY EN ORDERING INFORMATION Device Package Shipping† NCP5080MUTXG LLGA12 (Pb-Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. +VBAT C3 GND 10mF/6.3V D6 R6 22mF/315V C2 GND D1 1 R3 4 VHT U1 1k READY GND 7 2 ENABLE S1 1 TRGFL TRIGGER 12 VBAT 2 T1 4 R5 11k 9 X1 BAS21-B EN 1 3 TRGFL PHREF Vsw 6 PHSEN PGND 5 IPK-REF IGBT 3 VFB 11 GND COILCRAFT-CJ5143-AL GND AGNG 33R Np 47nF/400V GND 1 3 4 NCP5080 8 R2 12k GND G Collector Emitter Q1 IGBT-CY25BAH-8F 3.0M C1 7 6 10nF Figure 1. Typical NCP5080 Photo Flash Application July, 2007 - Rev. 1 Ns R12 VHT © Semiconductor Components Industries, LLC, 2007 3 R7 10k R1 GND 220k T2 FLTRG-TB-KR8 3 C4 1 2 GND 10 4 2 +VBAT EN READY 1 S2 READY 8 XENON TUBE +VBAT 1 5 GND Publication Order Number: NCP5080/D NCP5080 VBAT +VBAT UVLO 4 6 Thermal Shutdown Boost Driver Vsw Q1 +Vbat 5 READY PGND 8 GND Vbat EN TRGFL PHREF PHSEN IPKREF AGND 7 2 100k 1 100k 12 GND 3 GND GND GND 11 10 Controller 9 IGBT Buffer GND Figure 2. NCP5080 Simplified Block Diagram http://onsemi.com 2 VFB NCP5080 PIN DESCRIPTIONS PIN Name Type 1 PHREF INPUT, ANALOG The external controller biases this pin with the reference voltage used, together with the PHSEN pin, to control the illumination of the photo scene. The VPH voltage shall be in the 0.5 V to 1.5 V range, capable to support the internal resistor network (R load minimum is 500 kW). The photo sense function is deactivated when 0.5 V v PHREF v 1.5 V and PHSEN = GND (see Table 4). Description 2 TRGFL INPUT, DIGITAL A positive going pulse applied to this pin triggers the external IGBT and the flash sequence takes place. This command is active when EN = High, but is not synchronized with the output voltage value (see Table 4). 3 IGBT OUTPUT, POWER This pin provides the signal to drive the external IGBT and can be forced High or Low independ‐ ently of the output voltage value, (assuming EN = High) according to the TRGFL pin status (see Table 4). Depending upon the type of IGBT used in the application, specific external gate network might be necessary to satisfy the IGBT gate drive conditions. 4 VBAT INPUT, POWER This pin carries the power supply to the analog, digital and DC/DC converter blocks and must be decoupled to ground by a 10 mF ceramic capacitor connected as close as possible to the package. 5 PGND POWER This pin is the GROUND return for the DC/DC converter and must be connected to the system ground, a ground plane is strongly recommended. 6 VSW OUTPUT, POWER This pin is the drain of the internal NMOS device and shall be connected to the primary of the external transformer. Care must be observed, at PCB layout level, to minimize the noise due to the large current and voltage transients present on that pin during normal operation. 7 EN INPUT, DIGITAL This pin controls the operation of the boost converter: EN = Low ³ The DC/DC converter is OFF, no flash can take place, the voltage across the external reservoir capacitor depends solely upon the leakage current present in the environment. EN = High ³ The DC/DC converter is activated, the voltage across the external reservoir capacitor is regulated at the predetermined value according to the VFB reference. Similarly, a flash can take place, assuming the Xenon tube is properly biased. 8 READY OUTPUT, DIGITAL This Open Drain Output goes LOW when the output voltage has reached the predetermined value across the external reservoir capacitor. The signal is HIGH when Vout is below the expected value, or if a fault has been detected at chip level. 9 AGND POWER This pin returns the Analog and Digital blocks ground and must be connected to the external ground plane. 10 IPKREF INPUT, ANALOG This pin provides the setup of the peak current flowing into the primary of the external transformer. The main purpose of this reference is to adjust the size of the transformer as a function of the flash power. 11 VFB INPUT, ANALOG This pin is the voltage feedback used to regulate the high voltage across the external reservoir capacitor. The impedance across VFB and GND shall be kept to the lowest possible value to minimize the noise pickup. 12 PHSEN INPUT, ANALOG This pin provides a feedback from the illumination during the photo flash and, associated to the PHREF signal, controls the duration of the photo flash. The photodiode, connected across PHSEN and VBAT, shall be adjusted according to the Xenon flash in use. On the other hand, an external pulldown resistor shall be connected between the PHSEN pin and the ground reference. Such a resistor shall be calculated to cope with the type of photodiode used in the illumination sense loop. The photo sense function is deactivated when PHSEN = GND and 0.5 V v PHREF v 1.5 V (see Table 4). 1. Using low ESR ceramic capacitor, X5R type, is mandatory to optimize the DC/DC operation and to reduce the EMI. http://onsemi.com 3 NCP5080 MAXIMUM RATINGS (Note 2) Rating Symbol VBAT, VCC Power Supply Value Unit -0.3 < VBAT < 7.0 V VSW Output Power Supply 40.0 V EN, PFLASH Digital Input Voltage Digital Input Current -0.3 < V < VBAT 1 V mA Human Body Model: R=1500 W, C=100 pF (Note 3) Machine Model 2 200 kV V LLGA12 package Power Dissipation @ TA = +85°C (Note 4) Thermal Resistance Junction-to-Air Thermal Resistance Junction-to-Case 400 100 12 mW °C/W °C/W ESD PD RTHja RTHJC TA Operating Ambient Temperature Range -40 to +85 °C TJ Operating Junction Temperature Range -40 to +125 °C +150 °C TJmax Tstg Maximum Junction Temperature Storage Temperature Range Latchup Current Maximum Rating per JEDEC Standard: JESD78 -65 to + 150 °C $100 mA Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 2. Maximum electrical ratings define the values beyond which permanent damage(s) may occur internally to the chip whatever be the operating temperature 3. This device series contains ESD protection and exceeds the following tests: Human Body Model (HBM) $2.0 kV per JEDEC standard: JESD22-A114 Machine Model (MM) $200 V per JEDEC standard: JESD22-A115 4. The maximum package power dissipation limit must not be exceeded. 5. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J-STD-020A. POWER SUPPLY SECTION (Typical values are referenced to TA =+25°C, minimum and maximum values are referenced -40°C to +85°C ambient temperature, unless otherwise noted, and operating conditions are 2.85 V < VBAT < 5.5 V, unless otherwise noted) Pin Symbol 4 VBAT DC/DC Converter Power Supply 4 UVLO Input Voltage Undervoltage Monitoring 6 Ipk 6 Idss tstart 4 4 3 6 Istdb Iop Rating Min Typ Max Unit 2.7 5.5 V 2.1 2.6 V Primary Transformer Peak Current (750 mA Final Test Correlation) Ripk = 11 kW 1.5 A Internal Power Switch NMOS Leakage Current @ Vdss = 40 V 0.5 mA DC/DC Start Time (Cout = 100 mF, No Load) VBAT = 4 V, from EN Positive Pulse to Vout = 300 V (Note 6) s 2 3 mA Standby Current, VBAT = 5.5 V, Iout = 0 mA, EN = Low VBAT = 3.6 V, Iout = 0 mA, EN = Low 1 0.75 Operating Current, @Vout = Nominal, VBAT = 3.6 V, EN = High 0.5 External IGBT Drive @ VBAT = 3.6V Vgs = High (Note 8) Vgs = Low 23 33 Tonmx Maximum Inductor Charge Current ON Time 60 ms Toffmx Maximum Inductor Discharge Current OFF Time 60 ms TLEB Leading Blanking (Note 7) 260 ns Internal Power Switch NMOS RDS(on) @ VBAT = 4.2 V 250 Rdrv RDS(on) mA W 37 52 600 mW 6. Since this parameter is highly depending upon the application, it is not tested, guaranteed by design. 7. The blanking parameter is internal and cannot be tested in production, guaranteed by design. 8. Since the IGBT gate drive is derived from the VBAT supply, special care must be taken to ensure that the IGBT triggers when Vgs is high and VBAT is below 3.0 V. http://onsemi.com 4 NCP5080 ANALOG SECTION (Typical values are referenced to TA = +25°C, minimum and maximum values are referenced -40°C to +85°C ambient temperature, unless otherwise noted, operating conditions 2.85 V < VBAT < 5.5 V, unless otherwise noted) Pin Symbol 10 IREF Reference current @ VREF = 1.14 V (Notes 9 and 10) 10 VREF Reference Voltage (Note 10) 10 IPKR Reference Current (IREF) Current Ratio 6 FPWM 11 VFB Output Voltage Feed Back reference 1.10 1 VPH Photo Sense Voltage Reference 0.5 1 VPHR Photo Reference Internal Resistance (Pin 1 to GND) 625 kW Photo Feedback Tolerance $3 % PFB Rating Min Typ 10 Max Unit 100 mA V -3% 1.14 +3% 12000 13700 15400 Internal DC/DC Flyback Frequency @ VBAT = 4.2 V, Ip = 1 A, Lp = 6 mH, Lf = 200 nH, Transformer = TDK (Note 11) 15 1.15 600 kHz 1.20 V 1.5 V 9. IREF current specifies the reference current range one can absorb from the IREF pin 10. The external circuit must not force the IREF pin voltage either higher or lower than the 1.14 V specified. 11. This parameter depends solely upon the output transformer and load characteristic and cannot be tested. 12. The overall photo sense tolerance depends upon the accuracy of the external resistor. Using 1% or better resistor is recommended. DIGITAL PARAMETERS SECTION (Typical values are referenced to TA = +25°C, minimum and maximum values are referenced -40 °C to +85°C ambient temperature, unless otherwise noted, operating conditions 2.85 V < VBAT < 5.5 V, unless otherwise noted) Pin Symbol 2, 7 VIH EN, TRGFL Input Digital Signal 2, 7 VIL EN, TRGFL Input Digital Signal 8 VOL Ready Output Digital @ Irdy = 1 mA 2 Tpwfl TRGFL Input Flash Signal Pulse Width 10 2, 7 Rp EN, TRGFL Input Pulldown Resistor 50 NOTE: Rating Min Typ Max Unit 1.2 VBAT V 0 0.4 V 0.3 V ms 100 200 kW Digital inputs undershoot v 0.30 V to ground, Digital inputs overshoot < 0.30 V to VBAT. DC/DC Startup Start Next Cycle EN DC/DC Operation Vout Reference Vout READY TRGFL Vout = Programmed Value Send Flash Command Figure 3. Basic Operation Timings DC/DC Operation limit the peak voltage, at the NCP5080 pin VSW level, to the operating voltage sustained by the internal NMOS device. With a 1:10 ratio, the peak voltage is limited to 30 V to The converter is based on a flyback topology, associated to an external transformer dedicated to the high voltage application. The Primary/Secondary turns ratio is defined to http://onsemi.com 5 NCP5080 Inductor Peak Current supply a regulated 300 V across the external reservoir capacitor. Note that although an OVP circuit is built-in the NCP5080 chip, it is strongly recommended to avoid operation without an external reservoir capacitor, a 1 mF / 315 V being the minimum value. When the NMOS is ON, the current increases into the primary of the transformer until either the Ipeak limit has been reached, or the time out is finished: at this point, the NMOS is switched OFF and the energy stored into the primary is dumped to the secondary, providing the current to recharge the reservoir capacitor. The OFF period is monitored by sensing the primary voltage and the system will re-start a new cycle when either Vp = 0 V or the time out is finished. The external resistor divider, connected across Vout and Ground, senses the output voltage to close the feedback loop at FBD pin. The output voltage is based on the 1.2 V reference and the R1/R2 ratio: Vout = VREF * ((R1 + R2) / R2). The output voltage is regulated when the EN = H, but drops to zero when EN = L. In this case, the discharge time of the external reservoir depends solely upon the value of the passive component and the leakage currents that might exist at system level. The DC/DC converter is switched OFF when either EN = Low, or TRGFL = High, or when the output voltage has reached the programmed value (see Figure 3). In order to provide more flexibility to the NCP5080 driver, an extra pin, IPKREF, is provided to set up the peak current flowing into the primary inductor of the transformer. The IREF is given by the 1.14 V voltage reference and the value of the external resistor: I REF + 1.14Vń RIPK (eq. 1) The primary peak current is given by Equation 1: I peak + I REF * 14000 (eq. 2) The maximum Ipeak current shall be limited to 1.5 A maximum, assuming the transformer is sized to sustain such amount of electromagnetic energy. The efficiency of the DC/DC converter, and the recharge cycle time as well, depends upon the ESR and leakage inductance of the power transformer: a poor transformer will generate large oscillations during the operation which will be difficult to filter out at PCB level. Table 1. PREFERRED POWER TRANSFORMER MANUFACTURERS Manufacturer Model Comments TDK LDT565620ST-20 3 Ipeak = 750 mA Max Coilcraft CJ5143-AL Ipeak = 1200 mA Max Table 2. PREFERRED HIGH VOLTAGE TRIGGER FUNCTION Component Manufacturer Model High Voltage Trigger PCA EPC3215G-X High Voltage Ceramic Capacitor TDK C3225X7R2J473M RUBYCON FW series 22 mF/330 V to 120 mF/330 V Comments Vout = 4000 V Reference design+ Preferred Table 3. PREFERRED XENON LAMP Component Manufacturer Model Comments Flash Lamp-Reflector Assembly Perkin-Elmer RF-ASYRF160709 PKI08 (H) Ej = 1.5 Joule Cout = 33 mF Flash Lamp-Reflector Assembly Perkin-Elmer RF-ASY RF160709 PKI07 (H) Ej = 2.1 Joule Cout = 47 mF Flash Lamp-Reflector Assembly Nam Kwong Co. LTD. FET-O-D03150220E-02 9.8 Joule, Cout = 180 mF Flash Lamp-Reflector Assembly Nam Kwong Co. LTD. FET-O-D02230202A-07 8.0 Joule, Cout = 150 mF Perkin Elmer coordinates: [email protected] Flash Strobe The flash is activated by the digital status present at the TRGFL Pin and the logic condition of the EN and PHSEN Pins as defined in Table 4. http://onsemi.com 6 NCP5080 Table 4. FLASH OPERATING TRUE TABLE EN TRGFL PHREF PHSEN Status 0 X X X System Disabled: The boost and the flash are de-activated. Any on going flash is immediately switched OFF. 1 0 0.5 V to 1.5 V GND System Active: The output reservoir is being charged and the output voltage regulated. The photo sense is deactivated. The IGBT gate drive is LOW. 1 1 0.5 V to 1.5 V GND System Active: The output reservoir is being charged and the output voltage regulated. The photo sense is deactivated. The IGBT gate drive is HIGH whatever be the Vout voltage value . The xenon tube is fired if Vout = Vxen minim‐ um and the flash light keeps going until either TRGFL = 0, or the reservoir capacitor is fully discharged. 1 0 VREF PHOTODIODE VREF PHOTODIODE 1 1 System Active: The output reservoir is being charged and the output voltage regulated. The photo sense is activated . The IGBT gate drive is LOW. System Active: The output reservoir is being charged and the output voltage regulated. The photo sense is deactivated and the flash is switched OFF if the voltage present at the PHSEN Pin is higher the reference voltage applied to the PHREF Pin. The IGBT gate drive is HIGH whatever be the Vout voltage value . The Xenon tube is fired if Vout = Vxen minimum and the IGBT keeps going until either TRGFL = 0, or the PHSEN > PHREF, or the reservoir capacitor is fully discharged. The TRGFL signal provides a simple way to generate multiple consecutive flashes (similar to the stroboscope effect) to minimize the red eye effect, or to freeze multiple pictures of moving objects. The IGBT must be capable to turn ON with limited Gate voltage. The function can be deactivated when not used in the application shown in Table 5. More over, connecting the PHREF Pin to the IPKREF Pin provides an easy way to fully disconnect the photo sense function. The external photo sense element shall be connected across PHSEN and VBAT to source the current as the illumination increases, with a pull-down resistor connected to the ground reference as depicted in Figure 4. The sense resistor is calculated to get the collector current when the photo diode is saturated. With a typical 10 mA to 30 mA of photodiode current, the resistor will be 100 kW to cope with the low input battery supply voltage situation. Photodiode Sensor The photodiode sensor provides a feedback from the illumination generated by the xenon flash to avoid the overexposed picture. The PHREF pin shall be biased according to the model of xenon tube (in particular, the energy level) and optical lens aperture. Table 5. NCP5080 PHOTO SENSE TRUE TABLE Pin Operation 0.5 V v PHREF w 1.5 V PHSEN = GND Operation Photodiode Sense Deactivated PHREF = VPH PHSEN = Photodiode The IGBT is solely controlled by the TRGFL Pin Photodiode Sense Activated The IGBT is controlled by the [TRGFL AND PHSEN ] status. VBAT 4 VBAT D2 PHOTO VBAT 12 PHSEN U1 + R1 R1 100k GND 100k 1 R2 PHREF 100k GND Figure 4. Basic Photo Sense Input Circuit http://onsemi.com 7 U2 + Comparator PHSTP NCP5080 Although it is possible to increase the photo feedback sensitivity by increasing the value of the pulldown resistor, care must be observed since such a resistor is in parallel with the internal network as depicted in Figure 4 and the input node might be too sensitive to the ambient noise. It is recommended to avoid sense resistor value above 100 kW, although that 1 MW is possible, the operation being rapidly downgraded when the resistance increases beyond this value. The PHREF voltage is setup by the external controller, in the 0.5 V to 1.5 V range, depending upon the need of the application. The internal structure includes a 500 kW (typical) resistor network, connected between PHREF pin and GND : the external reference source must support such a load and a 10 kW output impedance, or lower, is recommended to avoid uncontrolled operation. Finally, the IGBT signal will be switched OFF when the PHSEN signal reaches the PHREF reference. The function is deactivated by forcing a voltage in the 0.5 V to 1.5 V range at the PHREF pin, associated with a GND connection to the PHSEN pin. When the photo sense is active and the photo sense threshold has been crossed, the photo sense feedback is internally latched and recycling the TRGFL signal (H to L) is necessary to reset the latch and start a new sequence . Simplified Flash The circuitry can be simplified when the application does not need the multiple flashes during the same photo sequence. In this case, the IGBT can be removed as there is no more need to dynamically switch off the xenon tube . Similarly, the photo sense becomes useless since there will be no way to control the illumination once the xenon flash has been triggered. Such a feature must be properly deactivated to avoid uncontrolled operation during a photo sequence: a simple resistor network fulfill such a requirement as depicted in Figure 6. EN Vout Ref. Vout READY IGBT TRGFL VPH Photo transistor current Illumination = Vreference --> IGBT switched OFF PHSEN Figure 5. Typical Photo Sense Timings http://onsemi.com 8 NCP5080 +VBAT VCC 22mF/315V D1 10mF/6.3V 10k R6 C3 GND C2 GND R3 1 VHT U1 GND 12 10 R5 11k 9 EN 3 1 GND TRGFL PHREF VSW 6 PHSEN PGND 5 IPK-REF IGBT 3 VFB 11 AGNG LDT565630T 220k T2 3 3 1 C4 100nF/400V TRIG_FLASH GND R7 2 22R R2 VHT 11k GND GND GND NCP5080 R1 GND X1 MURHS160T3G 2 1 T1 4 2 R9 2 4 1 7 EN VBAT READY XENON TUBE MCU 8 100R READY GND 3.3M CI 10nF Figure 6. Simplified Xenon Flash Controller On the other hand, since it is not possible to connect the high voltage trigger pin to the controller (MCU or other digital device), the IGBT pin will be used to trig the SCR device necessary to fire the high voltage pulse as depicted in Figure 6. http://onsemi.com 9 NCP5080 DEMO BOARD +VBAT GND S2 EN TRGFL Ready READY 1 GND 4 R7 GND 3 GND VHT 1 C3 D1 4 8 22mF/315V GND BAS21 R12 10k R13 100nF P1 1R G X1 7 6 3 VHT THT GND 5 R3 220k 1 Ns 2 3 Collector Q1 IGBT-CY25BAH-8F Emitter 1 3 4 2 R5 GND 22R 3.0M R2 COILCRAFT-CJ5143-AL 2 T1 +VBAT 5 C2 4 10mF/6.3V VBAT PGND 3 6 PHSEN IGBT Vsw IPK-REF PHREF TRGFL EN READY U1 GND 8 7 2 1 12 10 9 11 VFB C5 R1 10nF AGNG NCP5080 GND 12k PERKIN -ELMER GND ENABLE S1 TRIGGER R11 10k 10k GND GND Q2 1 +VBAT C1 J3 3 1 1k SHB410 Np T2 EC3215G-X C4 GND 10 R10 Enable 2 http://onsemi.com R6 D6 11k R4 10k GND Figure 7. Demo Board Schematic Diagram D5 +VBAT 1k PHOTOEN NCP5080 Figure 8. Output Capacitor Recharge Cycle Figure 9. Xenon Tube Discharge Current Figure 10. Recycling VOUT Slope and Battery Input Current with Ipeak = 1.5 A Figure 11. Recycling VOUT Slope and Battery Input Current with Ipeak = 750 mA TRGFL: Trigger Flash pulse PHREF: photo sense reference voltage ( provided by the external circuit) PHSEN: photo sense input voltage ( provided by the photo transistor sensor ) http://onsemi.com 11 NCP5080 PACKAGE DIMENSIONS LLGA12 CASE 513AD-01 ISSUE A A D PIN ONE REFERENCE 2X 0.15 C 2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. B ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ E DIM A A1 b D D2 E E2 e K L 0.15 C TOP VIEW 0.10 C MILLIMETERS MIN MAX 0.50 0.60 0.00 0.05 0.20 0.30 3.00 BSC 2.75 2.85 3.00 BSC 1.65 1.75 0.50 BSC 0.20 --0.35 0.45 A 12X 0.08 C SIDE VIEW A1 C SEATING PLANE SOLDERING FOOTPRINT* 3.30 12X D2 1 0.56 1 6 e 0.25 PITCH 0.40 12X K E2 2.78 11X 12X L 12 7 12X b 0.10 C A B 0.05 C 0.28 NOTE 3 1.73 DIMENSIONS: MILLIMETERS BOTTOM VIEW *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 http://onsemi.com 12 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NCP5080/D