CYPRESS CY28442-2

PRELIMINARY
CY28442-2
Clock Generator for Intel Alviso Chipset
Features
• 96/100 MHz Spreadable differential clock.
• 33-MHz PCI clock
• Compliant to Intel CK410M
• Low-voltage frequency select input
• Supports Intel Pentium-M CPU
• I2C support with readback capabilities
• Selectable CPU frequencies
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• Differential CPU clock pairs
• 100-MHz differential SRC clocks
• 3.3V power supply
• 96-MHz differential dot clock
• 56-pin TSSOP package
• 48-MHz USB clocks
• SRC clocks independently stoppable through
CLKREQ#[A:B]
CPU
SRC
PCI
REF
DOT96
USB_48
x2 / x3
x5/6
x6
x2
x2
x1
Block Diagram
XIN
XOUT
Pin Configuration
14.318MHz
Crystal
PCI_STP#
PLL1
CPU
CPU_STP#
CLKREQ[A:B]#
PLL Reference
VDD_REF
REF
Divider
VDD_CPU
CPUT_ITP/SRCT7
CPUC_ITP/SRCC7
FS_[C:A]
VDD_SRC
SRCT[1:5]
CPUC[1:5]
VDD_PCI
PCI
VDD_PCI
PCIF
PLL2
96MSS
PLL4
FIXED
VDD_48MHz
96_100_SSCT
96_100_SSCC
Divider
VDD_48MHz
DOT96T
DOT96C
Divider
VDD_48
USB
VTTPWR_GD#/PD
SDATA
SCLK
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PCI2/SEL_CLKREQ**
PCI_STP#
CPU_STP#
FS_C(TEST_SEL)/REF0
REF1
VSSA2
XIN
XOUT
VDDA2
SDATA
SCLK
VSS_CPU
CPUT0
CPUC0
VDD_CPU
CPUT1
CPUC1
IREF
VSSA
VDDA
CPU2T_ITP/SRCT7
CPU2C_ITP/SRCC7
VDD_SRC_ITP
CLKREQA#/SRCT6
CLKREQB#/SRCC6
SRCT5
SRCC5
VSS_SRC
56 pin TSSOP/SSOP
I2C
Logic
Cypress Semiconductor Corporation
Document #: 38-07691 Rev. **
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
CY28442-2
VDD_REF
VSS_REF
PCI3
PCI4
PCI5
VSS_PCI
VDD_PCI
ITP_EN/PCIF0
**96_100_SEL/PCIF1
VTTPWRGD#/PD
VDD_48
FS_A/48M_0
VSS_48
DOT96T
DOT96C
FS_B/TESTMODE
96_100_SSCT
96_100_SSCC
SRCT1
SRCC1
VDD_SRC
SRCT2
SRCC2
SRCT3
SRCC3
SRCT4_SATA
SRCC4_SATA
VDD_SRC
IREF
VDD_CPU
CPUT
CPUC
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised June 24, 2004
PRELIMINARY
CY28442-2
Pin Definitions
Pin No.
Name
1
VDD_REF
2
VSS_REF
33,32
CLKREQA#/SRCT6,
CLKREQB#,SRCC6
7
VDD_PCI
6
3,4,5
Type
Description
PWR
3.3V power supply for output
GND
Ground for outputs.
I/O, PU 3.3V LVTTL input for enabling assigned SRC clock (active low) or 100MHz
Serial Reference Clock.
Selectable through
CLKREQA# defaults to enable/disable SRCT/C4, CLKREQB# defaults to
enable/disable SRCT/C5. Assignment can be changed via SMBUS register Byte
8.
PWR
3.3V power supply for outputs.
VSS_PCI
GND
Ground for outputs.
PCI
O, SE 33-MHz clock
8
ITP_EN/PCIF0
I/O, SE 3.3V LVTTL input to enable SRC7 or CPU2_ITP/33MHz clock output.
(sampled on the VTT_PWRGD# assertion).
1 = CPU2_ITP, 0 = SRC7
9
PCIF1/96_100_SEL
I/O, 33-MHz clock/3.3V-tolerant input for 96_100M frequency selection
PD,SE (sampled on the VTT_PWRGD# assertion).
1 = 100MHz, 0 = 96MHz
10
VTT_PWRGD#/PD
I, PU
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A,
FS_B, FS_C and ITP_EN, 96MSS_SRC_SEL inputs, SEL_CLKREQ. After
VTT_PWRGD# (active low) assertion, this pin becomes a real-time input for
asserting power down (active high).
PWR
3.3V power supply for outputs.
11
VDD_48
12
FS_A/48_M0
13
VSS_48
14,15
DOT96T, DOT96C
16
FS_B/TEST_MODE
17,18
96_100_SSC
I/O
GND
3.3V-tolerant input for CPU frequency selection/fixed 48-MHz clock output.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
Ground for outputs.
O, DIF Fixed 96-MHz clock output.
I
3.3V-tolerant input for CPU frequency selection. Selects Ref/N or Tri-state
when in test mode
0 = Tri-state, 1 = Ref/N
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
O,DIF Differential 96/100MHz SS clock for flat-panel display
19,20,22,23, SRCT/C
24,25,30,31
O, DIF 100MHz Differential serial reference clocks.
21,28
VDD_SRC
PWR
3.3V power supply for outputs.
34
VDD_SRC_ITP
PWR
3.3V power supply for outputs.
26,27
SRC4_SATAT,
SRC4_SATAC
O, DIF Differential serial reference clock. Recommended output for SATA.
29
VSS_SRC
36,35
CPUT2_ITP/SRCT7,
CPUC2_ITP/SRCC7
GND
37
VDDA
PWR
3.3V power supply for PLL.
38
VSSA
GND
Ground for PLL.
39
IREF
I
42
VDD_CPU
PWR
44,43,41,40
CPUT/C
O, DIF Differential CPU clock outputs.
45
VSS_CPU
46
SCLK
I
47
SDATA
I/O
Document #: 38-07691 Rev. **
Ground for outputs.
O, DIF Selectable differential CPU or SRC clock output.
ITP_EN = 0 @ VTT_PWRGD# assertion = SRC7
ITP_EN = 1 @ VTT_PWRGD# assertion = CPU2
GND
A precision resistor is attached to this pin, which is connected to the internal
current reference.
3.3V power supply for outputs.
Ground for outputs.
SMBus-compatible SCLOCK.
SMBus-compatible SDATA.
Page 2 of 22
PRELIMINARY
CY28442-2
Pin Definitions (continued)
Pin No.
Name
Type
Description
48
VDDA2
PWR
49
XOUT
O, SE 14.318-MHz crystal output.
50
XIN
I
GND
3.3V power supply for PLL2
14.318-MHz crystal input.
51
VSSA2
52
REF1
O
Ground for PLL2.
Fixed 14.318 MHz clock output.
53
FS_C_TEST_SEL/
REF0
I/O
3.3V-tolerant input for CPU frequency selection/fixed 14.318 clock output.
Selects test mode if pulled to greater than 1.8V when VTT_PWRGD# is asserted
low.
Refer to DC Electrical Specifications table for VIL_FS,VIH_FS specifications.
54
CPU_STP#
I, PU
3.3V LVTTL input for CPU_STP# active low.
55
PCI_STP#
I, PU
3.3V LVTTL input for PCI_STP# active low.
56
PCI2/SEL_CLKREQ
I/O, PD 3.3V-tolerant input for CLKREQ pin selection/fixed 33-MHz clock output.
(sampled on the VTT_PWRGD# assertion).
1= pins 32,33 function as clk request pins, 0= pins 32,33 function as SRC outputs.
Frequency Select Pins (FS_A, FS_B and FS_C)
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A, FS_B, FS_C inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).
Upon VTT_PWRGD# being sampled low by the clock chip
(indicating processor VTT voltage is stable), the clock chip
samples the FS_A, FS_B and FS_C input values. For all logic
levels of FS_A, FS_B and FS_C, VTT_PWRGD# employs a
one-shot functionality in that once a valid low on
VTT_PWRGD# has been sampled, all further VTT_PWRGD#,
FS_A, FS_B and FS_C transitions will be ignored, except in
test mode.
Table 1. Frequency Select Table FS_A, FS_B and FS_C
FS_C
FS_B
FS_A
CPU
SRC
PCIF/PCI
REF0
DOT96
USB
1
0
1
100 MHz
100 MHz
33 MHz
14.318 MHz
96 MHz
48 MHz
0
0
1
133 MHz
100 MHz
33 MHz
14.318 MHz
96 MHz
48 MHz
0
1
1
166 MHz
100 MHz
33 MHz
14.318 MHz
96 MHz
48 MHz
0
1
0
200 MHz
100 MHz
33 MHz
14.318 MHz
96 MHz
48 MHz
Serial Data Interface
Data Protocol
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 2.
The block write and block read protocol is outlined in Table 3
while Table 4 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Table 2. Command Code Definition
Bit
7
(6:0)
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
Document #: 38-07691 Rev. **
Page 3 of 22
PRELIMINARY
CY28442-2
Table 3. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
Description
Start
Write
10
18:11
19
27:20
28
36:29
37
45:38
Bit
1
Slave address – 7 bits
9
Block Read Protocol
8:2
Description
Start
Slave address – 7 bits
9
Write
Acknowledge from slave
10
Acknowledge from slave
Command Code – 8 bits
18:11
Command Code – 8 bits
Acknowledge from slave
19
Acknowledge from slave
Byte Count – 8 bits
(Skip this step if I2C_EN bit set)
20
Repeat start
Acknowledge from slave
27:21
Slave address – 7 bits
Data byte 1 – 8 bits
28
Read = 1
Acknowledge from slave
29
Acknowledge from slave
Data byte 2 – 8 bits
46
Acknowledge from slave
....
Data Byte /Slave Acknowledges
....
Data Byte N –8 bits
....
Acknowledge from slave
....
Stop
37:30
38
46:39
47
55:48
Byte Count from slave – 8 bits
Acknowledge
Data byte 1 from slave – 8 bits
Acknowledge
Data byte 2 from slave – 8 bits
56
Acknowledge
....
Data bytes from slave / Acknowledge
....
Data Byte N from slave – 8 bits
....
NOT Acknowledge
....
Stop
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
8:2
Description
Start
Slave address – 7 bits
Byte Read Protocol
Bit
1
8:2
Slave address – 7 bits
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
18:11
Command Code – 8 bits
18:11
Command Code – 8 bits
Acknowledge from slave
19
Acknowledge from slave
Data byte – 8 bits
20
Repeated start
19
27:20
28
Acknowledge from slave
29
Stop
Document #: 38-07691 Rev. **
9
Description
Start
27:21
Write
Slave address – 7 bits
28
Read
29
Acknowledge from slave
37:30
Data from slave – 8 bits
38
NOT Acknowledge
39
Stop
Page 4 of 22
PRELIMINARY
CY28442-2
Control Registers
Byte 0: Control Register 0
Bit
@Pup
Name
Description
7
1
CPUT2_ITP/SRCT7
CPUC2_ITP/SRCC7
6
1
SRC[T/C]6
SRC[T/C]6 Output Enable
0 = Disable (Tri-state), 1 = Enable
5
1
SRC[T/C]5
SRC[T/C]5 Output Enable
0 = Disable (Tri-state), 1 = Enable
4
1
SRC[T/C]4
SRC[T/C]4 Output Enable
0 = Disable (Tri-state), 1 = Enable
3
1
SRC[T/C]3
SRC[T/C]3 Output Enable
0 = Disable (Tri-state), 1 = Enable
2
1
SRC[T/C]2
SRC[T/C]2 Output Enable
0 = Disable (Tri-state), 1 = Enable
1
1
SRC[T/C]1
SRC[T/C]1 Output Enable
0 = Disable (Tri-state), 1 = Enable
0
1
RESERVED
CPU[T/C]2_ITP/SRC[T/C]7 Output Enable
0 = Disable (Tri-state), 1 = Enable
RESERVED
Byte 1: Control Register 1
Bit
7
@Pup
1
Name
PCIF0
6
1
DOT_96T/C
5
1
USB_48
4
1
REF0
3
1
REF1
2
1
CPU[T/C]1
1
1
CPU[T/C]0
0
0
CPU
Description
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
DOT_96 MHz Output Enable
0 = Disable (Tri-state), 1 = Enabled
USB_48 MHz Output Enable
0 = Disabled, 1 = Enabled
REF0 Output Enable
0 = Disabled, 1 = Enabled
REF1 Output Enable
0 = Disabled, 1 = Enabled
CPU[T/C]1 Output Enable
0 = Disable (Tri-state), 1 = Enabled
CPU[T/C]0 Output Enable
0 = Disable (Tri-state), 1 = Enabled
PLL1 (CPU PLL) Spread Spectrum Enable
0 = Spread off, 1 = Spread on
Byte 2: Control Register 2
Bit
7
@Pup
1
Name
PCI5
6
1
PCI4
5
1
PCI3
4
1
PCI2
3
2
1
0
1
1
1
1
Reserved
Reserved
Reserved
PCIF1
Document #: 38-07691 Rev. **
Description
PCI5 Output Enable
0 = Disabled, 1 = Enabled
PCI4 Output Enable
0 = Disabled, 1 = Enabled
PCI3 Output Enable
0 = Disabled, 1 = Enabled
PCI2 Output Enable
0 = Disabled, 1 = Enabled
Reserved, Set = 1
Reserved, Set = 1
Reserved, Set = 1
PCIF1 Output Enable
0 = Disabled, 1 = Enabled
Page 5 of 22
PRELIMINARY
CY28442-2
Byte 3: Control Register 3
Bit
@Pup
Name
Description
7
0
SRC7
Allow control of SRC[T/C]7 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
6
0
SRC6
Allow control of SRC[T/C]6 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
5
0
SRC5
Allow control of SRC[T/C]5 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
4
0
SRC4
Allow control of SRC[T/C]4 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
3
0
SRC3
Allow control of SRC[T/C]3 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
2
0
SRC2
Allow control of SRC[T/C]2 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
1
0
SRC1
Allow control of SRC[T/C]1 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
0
0
RESERVED
RESERVED
Byte 4: Control Register 4
Bit
@Pup
Name
7
0
96_100_SSC
96_100_SSC Drive Mode
0 = Driven in PWRDWN, 1 = Tri-state
Description
6
0
DOT96T/C
DOT_PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Tri-state
5
0
RESERVED
4
0
PCIF1
Allow control of PCIF1 with assertion of SW and HW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
3
0
PCIF0
Allow control of PCIF0 with assertion of SW and HW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
2
1
CPU[T/C]2
Allow control of CPU[T/C]2 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
1
1
CPU[T/C]1
Allow control of CPU[T/C]1 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
0
1
CPU[T/C]0
Allow control of CPU[T/C]0 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
RESERVED
Byte 5: Control Register 5
Bit
@Pup
Name
7
0
SRC[T/C]
SRC[T/C] Stop Drive Mode
0 = Driven when PCI_STP# asserted,1 = Tri-state when PCI_STP#
asserted
6
0
CPU[T/C]2
CPU[T/C]2 Stop Drive Mode
0 = Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP#
asserted
5
0
CPU[T/C]1
CPU[T/C]1 Stop Drive Mode
0 = Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP#
asserted
4
0
CPU[T/C]0
CPU[T/C]0 Stop Drive Mode
0 = Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP#
asserted
3
0
SRC[T/C][7:1]
SRC[T/C] PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Tri-state when PD asserted
2
0
CPU[T/C]2
CPU[T/C]2 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Tri-state when PD asserted
Document #: 38-07691 Rev. **
Description
Page 6 of 22
PRELIMINARY
CY28442-2
Byte 5: Control Register 5 (continued)
Bit
@Pup
Name
Description
1
0
CPU[T/C]1
CPU[T/C]1 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Tri-state when PD asserted
0
0
CPU[T/C]0
CPU[T/C]0 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Tri-state when PD asserted
Byte 6: Control Register 6
Bit
@Pup
Name
Description
7
0
TEST_SEL
6
0
TEST_MODE
5
0
RESERVED
4
1
REF
3
1
2
HW
FS_C
FS_C Reflects the value of the FS_C pin sampled on power up
0 = FS_C was low during VTT_PWRGD# assertion
1
HW
FS_B
FS_B Reflects the value of the FS_B pin sampled on power up
0 = FS_B was low during VTT_PWRGD# assertion
0
HW
FS_A
FS_A Reflects the value of the FS_A pin sampled on power up
0 = FS_A was low during VTT_PWRGD# assertion
REF/N or Tri-state Select
0 = Tri-state, 1 = REF/N Clock
Test Clock Mode Entry Control
0 = Normal operation, 1 = REF/N or Tri-state mode,
RESERVED
REF Output Drive Strength
0 = Low, 1 = High
PCI, PCIF and SRC clock SW PCI_STP Function
outputs except those set 0=SW PCI_STP assert, 1= SW PCI_STP deassert
to free running
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
Byte 7: Vendor ID
Bit
@Pup
Name
Description
7
0
Revision Code Bit 3
Revision Code Bit 3
6
0
Revision Code Bit 2
Revision Code Bit 2
5
0
Revision Code Bit 1
Revision Code Bit 1
4
0
Revision Code Bit 0
Revision Code Bit 0
3
1
Vendor ID Bit 3
Vendor ID Bit 3
2
0
Vendor ID Bit 2
Vendor ID Bit 2
1
0
Vendor ID Bit 1
Vendor ID Bit 1
0
0
Vendor ID Bit 0
Vendor ID Bit 0
Byte 8: Control Register 8
Bit
@Pup
Name
Description
7
0
CLKREQ#B
SRC[T/C]7CLKREQ#B control
1 = SRC[T/C]7 stoppable by CLKREQ#B pin
0 = SRC[T/C]7 not controlled by CLKREQ#B pin
6
1
CLKREQ#B
SRC[T/C]5 CLKREQ#B control
1 = SRC[T/C]5 stoppable by CLKREQ#B pin
0 = SRC[T/C]5 not controlled by CLKREQ#B pin
5
0
CLKREQ#B
SRC[T/C]3 CLKREQ#B control
1 = SRC[T/C]3 stoppable by CLKREQ#B pin
0 = SRC[T/C]3 not controlled by CLKREQ#B pin
4
0
CLKREQ#B
SRC[T/C]1 CLKREQ#B control
1 = SRC[T/C]1 stoppable by CLKREQ#B pin
0 = SRC[T/C]1 not controlled by CLKREQ#B pin
Document #: 38-07691 Rev. **
Page 7 of 22
PRELIMINARY
CY28442-2
Byte 8: Control Register 8 (continued)
Bit
@Pup
Name
Description
3
0
RESERVED
RESERVED
2
1
CLKREQ#A
SRC[T/C]4 CLKREQ#A control
1 = SRC[T/C]4 stoppable by CLKREQ#A pin
0 = SRC[T/C]4 not controlled by CLKREQ#A pin
1
0
CLKREQ#A
SRC[T/C]2 CLKREQ#A control
1 = SRC[T/C]2 stoppable by CLKREQ#A pin
0 = SRC[T/C]2 not controlled by CLKREQ#A pin
0
0
RESERVED
RESERVED
Byte 9: Control Register 9
Bit
@Pup
Name
7
0
S3
6
0
S2
5
0
S1
4
0
S0
Description
96_100_SSC Spread Spectrum Selection table:
S[3:0] SS%
‘0000’ = -0.8%(Default value)
‘0001’ = -1.0%
‘0010‘ = -1.25%
‘0011‘ = -1.5%
‘0100‘ = -1.75%
‘0101‘ = -2.0%
‘0110‘ = -2.5%
‘0111‘ = -0.5%
‘1000‘ = ± 0.25%
‘1001‘ = ± 0.4%
‘1010‘ = ± 0.5%
‘1011‘ = ± 0.6%
‘1100‘ = ± 0.8%
‘1101‘ = ± 1.0%
‘1110‘ = ± 1.25%
3
1
96_100 SEL
‘1111‘ = ± 1.5%
Software select 96_100_SSC output frequency, 0 = 96MHz, 1 = 100MHz.
2
1
96_100 Enable
96_100_SSC Enable, 0 = Disable, 1 = Enable.
1
1
96_100 SS Enable
0
0
96_100 SW HW
96_100_SSC Spread spectrum enable. 0 = Disable, 1 = Enable.
Select output frequency of 96_100_SSC via software or hardware
0 = Hardware, 1 = Software.
Byte 10: Control Register 10
Bit
@Pup
Name
Description
7
0
RESERVED
RESERVED
6
0
CLKREQ#B
SRC[T/C]4 CLKREQ#B control
1 = SRC[T/C]4 stoppable by CLKREQ#B pin
0 = SRC[T/C]4not controlled by CLKREQ#B pin
5
0
CLKREQ#B
SRC[T/C]2 CLKREQ#B control
1 = SRC[T/C]2 stoppable by CLKREQ#B pin
0 = SRC[T/C]2 not controlled by CLKREQ#B pin
4
0
RESERVED
RESERVED
3
0
CLKREQ#A
SRC[T/C]7CLKREQ#A control
1 = SRC[T/C]7 stoppable by CLKREQ#A pin
0 = SRC[T/C]7 not controlled by CLKREQ#A pin
Document #: 38-07691 Rev. **
Page 8 of 22
PRELIMINARY
CY28442-2
Byte 10: Control Register 10 (continued)
Bit
@Pup
Name
Description
2
0
CLKREQ#A
SRC[T/C]5 CLKREQ#A control
1 = SRC[T/C]5 stoppable by CLKREQ#A pin
0 = SRC[T/C]5 not controlled by CLKREQ#A pin
1
0
CLKREQ#A
SRC[T/C]3 CLKREQ#A control
1 = SRC[T/C]3 stoppable by CLKREQ#A pin
0 = SRC[T/C]3 not controlled by CLKREQ#A pin
0
0
CLKREQ#A
SRC[T/C]1 CLKREQ#A control
1 = SRC[T/C]1 stoppable by CLKREQ#A pin
0 = SRC[T/C]1 not controlled by CLKREQ#A pin
The CY28442-2 requires a Parallel Resonance Crystal.
Substituting a series resonance crystal will cause the
CY28442-2 to operate at the wrong frequency and violate the
ppm specification. For most applications there is a 300-ppm
frequency shift between series and parallel crystals due to
incorrect loading.
Table 5. Crystal Recommendations
Frequency
(Fund)
Cut
Loading Load Cap
Drive
(max.)
Shunt Cap
(max.)
Motional
(max.)
Tolerance
(max.)
Stability
(max.)
Aging
(max.)
14.31818 MHz
AT
Parallel
0.1 mW
5 pF
0.016 pF
35 ppm
30 ppm
5 ppm
20 pF
Crystal Loading
Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appropriate capacitive loading (CL).
The following diagram shows a typical crystal configuration
using the two trim capacitors. An important clarification for the
following discussion is that the trim capacitors are in series
with the crystal not parallel. It’s a common misconception that
load capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
Figure 1. Crystal Capacitive Clarification
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
Document #: 38-07691 Rev. **
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
Page 9 of 22
PRELIMINARY
CY28442-2
.
Clock Chip
Ci2
Ci1
Pin
3 to 6p
X2
X1
Cs1
Cs2
Trace
2.8pF
XTAL
Ce1
Ce2
Trim
33pF
Figure 2. Crystal Loading Example
As mentioned previously, the capacitance on each side of the
crystal is in series with the crystal. This mean the total capacitance on each side of the crystal must be twice the specified
load capacitance (CL). While the capacitance on each side of
the crystal is in series with the crystal, trim capacitors
(Ce1,Ce2) should be calculated to provide equal capacitance
loading on both sides.
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
Load Capacitance (each side)
Ce = 2 * CL – (Cs + Ci)
Total Capacitance (as seen by the crystal)
CLe
=
1
1
( Ce1 + Cs1
+ Ci1 +
1
Ce2 + Cs2 + Ci2
)
CL ....................................................Crystal load capacitance
CLe ......................................... Actual loading seen by crystal
using standard value trim capacitors
Ce ..................................................... External trim capacitors
Cs ..............................................Stray capacitance (terraced)
Ci .......................................................... Internal capacitance
(lead frame, bond wires etc.)
CLK_REQ[0:1]# Description
The CLKREQ#[A:B] signals are active low input used for clean
enabling and disabling selected SRC outputs. The outputs
controlled by CLKREQ#[A:B] are determined by the settings
in register byte 8. The CLKREQ# signal is a de-bounced signal
in that it’s state must remain unchanged during two consecutive rising edges of SRCC to be recognized as a valid
assertion or de-assertion. (The assertion and de-assertion of
this signal is absolutely asynchronous).
CL ................................................... Crystal load capacitance
CLe .........................................Actual loading seen by crystal
using standard value trim capacitors
Ce .....................................................External trim capacitors
Cs.............................................. Stray capacitance (terraced)
Ci ........................................................... Internal capacitance
(lead frame, bond wires etc.)
CLKREQ#X
SRCT(free running)
SRCC(free running)
SRCT(stoppable)
SRCT(stoppable)
Figure 3. CLK_REQ#[A:B] Deassertion/Assertion Waveform
Document #: 38-07691 Rev. **
Page 10 of 22
PRELIMINARY
CY28442-2
CLK_REQ[A:B]# Assertion (CLKREQ# -> LOW)
PD (Power-down) – Assertion
All differential outputs that were stopped are to resume normal
operation in a glitch free manner. The maximum latency from
the assertion to active outputs is between 2-6 SRC clock
periods (2 clocks are shown) with all SRC outputs resuming
simultaneously. All stopped SRC outputs must be driven high
within 10 ns of CLKREQ#[1:0] de-assertion to a voltage
greater than 200mV.
When PD is sampled high by two consecutive rising edges of
CPUC, all single-ended outputs will be held low on their next
high to low transition and differential clocks must held high or
Tri-stated (depending on the state of the control register drive
mode bit) on the next diff clock# high to low transition within 4
clock periods. When the SMBus PD drive mode bit corresponding to the differential (CPU, SRC, and DOT) clock output
of interest is programmed to ‘0’, the clock output are held with
“Diff clock” pin driven high at 2 x Iref, and “Diff clock#” tristate.
If the control register PD drive mode bit corresponding to the
output of interest is programmed to “1”, then both the “Diff
clock” and the “Diff clock#” are tristate. Note the example
below shows CPUT = 133 MHz and PD drive mode = ‘1’ for all
differential outputs. This diagram and description is applicable
to valid CPU frequencies 100,133,166,200,266,333 and
400MHz. In the event that PD mode is desired as the initial
power-on state, PD must be asserted high in less than 10 uS
after asserting Vtt_PwrGd#.
CLK_REQ[A:B]# Deassertion (CLKREQ# -> HIGH)
The impact of deasserting the CLKREQ#[A:B] pins is all SRC
outputs that are set in the control registers to stoppable via
deassertion of CLKREQ#[A:B] are to be stopped after their
next transition. The final state of all stopped DIF signals is low,
both SRCT clock and SRCC clock outputs will not be driven.
PD (Power-down) Clarification
The VTT_PWRGD# /PD pin is a dual function pin. During initial
power up, the pin functions as VTT_PWRGD#. Once
VTT_PWRGD# has been sampled low by the clock chip, the
pin assumes PD functionality. The PD pin is an asynchronous
active high input used to shut off all clocks cleanly prior to
shutting off power to the device. This signal is synchronized
internal to the device prior to powering down the clock synthesizer. PD is also an asynchronous input for powering up the
system. When PD is asserted high, all clocks need to be driven
to a low value and held prior to turning off the VCOs and the
crystal oscillator.
PD
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
USB, 48MHz
DOT96T
DOT96C
PCI, 33 MHz
REF
Figure 4. Power-down Assertion Timing Waveform
PD Deassertion
The power-up latency is less than 1.8 ms. This is the time from
the deassertion of the PD pin or the ramping of the power
supply until the time that stable clocks are output from the
clock chip. All differential outputs stopped in a three-state
condition resulting from power down will be driven high in less
Document #: 38-07691 Rev. **
than 300 µs of PD deassertion to a voltage greater than 200
mV. After the clock chip’s internal PLL is powered up and
locked, all outputs will be enabled within a few clock cycles of
each other. Below is an example showing the relationship of
clocks coming up.
Page 11 of 22
PRELIMINARY
CY28442-2
Tstable
<1.8nS
PD
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
USB, 48MHz
DOT96T
DOT96C
PCI, 33MHz
REF
Tdrive_PWRDN#
<300µS, >200mV
Figure 5. Power-down Deassertion Timing Waveform
CPU_STP# Assertion
The CPU_STP# signal is an active low input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_STP# pin is asserted, all CPU outputs that are
set with the SMBus configuration to be stoppable via assertion
of CPU_STP# will be stopped within two–six CPU clock
periods after being sampled by two rising edges of the internal
CPUC clock. The final states of the stopped CPU signals are
CPUT = HIGH and CPUC = LOW. There is no change to the
output drive current values during the stopped state. The
CPUT is driven HIGH with a current value equal to 6 x (Iref),
and the CPUC signal will be Tri-stated.
CPU_STP#
CPUT
CPUC
Figure 6. CPU_STP# Assertion Waveform
CPU_STP# Deassertion
The deassertion of the CPU_STP# signal will cause all CPU
outputs that were stopped to resume normal operation in a
synchronous manner. Synchronous manner meaning that no
short or stretched clock pulses will be produce when the clock
resumes. The maximum latency from the deassertion to active
outputs is no more than two CPU clock cycles.
CPU_STP#
CPUT
CPUC
CPUT Internal
CPUC Internal
Tdrive_CPU_STP#,10nS>200mV
Figure 7. CPU_STP# Deassertion Waveform
Document #: 38-07691 Rev. **
Page 12 of 22
PRELIMINARY
CY28442-2
1.8mS
CPU_STOP#
PD
CPUT(Free Running
CPUC(Free Running
CPUT(Stoppable)
CPUC(Stoppable)
DOT96T
DOT96C
Figure 8. CPU_STP#= Driven, CPU_PD = Driven, DOT_PD = Driven
1.8mS
CPU_STOP#
PD
CPUT(Free Running)
CPUC(Free Running)
CPUT(Stoppable)
CPUC(Stoppable)
DOT96T
DOT96C
Figure 9. CPU_STP# = Tri-state, CPU_PD = Tri-state, DOT_PD = Tri-state
PCI_STP# Assertion
The PCI_STP# signal is an active LOW input used for
synchronous stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
PCI_STP#
time for capturing PCI_STP# going LOW is 10 ns (tSU). (See
Figure 10.) The PCIF clocks will not be affected by this pin if
their corresponding control bit in the SMBus register is set to
allow them to be free running.
Tsu
PCI_F
PCI
SRC 100MHz
Figure 10. PCI_STP# Assertion Waveform
Document #: 38-07691 Rev. **
Page 13 of 22
PRELIMINARY
CY28442-2
PCI_STP# Deassertion
The deassertion of the PCI_STP# signal will cause all PCI and
stoppable PCIF clocks to resume running in a synchronous
manner within two PCI clock periods after PCI_STP# transitions to a high level.
Tsu
Tdrive_SRC
PCI_STP#
PCI_F
PCI
SRC 100MHz
Figure 11. PCI_STP# Deassertion Waveform
Document #: 38-07691 Rev. **
Page 14 of 22
PRELIMINARY
CY28442-2
FS_A, FS_B,FS_C
VTT_PW RGD#
PW RGD_VRM
0.2-0.3mS
Delay
VDD Clock Gen
State 0
Clock State
W ait for
VTT_PW RGD#
State 1
State 2
Off
Clock Outputs
State 3
On
On
Off
Clock VCO
Device is not affected,
VTT_PW RGD# is ignored
Sample Sels
Figure 12. VTT_PWRGD# Timing Diagram
S2
S1
Delay
>0.25mS
VTT_PWRGD# = Low
Sample
Inputs straps
VDD_A = 2.0V
Wait for <1.8ms
S0
Power Off
S3
VDD_A = off
Normal
Operation
Enable Outputs
VTT_PWRGD# = toggle
Figure 13. Clock Generator Power-up/Run State Diagram
Document #: 38-07691 Rev. **
Page 15 of 22
PRELIMINARY
CY28442-2
Absolute Maximum Conditions
Parameter
Description
Condition
Min.
Max.
Unit
VDD
Core Supply Voltage
–0.5
4.6
V
VDD_A
Analog Supply Voltage
–0.5
4.6
V
VIN
Input Voltage
Relative to VSS
–0.5
VDD + 0.5
VDC
TS
Temperature, Storage
Non-functional
–65
150
°C
TA
Temperature, Operating Ambient
Functional
0
85
°C
TJ
Temperature, Junction
Functional
–
150
°C
ØJC
Dissipation, Junction to Case
Mil-STD-883E Method 1012.1
–
20
°C/W
ØJA
Dissipation, Junction to Ambient
JEDEC (JESD 51)
–
60
°C/W
ESDHBM
ESD Protection (Human Body Model)
MIL-STD-883, Method 3015
–
V
UL-94
Flammability Rating
At 1/8 in.
MSL
Moisture Sensitivity Level
2000
V–0
1
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing
is NOT required.
DC Electrical Specifications
Parameter
Description
Condition
All VDD’s
3.3V Operating Voltage
3.3 ± 5%
VILI2C
Input Low Voltage
SDATA, SCLK
VIHI2C
Input High Voltage
SDATA, SCLK
VIL_FS
FS_[A,B] Input Low Voltage
Min.
Max.
Unit
3.135
3.465
V
–
1.0
V
2.2
–
V
VSS – 0.3
0.35
V
0.7
VDD + 0.5
V
VSS – 0.3
0.35
V
VIH_FS
FS_[A,B] Input High Voltage
VILFS_C
FS_C Input Low Voltage
VIMFS_C
FS_C Input Middle Voltage
0.7
1.8
V
VIHFS_C
FS_C Input High Voltage
1.8
VDD + 0.5
V
VIL
3.3V Input Low Voltage
VSS – 0.3
0.8
V
VIH
3.3V Input High Voltage
2.0
VDD + 0.3
V
IIL
Input Low Leakage Current
except internal pull-up resistors, 0 < VIN < VDD
–5
5
µA
IIH
Input High Leakage Current
except internal pull-down resistors, 0 < VIN < VDD
–
5
µA
VOL
3.3V Output Low Voltage
IOL = 1 mA
VOH
3.3V Output High Voltage
IOH = –1 mA
IOZ
High-impedance Output
Current
CIN
COUT
LIN
Pin Inductance
VXIH
Xin High Voltage
VXIL
Xin Low Voltage
IDD3.3V
Dynamic Supply Current
At max. load and freq. per Figure 15
IPD3.3V
Power-down Supply Current
IPD3.3V
Power-down Supply Current
ITRI
Tri-state Current
–
0.4
V
2.4
–
V
–10
10
µA
Input Pin Capacitance
3
5
pF
Output Pin Capacitance
3
5
pF
Document #: 38-07691 Rev. **
–
7
nH
0.7VDD
VDD
V
0
0.3VDD
V
–
400
mA
PD asserted, Outputs Driven
–
70
mA
PD asserted, Outputs Tri-state
–
2
mA
Current in tri-state mode
–
100
mA
Page 16 of 22
PRELIMINARY
CY28442-2
AC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
47.5
52.5
%
69.841
71.0
ns
–
10.0
ns
Crystal
TDC
XIN Duty Cycle
The device will operate reliably with input
duty cycles up to 30/70 but the REF clock
duty cycle will not be within specification
TPERIOD
XIN Period
When XIN is driven from an external
clock source
TR / TF
XIN Rise and Fall Times
Measured between 0.3VDD and 0.7VDD
TCCJ
XIN Cycle to Cycle Jitter
As an average over 1-µs duration
–
500
ps
LACC
Long-term Accuracy
Over 150 ms
–
300
ppm
CPU at 0.7V
TDC
CPUT and CPUC Duty Cycle
Measured at crossing point VOX
45
55
%
TPERIOD
100-MHz CPUT and CPUC Period
Measured at crossing point VOX
9.997001
10.00300
ns
TPERIOD
133-MHz CPUT and CPUC Period
Measured at crossing point VOX
7.497751
7.502251
ns
TPERIOD
166-MHz CPUT and CPUC Period
Measured at crossing point VOX
5.998201
6.001801
ns
TPERIOD
200-MHz CPUT and CPUC Period
Measured at crossing point VOX
4.998500
5.001500
ns
TPERIODSS
100-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX
9.997001
10.05327
ns
TPERIODSS
133-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX
7.497751
7.539950
ns
TPERIODSS
166-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX
5.998201
6.031960
ns
TPERIODSS
200-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX
4.998500
5.026634
ns
TPERIODAbs
100-MHz CPUT and CPUC Absolute
period
Measured at crossing point VOX
9.912001
10.08800
ns
TPERIODAbs
133-MHz CPUT and CPUC Absolute
period
Measured at crossing point VOX
7.412751
7.587251
ns
TPERIODAbs
166-MHz CPUT and CPUC Absolute
period
Measured at crossing point VOX
5.913201
6.086801
ns
TPERIODAbs
200-MHz CPUT and CPUC Absolute
period
Measured at crossing point VOX
4.913500
5.086500
ns
TPERIODSSAbs 100-MHz CPUT and CPUC Absolute
period, SSC
Measured at crossing point VOX
9.912001
10.13827
ns
TPERIODSSAbs 133-MHz CPUT and CPUC Absolute
period, SSC
Measured at crossing point VOX
7.412751
7.624950
ns
TPERIODSSAbs 166-MHz CPUT and CPUC Absolute
period, SSC
Measured at crossing point VOX
5.913201
6.116960
ns
TPERIODSSAbs 200-MHz CPUT and CPUC Absolute
period, SSC
Measured at crossing point VOX
4.913500
5.111634
ns
TCCJ
CPUT/C Cycle to Cycle Jitter
Measured at crossing point VOX
–
85
ps
TCCJ2
CPU2_ITP Cycle to Cycle Jitter
Measured at crossing point VOX
–
125
ps
TSKEW2
CPU2_ITP to CPU0 Clock Skew
Measured at crossing point VOX
–
150
ps
TR / TF
CPUT and CPUC Rise and Fall Time
Measured from VOL = 0.175 to VOH =
0.525V
175
700
ps
TRFM
Rise/Fall Matching
Determined as a fraction of 2*(TR –
TF)/(TR + TF)
–
20
%
∆TR
Rise Time Variation
–
125
ps
∆TF
Fall Time Variation
–
125
ps
VHIGH
Voltage High
Math averages Figure 15
660
850
mV
VLOW
Voltage Low
Math averages Figure 15
–150
–
mV
VOX
Crossing Point Voltage at 0.7V Swing
250
550
mV
Document #: 38-07691 Rev. **
Page 17 of 22
PRELIMINARY
CY28442-2
AC Electrical Specifications (continued)
Parameter
Description
Min.
Max.
Unit
–
VHIGH +
0.3
V
–0.3
–
V
See Figure 15. Measure SE
–
0.2
V
SRCT and SRCC Duty Cycle
Measured at crossing point VOX
45
55
%
VOVS
Maximum Overshoot Voltage
VUDS
Minimum Undershoot Voltage
VRB
Ring Back Voltage
SRC
TDC
Condition
TPERIOD
100-MHz SRCT and SRCC Period
Measured at crossing point VOX
9.997001
10.00300
ns
TPERIODSS
100-MHz SRCT and SRCC Period, SSC Measured at crossing point VOX
9.997001
10.05327
ns
TPERIODAbs
100-MHz SRCT and SRCC Absolute
Period
Measured at crossing point VOX
9.872001
10.12800
ns
TPERIODSSAbs 100-MHz SRCT and SRCC Absolute
Period, SSC
Measured at crossing point VOX
9.872001
10.17827
ns
TSKEW
Any SRCT/C to SRCT/C Clock Skew
Measured at crossing point VOX
–
100
ps
TCCJ
SRCT/C Cycle to Cycle Jitter
Measured at crossing point VOX
–
125
ps
LACC
SRCT/C Long Term Accuracy
Measured at crossing point VOX
–
300
ppm
TR / TF
SRCT and SRCC Rise and Fall Time
Measured from VOL = 0.175 to VOH =
0.525V
175
700
ps
TRFM
Rise/Fall Matching
Determined as a fraction of 2*(TR –
TF)/(TR + TF)
–
20
%
∆TR
Rise TimeVariation
–
125
ps
∆TF
Fall Time Variation
–
125
ps
VHIGH
Voltage High
Math averages Figure 15
660
850
mV
VLOW
Voltage Low
Math averages Figure 15
–150
–
mV
VOX
Crossing Point Voltage at 0.7V Swing
250
550
mV
VOVS
Maximum Overshoot Voltage
–
VHIGH +
0.3
V
VUDS
Minimum Undershoot Voltage
–0.3
–
V
VRB
Ring Back Voltage
–
0.2
V
PCI/PCIF
TDC
PCI Duty Cycle
Measurement at 1.5V
45
55
%
TPERIOD
Spread Disabled PCIF/PCI Period
Measurement at 1.5V
29.99100
30.00900
ns
TPERIODSS
Spread Enabled PCIF/PCI Period, SSC Measurement at 1.5V
29.9910
30.15980
ns
TPERIODAbs
Spread Disabled PCIF/PCI Period
Measurement at 1.5V
29.49100
30.50900
ns
TPERIODSSAbs Spread Enabled PCIF/PCI Period, SSC Measurement at 1.5V
See Figure 15. Measure SE
29.49100
30.65980
ns
Measurement at 2.4V
12.0
–
ns
PCIF and PCI low time
Measurement at 0.4V
12.0
–
ns
PCIF/PCI rising and falling Edge Rate
Measured between 0.8V and 2.0V
1.0
4.0
V/ns
TSKEW
Any PCI clock to Any PCI clock Skew
Measurement at 1.5V
–
500
ps
TCCJ
PCIF and PCI Cycle to Cycle Jitter
Measurement at 1.5V
–
500
ps
DOT
TDC
DOT96T and DOT96C Duty Cycle
Measured at crossing point VOX
45
55
%
TPERIOD
DOT96T and DOT96C Period
Measured at crossing point VOX
10.41354
10.41979
ns
TPERIODAbs
DOT96T and DOT96C Absolute Period Measured at crossing point VOX
10.16354
10.66979
ns
TCCJ
DOT96T/C Cycle to Cycle Jitter
Measured at crossing point VOX
–
250
ps
LACC
DOT96T/C Long Term Accuracy
Measured at crossing point VOX
–
100
ppm
THIGH
PCIF and PCI high time
TLOW
TR / TF
Document #: 38-07691 Rev. **
Page 18 of 22
PRELIMINARY
CY28442-2
AC Electrical Specifications (continued)
Parameter
Description
Condition
Min.
Max.
Unit
175
700
ps
–
20
%
–
125
ps
–
125
ps
660
850
mV
TR / TF
DOT96T and DOT96C Rise and Fall
Time
Measured from VOL = 0.175 to VOH =
0.525V
TRFM
Rise/Fall Matching
Determined as a fraction of 2*(TR –
TF)/(TR + TF)
∆TR
Rise Time Variation
∆TF
Fall Time Variation
VHIGH
Voltage High
Math averages Figure 15
VLOW
Voltage Low
Math averages Figure 15
–150
–
mV
VOX
Crossing Point Voltage at 0.7V Swing
250
550
mV
VOVS
Maximum Overshoot Voltage
–
VHIGH +
0.3
V
VUDS
Minimum Undershoot Voltage
–0.3
–
V
VRB
Ring Back Voltage
See Figure 15. Measure SE
–
0.2
V
USB
TDC
Duty Cycle
Measurement at 1.5V
45
55
%
TPERIOD
Period
Measurement at 1.5V
20.83125
20.83542
ns
TPERIODAbs
Absolute Period
Measurement at 1.5V
20.48125
21.18542
ns
THIGH
USB high time
Measurement at 2.4V
8.094
10.036
ns
TLOW
USB low time
Measurement at 0.4V
7.694
9.836
ns
TR / TF
Rising and Falling Edge Rate
Measured between 0.8V and 2.0V
1.0
2.0
V/ns
TCCJ
Cycle to Cycle Jitter
Measurement at 1.5V
–
350
ps
REF
TDC
REF Duty Cycle
Measurement at 1.5V
45
55
%
TPERIOD
REF Period
Measurement at 1.5V
69.8203
69.8622
ns
TPERIODAbs
REF Absolute Period
Measurement at 1.5V
68.82033
70.86224
ns
TR / TF
REF Rising and Falling Edge Rate
Measured between 0.8V and 2.0V
1.0
4.0
V/ns
TCCJ
REF Cycle to Cycle Jitter
Measurement at 1.5V
–
1000
ps
ENABLE/DISABLE and SET-UP
TSTABLE
Clock Stabilization from Power-up
TSS
Stopclock Set-up Time
TSH
Stopclock Hold Time
–
1.8
ms
10.0
–
ns
0
–
ns
Test and Measurement Set-up
For PCI Single-ended Signals and Reference
The following diagram shows the Single ended PCI outputs.
Output under Test
tDC
Probe
3.3V
2.4V
1.5V
0.4V
30
pF
Load
Cap
0V
Tr
Tf
Figure 14. Single ended PCI lumped load configuration
Document #: 38-07691 Rev. **
Page 19 of 22
PRELIMINARY
CY28442-2
The following diagram shows the test load configuration for the
differential CPU and SRC outputs.
M e a s u re m e n t
P o in t
33Ω
CPUT
SRCT
D O T96T
96_100SSC T
4 9 .9 Ω
2pF
1 0 0 Ω D if f e r e n t ia l
M e a s u re m e n t
P o in t
33Ω
CPUC
SRCC
D O T96C
96_100SSC C
2pF
4 9 .9 Ω
IR E F
475Ω
Figure 15. 0.7V Differential clock Load Configuration
3 .3 V s ig n a l s
T DC
-
-
3 .3 V
2 .4 V
1 .5 V
0 .4 V
0V
TF
TR
Figure 16. Single-ended Output Signals (for AC Parameters Measurement)
Ordering Information
Part Number
Package Type
Product Flow
Lead-free
CY28442ZXC-2
56-pin TSSOP
Commercial, 0° to 85°C
CY28442ZXC-2T
56-pin TSSOP – Tape and Reel
Commercial, 0° to 85°C
Document #: 38-07691 Rev. **
Page 20 of 22
PRELIMINARY
CY28442-2
Package Diagrams
56-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z56
0.249[0.009]
28
1
DIMENSIONS IN MM[INCHES] MIN.
MAX.
REFERENCE JEDEC MO-153
7.950[0.313]
8.255[0.325]
PACKAGE WEIGHT 0.42gms
5.994[0.236]
6.198[0.244]
PART #
Z5624 STANDARD PKG.
ZZ5624 LEAD FREE PKG.
29
56
13.894[0.547]
14.097[0.555]
1.100[0.043]
MAX.
GAUGE PLANE
0.25[0.010]
0.20[0.008]
0.851[0.033]
0.950[0.037]
0.500[0.020]
BSC
0.170[0.006]
0.279[0.011]
0.051[0.002]
0.152[0.006]
0°-8°
SEATING
PLANE
0.508[0.020]
0.762[0.030]
0.100[0.003]
0.200[0.008]
51-85060-*C
Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document
are the trademarks of their respective holders.
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips
I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification
as defined by Philips.
Document #: 38-07691 Rev. **
Page 21 of 22
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Cypress products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress.
PRELIMINARY
CY28442-2
Document History Page
Document Title: CY28442-2 Clock Generator for Intel Alviso Chipset
Document Number: 38-07691
REV.
ECN NO.
Issue Date
Orig. of
Change
**
237627
See ECN
RGL
Document #: 38-07691 Rev. **
Description of Change
New Data Sheet
Page 22 of 22