MoBL®,CY62126EV30 1-Mbit (64K x 16) Static RAM Features Functional Description ■ High speed: 45 ns The CY62126EV30 is a high performance CMOS static RAM organized as 64K words by 16 bits[1]. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. Placing the device in standby mode reduces power consumption by more than 99 percent when deselected (CE HIGH). The input and output pins (IO0 through IO15) are placed in a high impedance state when: ■ Temperature ranges ❐ Industrial: –40°C to +85°C ❐ Automotive: –40°C to +125°C ■ Wide voltage range: 2.2V to 3.6V ■ Pin compatible with CY62126DV30 ■ Ultra low standby power ❐ Typical standby current: 1 μA ❐ Maximum standby current: 4 μA ■ Ultra low active power ❐ Typical active current: 1.3 mA at f = 1 MHz ■ Easy memory expansion with CE and OE features ■ Automatic power down when deselected ■ CMOS for optimum speed and power ■ Offered in Pb-free 48-ball VFBGA and 44-pin TSOP II packages ■ Deselected (CE HIGH) ■ Outputs are disabled (OE HIGH) ■ Both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH) ■ Write operation is active (CE LOW and WE LOW) To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0 through IO7) is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A15). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from memory appears on IO8 to IO15. See the “Truth Table” on page 9 for a complete description of read and write modes. Logic Block Diagram Note 1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines. Cypress Semiconductor Corporation Document #: 38-05486 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 5, 2009 [+] Feedback MoBL®, CY62126EV30 Pin Configurations Figure 2. 44-Pin TSOP II (Top View)[2] Figure 1. 44-Ball VFBGA (Top View) Table 1. Product Portfolio Power Dissipation Product VCC Range (V) Range Speed (ns) Min Typ[3] Max CY62126EV30LL Industrial 2.2 3.0 3.6 CY62126EV30LL Automotive 2.2 3.0 3.6 Operating, ICC (mA) f = 1 MHz f = fmax Standby, ISB2 (μA) Typ[3] Max Typ[3] Max Typ[3] Max 45 1.3 2 11 16 1 4 55 1.3 4 11 35 1 30 Notes 2. NC pins are not connected on the die. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C. Document #: 38-05486 Rev. *E Page 2 of 13 [+] Feedback MoBL®, CY62126EV30 DC Input Voltage[4, 5] ...............−0.3V to 3.6V (VCCmax + 0.3V) Maximum Ratings Exceeding maximum ratings may shorten the battery life of the device. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied ............................................ –55°C to +125°C Supply Voltage to Ground Potential................................. –0.3V to 3.6V (VCCmax + 0.3V) Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (MIL-STD-883, Method 3015) Latch up Current.................................................... > 200 mA Operating Range DC Voltage Applied to Outputs in High-Z State[4, 5] ................ –0.3V to 3.6V (VCCmax + 0.3V) Device Range Ambient Temperature VCC[6] CY62126EV30LL Industrial –40°C to +85°C 2.2V to 3.6V Automotive –40°C to +125°C Electrical Characteristics (Over the Operating Range) Parameter VOH Description Test Conditions Output HIGH Voltage IOH = –0.1 mA IOH = –1.0 mA, VCC > 2.70V VOL Output LOW Voltage VIH Input HIGH Voltage 45 ns (Industrial) Min Typ[1] Max 55 ns (Automotive) Min Typ[1] Unit Max 2.0 2.0 V 2.4 2.4 V IOL = 0.1 mA 0.4 IOL = 2.1mA, VCC > 2.70V 0.4 0.4 V 0.4 V VCC = 2.2V to 2.7V 1.8 VCC + 0.3 1.8 VCC + 0.3 V VCC = 2.7V to 3.6V 2.2 VCC + 0.3 2.2 VCC + 0.3 V VCC = 2.2V to 2.7V –0.3 0.6 –0.3 0.6 V VCC = 2.7V to 3.6V VIL Input LOW Voltage –0.3 0.8 –0.3 0.8 V IIX Input Leakage Current GND < VI < VCC –1 +1 –4 +4 μA IOZ Output Leakage Current –1 +1 –4 +4 μA ICC VCC Operating Supply f = fmax = 1/tRC Current f = 1 MHz mA GND < VO < VCC, Output Disabled VCC = VCCmax IOUT = 0 mA CMOS levels 11 16 11 35 1.3 2.0 1.3 4.0 ISB1 Automatic CE Power down Current —CMOS Inputs CE > VCC − 0.2V, VIN > VCC – 0.2V, VIN < 0.2V) f = fmax (Address and Data Only), f = 0 (OE, BHE, BLE and WE), VCC = 3.60V 1 4 1 35 μA ISB2 [7] Automatic CE Power down Current —CMOS Inputs CE > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V, f = 0, VCC = 3.60V 1 4 1 30 μA Capacitance For all packages. Tested initially and after any design or process changes that may affect these parameters. Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = VCC(typ) Max Unit 10 pF 10 pF Notes 4. VIL(min) = –2.0V for pulse durations less than 20 ns. 5. VIH(max) = VCC+0.75V for pulse durations less than 20 ns. 6. Full device AC operation assumes a 100 μs ramp time from 0 to Vcc(min) and 200 μs wait time after Vcc stabilization. 7. Only chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating. Document #: 38-05486 Rev. *E Page 3 of 13 [+] Feedback MoBL®, CY62126EV30 Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter Test Conditions VFBGA Package TSOP II Package Unit Still Air, soldered on a 4.25 x 1.125 inch, two-layer printed circuit board 58.85 28.2 °C/W 17.01 3.4 °C/W Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Figure 3. AC Test Loads and Waveforms R1 VCC OUTPUT VCC 30 pF 10% GND Rise Time = 1 V/ns R2 INCLUDING JIG AND SCOPE ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT VTH Parameters 2.2V - 2.7V 2.7V - 3.6V Unit R1 16600 1103 Ohms R2 15400 1554 Ohms RTH 8000 645 Ohms VTH 1.2 1.75 Volts Data Retention Characteristics Over the Operating Range Parameter Description VDR VCC for Data Retention ICCDR[7] Data Retention Current tCDR [8] tR[9] Conditions Min Typ[1] Max 1.5 VCC= VDR, CE > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V Unit V Industrial 3 μA Automotive 30 μA Chip Deselect to Data Retention Time 0 ns Operation Recovery Time tRC ns Figure 4. Data Retention Waveform VCC VCC(min) DATA RETENTION MODE VDR > 1.5V tCDR VCC(min) tR CE Notes 8. Tested initially and after any design or process changes that may affect these parameters. 9. Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 μs. Document #: 38-05486 Rev. *E Page 4 of 13 [+] Feedback MoBL®, CY62126EV30 Switching Characteristics Over the Operating Range [10, 11] Parameter 45 ns (Industrial) Description Min Max 55 ns (Automotive) Min Max Unit Read Cycle tRC Read Cycle Time tAA Address to Data Valid 45 tOHA Data Hold from Address Change tACE CE LOW to Data Valid 45 55 ns tDOE OE LOW to Data Valid 22 25 ns 20 ns [12] tLZOE OE LOW to Low Z tHZOE OE HIGH to High Z [12, 13] tLZCE CE LOW to Low Z [12] tPU CE LOW to Power Up tPD CE HIGH to Power Down tDBE BHE / BLE LOW to Data Valid BHE / BLE LOW to Low Z 10 0 [12] BHE / BLE HIGH to High Z ns 20 0 ns ns 45 55 ns 22 25 ns 5 [12, 13] ns 10 18 ns ns 5 10 [12, 13] ns 55 18 CE HIGH to High Z tHZBE 10 5 tHZCE tLZBE 55 45 5 18 ns 20 ns Write Cycle [14] tWC Write Cycle Time 45 55 ns tSCE CE LOW to Write End 35 40 ns tAW Address Setup to Write End 35 40 ns tHA Address Hold from Write End 0 0 ns tSA Address Setup to Write Start 0 0 ns tPWE WE Pulse Width 35 40 ns tBW BHE / BLE Pulse Width 35 40 ns tSD Data Setup to Write End 25 25 ns tHD Data Hold from Write End 0 0 ns tHZWE tLZWE WE LOW to High Z [12, 13] WE HIGH to Low Z [12] 18 10 20 10 ns ns Notes 10. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH and 30-pF load capacitance. 11. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification. 12. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 13. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 14. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must refer to the edge of signal that terminates write. Document #: 38-05486 Rev. *E Page 5 of 13 [+] Feedback MoBL®, CY62126EV30 Switching Waveforms Figure 5. Read Cycle No. 1(Address transition controlled)[15, 16] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 6. Read Cycle No. 2 (OE controlled)[16, 17] ADDRESS tRC CE tPD tHZCE tACE OE tHZOE tDOE tLZOE BHE/BLE tHZBE tDBE tLZBE DATA OUT HIGHIMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE tPU VCC SUPPLY CURRENT 50% 50% ICC ISB Notes 15. The device is continuously selected. OE, CE = VIL, BHE, BLE, or both = VIL. 16. WE is HIGH for read cycle. 17. Address valid before or similar to CE and BHE, BLE transition LOW. Document #: 38-05486 Rev. *E Page 6 of 13 [+] Feedback MoBL®, CY62126EV30 Switching Waveforms (continued) Figure 7. Write Cycle No. 1 (WE controlled)[14, 18, 19] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE/BLE OE DATA IO tSD NOTE 20 tHD DATAIN tHZOE Figure 8. Write Cycle No. 2 (CE controlled)[14, 18, 19] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tBW BHE/BLE OE tSD DATA IO tHD DATAIN NOTE 20 tHZOE Notes 18. Data IO is high impedance if OE = VIH. 19. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state. 20. During this period, the IOs are in output state. Do not apply input signals. Document #: 38-05486 Rev. *E Page 7 of 13 [+] Feedback MoBL®, CY62126EV30 Switching Waveforms (continued) Figure 9. Write Cycle No. 3 (WE controlled, OE LOW [19] tWC ADDRESS tSCE CE tBW BHE/BLE tAW tHA tSA WE tPWE tSD DATA IO NOTE 20 tHD DATAIN tLZWE tHZWE Figure 10. Write Cycle No. 4 (BHE/BLE controlled, OE LOW)[19] tWC ADDRESS CE tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tHZWE DATA IO NOTE 20 tSD tHD DATAIN tLZWE Document #: 38-05486 Rev. *E Page 8 of 13 [+] Feedback MoBL®, CY62126EV30 Truth Table CE WE OE BHE BLE H X X X X High Z Inputs/Outputs Deselect/Power Down Mode Standby (ISB) Power L X X H H High Z Output Disabled Active (ICC) L H L L L Data Out (IO0–IO15) Read Active (ICC) L H L H L Data Out (IO0–IO7); IO8–IO15 in High Z Read Active (ICC) L H L L H Data Out (IO8–IO15); IO0–IO7 in High Z Read Active (ICC) L H H L L High Z Output Disabled Active (ICC) L H H H L High Z Output Disabled Active (ICC) L H H L H High Z Output Disabled Active (ICC) L L X L L Data In (IO0–IO15) Write Active (ICC) L L X H L Data In (IO0–IO7); IO8–IO15 in High Z Write Active (ICC) L L X L H Data In (IO8–IO15); IO0–IO7 in High Z Write Active (ICC) Ordering Information Speed (ns) 45 55 Ordering Code Package Diagram Package Type CY62126EV30LL-45BVXI 51-85150 48-ball Very Fine Pitch Ball Grid Array (Pb-free) CY62126EV30LL-45ZSXI 51-85087 44-pin Thin Small Outline Package II (Pb-free) CY62126EV30LL-55BVXE 51-85150 48-ball Very Fine Pitch Ball Grid Array (Pb-free) CY62126EV30LL-55ZSXE 51-85087 44-pin Thin Small Outline Package II (Pb-free) Operating Range Industrial Automotive Contact your local Cypress sales representative for availability of other parts. Document #: 38-05486 Rev. *E Page 9 of 13 [+] Feedback MoBL®, CY62126EV30 Package Diagrams Figure 11. 48-Ball VFBGA (6 x 8 x 1 mm) (51-85150) BOTTOM VIEW TOP VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 2 3 4 5 6 6 5 4 3 2 1 C C E F G D E 2.625 D 0.75 A B 5.25 A B 8.00±0.10 8.00±0.10 1 F G H H A 1.875 A B 0.75 6.00±0.10 3.75 0.55 MAX. 6.00±0.10 0.10 C 0.21±0.05 0.25 C B 0.15(4X) Document #: 38-05486 Rev. *E 1.00 MAX 0.26 MAX. SEATING PLANE C 51-85150-*D Page 10 of 13 [+] Feedback MoBL®, CY62126EV30 Package Diagrams (continued) Figure 12. 44-Pin TSOP II (51-85087) 51-85087-*A Document #: 38-05486 Rev. *E Page 11 of 13 [+] Feedback MoBL®, CY62126EV30 Document History Page Document Title: MoBL® CY62126EV30, 1-Mbit (64K x 16) Static RAM Document Number: 38-05486 Rev. ECN No. Submission Date Orig. of Change Description of Change ** 202760 See ECN AJU New data sheet *A 300835 See ECN SYT Converted from Advance Information to Preliminary Specified Typical standby power in the Features Section Changed E3 ball from DNU to NC in the Pin Configuration for the FBGA Package and removed the footnote associated with it on page #2 Changed tOHA from 6 ns to 10 ns for both 35- and 45-ns speed bins, respectively Changed tDOE, tSD from 15 to 18 ns for 35-ns speed bin Changed tHZOE, tHZBE, tHZWE from 12 and 15 ns to 15 and 18 ns for the 35- and 45-ns speed bins, respectively Changed tHZCE from 12 and 15 ns to 18 and 22 ns for the 35- and 45-ns speed bins, respectively Changed tSCE,tBW from 25 and 40 ns to 30 and 35 ns for the 35- and 45-ns speed bins, respectively Changed tAW from 25 to 30 ns and 40 to 35 ns for 35 and 45-ns speed bins respectively Changed tDBE from 35 and 45 ns to 18 and 22 ns for the 35 and 45 ns speed bins respectively Removed footnote that read “BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE” on page # 4 Removed footnote that read “If both BHE and BLE are toggled together, then tLZBE is 10 ns” on page # 5 Added Pb-free package information *B 461631 See ECN NXR Converted from Preliminary to Final Removed 35 ns Speed Bin Removed “L” version of CY62126EV30 Changed ICC (Typ) from 8 mA to 11 mA and ICC (max) from 12 mA to 16 mA for f = fmax Changed ICC (max) from 1.5 mA to 2.0 mA for f = 1 MHz Changed ISB1, ISB2 (max) from 1 μA to 4 μA Changed ISB1, ISB2 (Typ) from 0.5 μA to 1 μA Changed ICCDR (max) from 1.5 μA to 3 μA Changed the AC Test load Capacitance value from 50 pF to 30 pF Changed tLZOE from 3 to 5 ns Changed tLZCE from 6 to 10 ns Changed tHZCE from 22 to 18 ns Changed tLZBE from 6 to 5 ns Changed tPWE from 30 to 35 ns Changed tSD from 22 to 25 ns Changed tLZWE from 6 to 10 ns Updated the Ordering Information table. *C 925501 See ECN VKN Added footnote #7 related to ISB2 and ICCDR Added footnote #11 related AC timing parameters *D 1045260 See ECN VKN Added Automotive information Updated Ordering Information table *E 2631771 01/07/09 Document #: 38-05486 Rev. *E NXR/PYRS Changed CE condition from X to L in Truth table for Output Disable mode Updated template Page 12 of 13 [+] Feedback MoBL®, CY62126EV30 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers PSoC Solutions psoc.cypress.com clocks.cypress.com General Low Power/Low Voltage psoc.cypress.com/solutions psoc.cypress.com/low-power Wireless wireless.cypress.com Precision Analog Memories memory.cypress.com LCD Drive psoc.cypress.com/lcd-drive image.cypress.com CAN 2.0b psoc.cypress.com/can USB psoc.cypress.com/usb Image Sensors psoc.cypress.com/precision-analog © Cypress Semiconductor Corporation, 2008-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-05486 Rev. *E Revised January 5, 2009 Page 13 of 13 MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback