PRELIMINARY CY23S08 3.3V Zero Delay Buffer Features • Zero input-output propagation delay, adjustable by capacitive load on FBK input • Multiple configurations, see Table 2 • Multiple low-skew outputs — Output-output skew less than 200 ps — Device-device skew less than 700 ps — Two banks of four outputs, three-stateable by two select inputs • 10-MHz to 133-MHz operating range • Low jitter, less than 200 ps cycle-cycle (–1, –1H, –4) • Advanced 0.65µ CMOS technology • Space-saving 16-pin 150-mil SOIC/TSSOP packages • 3.3V operation • Spread Aware™ Functional Description The CY23S08 is a 3.3V zero delay buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high-performance applications. The part has an on-chip PLL which locks to an input clock presented on the REF pin. The PLL feedback is required to be driven into the FBK pin, and can be obtained from one of the outputs. The input-to-output propagation delay is guaranteed to be less than 350 ps, and output-to-output skew is guaranteed to be less than 250 ps. The CY23S08 has two banks of four outputs each, which can be controlled by the Select inputs as shown in Table 1. If all output clocks are not required, Bank B can be three-stated. The select inputs also allow the input clock to be directly applied to the output for chip and system testing purposes. The CY23S08 PLL enters a power-down state when there are no rising edges on the REF input. In this mode, all outputs are three-stated and the PLL is turned off, resulting in less than 50 µA of current draw. The PLL shuts down in two additional cases as shown in Table 1. Multiple CY23S08 devices can accept the same input clock and distribute it in a system. In this case, the skew between the outputs of two devices is guaranteed to be less than 700 ps. The CY23S08 is available in five different configurations, as shown in Table 2. The CY23S08–1 is the base part, where the output frequencies equal the reference if there is no counter in the feedback path. The CY23S08–1H is the high-drive version of the –1, and rise and fall times on this device are much faster. The CY23S08–2 allows the user to obtain 2X and 1X frequencies on each output bank. The exact configuration and output frequencies depends on which output drives the feedback pin. The CY23S08–2H is the high-drive version of the –2, and rise and fall times on this device are much faster. The CY23S08–3 allows the user to obtain 4X and 2X frequencies on the outputs. The CY23S08–4 enables the user to obtain 2X clocks on all outputs. Thus, the part is extremely versatile, and can be used in a variety of applications. Pin Configuration Block Diagram /2 PLL FBK MUX REF SOIC Top View CLKA1 CLKA2 Extra Divider (–3, –4) CLKA3 S2 S1 CLKA4 Select Input Decoding /2 CLKB1 REF CLKA1 1 16 2 15 CLKA2 VDD 3 14 4 13 GND CLKB1 CLKB2 S2 5 12 6 11 7 10 8 9 FBK CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1 CLKB2 CLKB3 Extra Divider (–2, –2H, –3) Cypress Semiconductor Corporation Document #: 38-07265 Rev. *D CLKB4 • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised June 03, 2004 PRELIMINARY CY23S08 Table 1. Select Input Decoding S2 S1 CLOCK A1–A4 CLOCK B1–B4 Output Source PLL Shutdown 0 0 Three-State Three-State PLL Y 0 1 Driven Three-State PLL N 1 0 Driven Driven Reference Y Driven PLL N 1 1 Driven Table 2. Available CY23S08 Configurations Device Feedback From Bank A Frequency Bank B Frequency CY23S08–1 Bank A or Bank B Reference Reference CY23S08–1H Bank A or Bank B Reference Reference CY23S08–2 Bank A Reference Reference/2 CY23S08–2H Bank A Reference Reference/2 CY23S08–2 Bank B 2 X Reference Reference CY23S08–2H Bank B 2 X Reference Reference CY23S08–3 Bank A 2 X Reference Reference or Reference[1] CY23S08–3 Bank B 4 X Reference 2 X Reference CY23S08–4 Bank A or Bank B 2 X Reference 2 X Reference Pin Description Pin Signal Description 1 REF[2] Input reference frequency, 5V tolerant input 2 CLKA1[3] Clock output, Bank A 3 CLKA2[3] Clock output, Bank A 4 VDD 3.3V supply 5 GND Ground 6 CLKB1[3] Clock output, Bank B 7 CLKB2[3] Clock output, Bank B 8 S2[4] Select input, bit 2 9 S1[4] Select input, bit 1 10 CLKB3[3] Clock output, Bank B 11 CLKB4[3] Clock output, Bank B 12 GND Ground 13 VDD 3.3V supply 14 CLKA3[3] Clock output, Bank A 15 CLKA4[3] Clock output, Bank A 16 FBK PLL feedback input Spread Aware™ Many systems being designed now utilize a technology called Spread Spectrum Frequency Timing Generation. Cypress has been one of the pioneers of SSFTG development, and we designed this product so as not to filter off the Spread Spectrum feature of the Reference input, assuming it exists. When a zero delay buffer is not designed to pass the SS feature through, the result is a significant amount of tracking skew which may cause problems in systems requiring synchronization. For more details on Spread Spectrum timing technology, please see Cypress’s application note EMI Suppression Techniques with Spread Spectrum Frequency Timing Generator (SSFTG) ICs. Notes: 1. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the CY23S08–2. 2. Weak pull-down. 3. Weak pull-down on all outputs. 4. Weak pull-ups on these inputs. Document #: 38-07265 Rev. *D Page 2 of 8 PRELIMINARY Maximum Ratings CY23S08 Storage Temperature ................................. –65°C to +150°C Supply Voltage to Ground Potential ............... –0.5V to +7.0V DC Input Voltage (Except Ref)...............–0.5V to VDD + 0.5V DC Input Voltage REF............................................–0.5 to 7V Max. Soldering Temperature (10 sec.) ....................... 260°C Junction Temperature ................................................. 150°C Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................. >2000V Operating Conditions for CY23S08SC-XX Commercial Temperature Devices[5] Parameter Description Min. Max. Unit 3.0 3.6 V 0 70 °C VDD Supply Voltage TA Operating Temperature (Ambient Temperature) CL Load Capacitance, below 100 MHz 30 pF Load Capacitance, from 100 MHz to 133 MHz 15 pF 7 pF Max Unit 0.8 V CIN Input Capacitance [6] Electrical Characteristics for CY23S08SC-XX Commercial Temperature Devices Parameter Description Test Conditions Min. VIL Input LOW Voltage VIH Input HIGH Voltage IIL Input LOW Current VIN = 0V 50.0 µA 100.0 µA 0.4 V 2.0 V IIH Input HIGH Current VIN = VDD VOL Output LOW Voltage[7] IOL = 8 mA (–1, –2, –3, –4) IOL = 12 mA (-1H, -2H) VOH Output HIGH Voltage[7] IOH = –8 mA (–1, –2, –3, –4) IOH = –12 mA (–1H, –2H) IDD (PD mode) Power-down Supply Current REF = 0 MHz 12.0 IDD Supply Current 45.0 mA 70.0 (–1H, –2H) mA Unloaded outputs, 66-MHz REF (–1,–2,–3,–4) 32.0 mA Unloaded outputs, 33-MHz REF (–1,–2,–3,–4) 18.0 mA 2.4 Unloaded outputs, 100-MHz REF, Select inputs at VDD or GND V µA Switching Characteristics for CY23S08SC-XX Commercial Temperature Devices [8] Parameter Name Test Conditions Min. Typ. Max. Unit t1 Output Frequency 30-pF load, –1, –1H, –2, –3 devices 10 100 MHz t1 Output Frequency 30-pF load, –4 devices 15 100 MHz t1 Output Frequency 20-pF load, –1H device 10 133.3 MHz t1 Output Frequency 15-pF load, –1, –2, –3, devices 10 140.0 MHz t1 Output Frequency 15-pF load, –4 devices 140.0 MHz Duty Cycle[7] = t2 ÷ t1 (–1,–2,–3,–4,–1H, -2H) Measured at VDD/2, FOUT = 66.66 MHz 30-pF load 40.0 15 50.0 60.0 % Duty Cycle[7] = t2 ÷ t1 (–1,–2,–3,–4,–1H, -2H) Measured at VDD/2, FOUT <66.66 MHz 15-pf load 45.0 50.0 55.0 % t3 Rise Time[7] (–1, –2, –3, –4) Measured between 0.8V and 2.0V, 30-pF load 2.20 ns t3 Rise Time[7] (–1, –2, –3, –4) 1.50 ns Measured between 0.8V and 2.0V, 15-pF load Notes: 5. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 6. Applies to both Ref Clock and FBK. 7. Parameter is guaranteed by design and characterization. Not 100% tested in production. 8. All parameters are specified with loaded outputs. Document #: 38-07265 Rev. *D Page 3 of 8 PRELIMINARY CY23S08 Switching Characteristics for CY23S08SC-XX Commercial Temperature Devices (continued)[8] Parameter Name Test Conditions Rise Time[7] (–1H, -2H) t3 [7] Max. Unit Measured between 0.8V and 2.0V, 30-pF load Min. Typ. 1.50 ns t4 Fall Time (–1, –2, –3, –4) Measured between 0.8V and 2.0V, 30-pF load 2.20 ns t4 Fall Time[7] (–1, –2, –3, –4) Measured between 0.8V and 2.0V, 15-pF load 1.50 ns [7] t4 Fall Time Measured between 0.8V and 2.0V, 30-pF load 1.25 ns t5 Output to Output Skew on same Bank (–1)[7] All outputs equally loaded 200 ps Output to Output Skew on same Bank (–1H,–2,–2H,–3)[7] All outputs equally loaded 150 ps Output to Output Skew on same Bank (–4)[7] All outputs equally loaded 100 ps Output to Output Skew (–1H, -2H) All outputs equally loaded 200 ps Output Bank A to Output Bank B Skew (–1,–2, –3) All outputs equally loaded 300 ps Output Bank A to Output Bank B Skew (–4) All outputs equally loaded 215 ps Output Bank A to Output Bank B Skew (–1H) All outputs equally loaded 250 ps 0 +275 ps 0 700 ps (–1H, 2H) t6 Delay, REF Rising Edge to Measured at VDD/2 FBK Rising Edge[7] –250 t7 Device to Device Skew[7] Measured at VDD/2 on the FBK pins of devices t8 Output Slew Rate[7] Measured between 0.8V and 2.0V on –1H, –2H device using Test Circuit #2 tJ Cycle to Cycle Jitter[7] (–1, –1H) Measured at 66.67 MHz, loaded outputs, 15, 30-pF loads: 133 MHz, 15-pF load 125 ps Cycle to Cycle Jitter[7] (–2) Measured at 66.67 MHz, loaded outputs, 15-pF load 300 ps Cycle to Cycle Jitter[7] (–2) Measured at 66.67 MHz, loaded outputs, 30-pF load 400 ps tJ Cycle to Cycle Jitter[7] (–3,–4) Measured at 66.67 MHz, loaded outputs 15,30-pF loads 200 ps tLOCK PLL Lock Time[7] Stable power supply, valid clocks presented on REF and FBK pins 1.0 ms 1 V/ns Switching Waveforms Duty Cycle Timing t1 t2 1.4V 1.4V 1.4V All Outputs Rise/Fall Time OUTPUT 2.0V 0.8V t3 Document #: 38-07265 Rev. *D 2.0V 0.8V 3.3V 0V t4 Page 4 of 8 PRELIMINARY CY23S08 Switching Waveforms (continued) Output-Output Skew OUTPUT 1.4V 1.4V OUTPUT t5 Input-Output Propagation Delay INPUT VDD/2 VDD/2 FBK t6 Device-Device Skew VDD/2 FBK, Device 1 VDD/2 FBK, Device 2 t7 Test Circuits Test Circuit # 1 Test Circuit # 2 VDD V DD 0.1 µF OUTPUTS CLK OUT 0.1 µF GND Test Circuit for all parameters except t8 Document #: 38-07265 Rev. *D CLK out 10 pF V DD V DD GND OUTPUTS 1 KΩ C LOAD 0.1 µF 1 KΩ 0.1 µF GND GND Test Circuit for t8, Output slew rate on –1H device Page 5 of 8 PRELIMINARY CY23S08 Ordering Information Ordering Code Package Name Package Type Operating Range CY23S08SC–1 S16 16-pin 150-mil SOIC Commercial CY23S08SC–1T S16 16-pin 150-mil SOIC–Tape and Reel Commercial CY23S08SC–1H S16 16-pin 150-mil SOIC Commercial CY23S08SC–1HT S16 16-pin 150-mil SOIC–Tape and Reel Commercial CY23S08ZC–1H Z16 16-pin 150-mil TSSOP Commercial CY23S08ZC–1HT Z16 16-pin 150-mil TSSOP–Tape and Reel Commercial CY23S08SC–2 S16 16-pin 150-mil SOIC Commercial CY23S08SC–2T S16 16-pin 150-mil SOIC–Tape and Reel Commercial CY23S08SC–2H S16 16-pin 150-mil SOIC Commercial CY23S08SC–2HT S16 16-pin 150-mil SOIC–Tape and Reel Commercial CY23S08SC–3 S16 16-pin 150-mil SOIC Commercial CY23S08SC–3T S16 16-pin 150-mil SOIC–Tape and Reel Commercial CY23S08SC–4 S16 16-pin 150-mil SOIC Commercial CY23S08SC–4T S16 16-pin 150-mil SOIC–Tape and Reel Commercial Package Drawings and Dimensions 16-Lead (150-Mil) SOIC S16 PIN 1 ID 8 1 DIMENSIONS IN INCHES[MM] MIN. MAX. REFERENCE JEDEC MS-012 PACKAGE WEIGHT 0.15gms 0.150[3.810] 0.157[3.987] 0.230[5.842] 0.244[6.197] PART # S16.15 STANDARD PKG. 9 SZ16.15 LEAD FREE PKG. 16 0.386[9.804] 0.393[9.982] 0.010[0.254] 0.016[0.406] SEATING PLANE X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0°~8° 0.0138[0.350] 0.0192[0.487] 0.004[0.102] 0.0098[0.249] 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 51-85068-*B Document #: 38-07265 Rev. *D Page 6 of 8 PRELIMINARY CY23S08 Package Drawings and Dimensions (continued) 16-Lead Thin Shrunk Small Outline Package (4.40 MM Body) Z16 PIN 1 ID 1 6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177] 16 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0°-8° 0.076[0.003] 0.85[0.033] 0.95[0.037] 4.90[0.193] 5.10[0.200] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 51-85091-*A Spread Aware is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are trademarks of their respective holders. Document #: 38-07265 Rev. *D Page 7 of 8 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY CY23S08 Document History Page Document Title: CY23S08 3.3V Zero Delay Buffer Document Number: 38-07265 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 110530 12/02/01 SZV Change from Spec number: 38-01107 to 38-07265 *A 122863 12/20/02 RBI Added power-up requirements to operating conditions information. *B 130951 11/26/03 RGL Corrected the Switching Characteristics parameters to reflect the W152 device and new characterization. *C 204201 See ECN RGL Corrected the Block Diagram *D 231100 See ECN RGL Fixed Typo in table 2. Document #: 38-07265 Rev. *D Page 8 of 8