FAN7383
Half-Bridge Gate-Drive IC
Features
Description
Floating Channel Designed for Bootstrap Operation to
The FAN7383 is a half-bridge gate-drive IC with
shutdown and programmable dead-time control
functions for driving MOSFETs and IGBTs that operate
up to +600V.
+600V.
Typically 350mA/650mA Sourcing/Sinking Current
Driving Capability for Both Channels
Extended Allowable Negative VS Swing to -9.8V for
Signal Propagation at VDD=VBS=15V
High-Side Output in Phase of IN Signal
Built-in UVLO Functions for Both Channels
Built-in Common-Mode dv/dt Noise Canceling Circuit
Typically Internal 330ns Minimum Dead-Time
Programmable Turn-On Delay Time Control
(Dead-Time)
Fairchild’s high voltage process and common-mode
noise canceling technique give stable operation of highside drivers under high-dv/dt noise circumstances.
An advanced level-shift circuit allows high-side gate
driver operation up to VS= -9.8V (typical) for VBS=15V.
The UVLO circuits for both channels prevent malfunction
when VDD and VBS are lower than the specified
threshold voltage.
Output drivers typically source/sink 350mA/650mA,
respectively, which is suitable for all kinds of half and full
bridge inverter.
Applications
SMPS
Motor Drive Inverter
14-SOP
Fluorescent Lamp Ballast
HID Ballast
1
Ordering Information
Part Number
FAN7383M
Package
Pb-Free
14-SOP
Yes
Operating Temperature Range Packing Method
(1)
FAN7383MX(1)
-40°C ~ 125°C
Tube
Tape & Reel
Note:
1. These devices passed wave soldering test by JESD22A-111.
© 2006 Fairchild Semiconductor Corporation
FAN7383 Rev. 1.0.3
www.fairchildsemi.com
FAN7383 Half-Bridge Gate-Drive IC
February 2007
FAN7383 Half-Bridge Gate-Drive IC
Typical Application Circuit
RBOOT
VDC
DBOOT
VDD
PWM
PWM IC
Shutdown
Control
1
IN
2
VB
14
SD
HO1
13
3
DT
HO2
12
4
VDD
VS
11
5
LO1
NC
10
6
LO2
NC
9
7
GND
NC
8
RHON
RHOFF
CBOOT
RDT
RLOFF
RLON
FAN7383 Rev.01
Figure 1. Application Circuit for Half-Bridge Switching Power Supply
VDC
VCC
VDD
PHA
VDD
VB
VB
HO1
HO1
HO2
HO2
IN
VS
VS
PHB
Forward
IN
M
SD
SD
DC Motor
Controller
SD
FAN7383
FAN7383
LO1
DT
Reverse
LO1
DT
LO2
GND
LO2
GND
FAN7383 Rev.01
Figure 2. Application Circuit for Full-Bridge DC Motor Driver
© 2006 Fairchild Semiconductor Corporation
FAN7383 Rev. 1.0.3
www.fairchildsemi.com
2
14
VB
13
HO1
12
HO2
11
VS
4
VDD
5
LO1
6
LO2
7
GND
UVLO
1
SD
2
SHOOT THOUGH
PREVENTION
DT
3
DEAD-TIME
{ DTMIN=330nsec }
R
DRIVER
PULSE
GENERATOR
SCHMITT
TRIGGER INPUT
IN
NOISE
CANCELLER
R
S
Q
HS(ON/OFF)
UVLO
DELAY
DRIVER
LS(ON/OFF)
FAN7383 Rev:01
Figure 3. Functional Block Diagram of FAN7383
© 2006 Fairchild Semiconductor Corporation
FAN7383 Rev. 1.0.3
www.fairchildsemi.com
3
FAN7383 Half-Bridge Gate-Drive IC
Internal Block Diagram
FAN7383 Half-Bridge Gate-Drive IC
Pin Configuration
1
14
VB
SD
2
13
HO1
DT
3
12
HO2
VDD
4
11
VS
LO1
5
10
NC
LO2
6
9
NC
GND
7
8
NC
FAN7383
IN
FAN7383 Rev:00
Figure 4. Pin Configuration (Top View)
Pin Definitions
Pin #
Name
Description
1
IN
2
SD
Logic Input for Shutdown (Active Low)
3
DT
Programmable Dead-Time Control with External Resistor
4
VDD
Low-Side Supply Voltage
5
LO1
Low-Side Driver Source Output
6
LO2
Low-Side Driver Sink Output
7
GND
Ground
8
N.C.
Not connected
9
N.C.
Not connected
10
N.C.
11
VS
12
HO2
High-Side Driver Sink Output
13
HO1
High-Side Driver Source Output
14
VB
Logic Input for Gate Driver
Not connected
High-Side Floating Supply Return
High-Side Floating Supply
© 2006 Fairchild Semiconductor Corporation
FAN7383 Rev. 1.0.3
www.fairchildsemi.com
4
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In
addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only. TA = 25°C unless otherwise specified.
Symbol
Parameter
VS
High-side offset voltage
VB
High-side floating supply voltage
Min.
Max.
Unit
VB-25
VB+0.3
V
-0.3
625
V
VHO
High-side floating output voltage HO1, HO2
VS-0.3
VB+0.3
V
VDD
Low-side and logic fixed supply voltage
-0.3
25
V
VLO
Low-side output voltage LO1, LO2
-0.3
VDD+0.3
V
VIN
Logic input voltage (IN)
-0.3
VDD+0.3
V
VSD
Shutdown logic input voltage
-0.3
VDD+0.3
V
VDT
Dead-time control voltage
-0.3
5.0
V
GND
Logic ground
VDD-25
VDD+0.3
V
50
V/ns
dVS/dt
PD(2)(3)(4)
Allowable offset voltage slew rate
Power dissipation
1.0
W
θJA
Thermal resistance, junction-to-ambient
110
°C/W
TJ
Junction temperature
150
°C
TSTG
Storage temperature
150
°C
Notes:
2. When mounted on 76.2 x 114.3 x 1.6mm PCB. (FR-4 glass epoxy material).
3. Please refer to:
JESD51-2: Integral circuits thermal test method environmental conditions - Natural convection
JESD51-3: Low effective thermal conductivity test board for leaded surface mount packages
4. Do not exceed PD under any circumstances.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Condition
Min.
Max.
Unit
VB
High-side floating supply voltage
VS+15
VS+20
V
VS
High-side floating supply offset voltage
6-VDD
600
V
VDD
Low-side supply voltage
15
20
V
VHO
High-side (HO) output voltage
VS
VB
V
VLO
Low-side (LO) output voltage
GND
VDD
V
VIN
Logic input voltage (IN)
GND
VDD
V
TA
Ambient temperature
-40
125
°C
© 2006 Fairchild Semiconductor Corporation
FAN7383 Rev. 1.0.3
www.fairchildsemi.com
5
FAN7383 Half-Bridge Gate-Drive IC
Absolute Maximum Ratings
VBIAS (VDD, VBS) = 15.0V, RDT = GND, TA = 25°C, unless otherwise specified. The VIN and IIN parameters are
referenced to GND. The VO and IO parameters are referenced to VS and GND and are applicable to the respective
outputs HO and LO.
Symbol
Parameter
Condition
Min. Typ. Max. Unit
SUPPLY CURRENT SECTION
IQBS
Quiescent VBS supply current
VIN=0V or 5V
35
90
IQDD
Quiescent VDD supply current
VIN=0V or 5V, RDT=0Ω
650
900
ISD(5)
VDD supply current at shutdown mode
SD=GND
650
900
IPBS
Operating VBS supply current
fIN=20kHz,rms value
400
700
IPDD
Operating VDD supply current
fIN=20kHz,rms value, RDT=0Ω
950
1200
ILK
Offset supply leakage current
VB=VS=600V
μA
10
POWER SUPPLY SECTION
VDDUV+
VBSUV+
VDD and VBS supply under-voltage
positive going threshold
10.7
11.6
12.5
VDDUVVBSUV-
VDD and VBS supply under-voltage
negative going threshold
10.0
10.8
11.6
V
VDDUVH
VBSUVH
VDD and VBS supply under-voltage
lockout hysteresis
1.0
V
0.6
V
0.8
GATE DRIVER OUTPUT SECTION
VOH
High-level output voltage, VBIAS-VO
IO=20mA
VOL
Low-level output voltage, VO
IO+
Output high short-circuit pulse current
VO=0V, VIN=5V with PW<10µs
250
350
mA
IO-
Output low short-circuit pulsed current
VO=15V, VIN=0V with PW<10µs
500
650
mA
VS
Allowable negative VS pin voltage for IN
signal propagation to HO
-9.8
-7.0
V
LOGIC INPUT SECTION (INPUT AND SHUTDOWN)
VIH
Logic "1" input voltage
VIL
Logic "0" input voltage
IIN+
Logic "1" input bias current
VIN=5V
VIN=0V
IIN-
Logic "0" input bias current
SD+
Shutdown "1" input voltage
SD-
Shutdown "0" input voltage
RPD
Input pull-down resistance
2.9
V
50
2.9
1.2
V
100
μA
2.0
μA
1.2
V
V
100
KΩ
Note:
5.This parameter guaranteed by design.
© 2006 Fairchild Semiconductor Corporation
FAN7383 Rev. 1.0.3
www.fairchildsemi.com
6
FAN7383 Half-Bridge Gate-Drive IC
Electrical Characteristics
VBIAS (VDD, VBS) = 15.0V, VS = GND, CL=1000pF, RDT = GND, and TA = 25°C, unless otherwise specified.
Symbol
tON
tOFF
Parameter
Turn-on propagation delay
Min. Typ. Max. Unit
VS=0V
500
670
170
250
Turn-on rise time
50
100
tF
Turn-off fall time
30
80
Shutdown propagation delay
100
180
tSD
DT1,
DT2
Dead-time LO OFF to HO ON and HO
OFF to LO ON
DMT
Dead-time matching
VS=0V or 600V
(5)
tR
(5)
Turn-off propagation delay
Conditions
ns
RDT=0Ω
250
330
420
ns
RDT=200KΩ
1.20
1.68
2.30
µs
RDT=0Ω
0
60
RDT=200KΩ
0
150
ns
Note:
5.These parameters guaranteed by design.
© 2006 Fairchild Semiconductor Corporation
FAN7383 Rev. 1.0.3
www.fairchildsemi.com
7
FAN7383 Half-Bridge Gate-Drive IC
Dynamic Electrical Characteristics
11.6
11.4
11.8
VDDUV- ,VBSUV- [V]
VDDUV+ ,VBSUV+ [V]
12.0
11.6
11.4
11.2
11.2
11.0
10.8
10.6
10.4
11.0
10.2
10.8
-40
-20
0
20
40
60
80
100
10.0
-40
120
-20
0
1000
100
800
80
600
40
200
20
0
20
40
60
60
80
100
120
60
400
-20
40
Figure 6. VDD/VBS UVLO (-) vs. Temperature
IQBS [μA]
IQDD [μA]
Figure 5. VDD/VBS UVLO (+) vs. Temperature
-40
20
Temperature [°C]
Temperature [°C]
80
100
0
-40
120
-20
0
Temperature [°C]
20
40
60
80
100
120
Temperature [°C]
Figure 7. VDD Quiescent Current vs. Temperature
Figure 8. VBS Quiescent Current vs. Temperature
1600
800
1400
IPBS [μA]
IPDD [μA]
600
1200
1000
400
800
200
600
400
-40
-20
0
20
40
60
80
100
0
-40
120
Temperature [°C]
0
20
40
60
80
100
120
Temperature [°C]
Figure 9. VDD Operating Current vs. Temperature
Figure 10. VBS Operating Current vs. Temperature
© 2006 Fairchild Semiconductor Corporation
FAN7383 Rev. 1.0.3
-20
www.fairchildsemi.com
8
FAN7383 Half-Bridge Gate-Drive IC
Typical Characteristics
3.0
100
2.5
2.0
VIH [V]
IIN+ [μA]
80
60
1.5
40
1.0
20
0
-40
0.5
-20
0
20
40
60
80
100
0.0
-40
120
-20
0
Figure 11. Logic Input Current vs. Temperature
2.5
2.5
SD+ BAR [V]
3.0
VIL [V]
2.0
1.5
0.5
0.5
20
40
60
80
100
0.0
-40
120
-20
0
Temperature [°C]
100
120
20
40
60
80
100
120
Temperature [°C]
Figure 14. SD Positive Threshold vs. Temperature
Figure 13. Logic Input Low Voltage vs. Temperature
100
3.0
2.5
80
2.0
tR [nsec]
SD- BAR [V]
80
1.5
1.0
0
60
2.0
1.0
-20
40
Figure 12. Logic Input High Voltage vs. Temperature
3.0
0.0
-40
20
Temperature [°C]
Temperature [°C]
1.5
60
40
1.0
20
0.5
0.0
-40
-20
0
20
40
60
80
100
0
-40
120
Temperature [°C]
0
20
40
60
80
100
120
Temperature [°C]
Figure 15. SD Negative Threshold vs. Temperature
Figure 16. Rising Time vs. Temperature
© 2006 Fairchild Semiconductor Corporation
FAN7383 Rev. 1.0.3
-20
www.fairchildsemi.com
9
FAN7383 Half-Bridge Gate-Drive IC
Typical Characteristics (Continued)
700
80
600
tON [nsec]
tF [nsec]
60
40
20
500
400
300
0
-40
-20
0
20
40
60
80
100
200
-40
120
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 17. Falling Time vs. Temperature
Figure 18. Turn-on Delay Time vs. Temperature
300
400
DT1, RDT= 0Ω [nsec]
tOFF [nsec]
250
200
150
100
360
320
280
50
0
-40
-20
0
20
40
60
80
100
240
-40
120
-20
0
20
2.0
2.2
1.6
Deadtime [μS]
DT1, RDT= 200kΩ [nsec]
2.4
2.0
1.8
1.6
80
100
120
1.2
0.8
0.4
1.4
-20
0
20
40
60
80
100
0.0
0
120
20
40
60
80
100
120
140
160
180
200
RDT [kohm]
Temperature [°C]
Figure 21. Dead Time (RDT=200kΩ) vs. Temperature
Figure 22. RDT vs. Dead Time
© 2006 Fairchild Semiconductor Corporation
FAN7383 Rev. 1.0.3
60
Figure 20. Dead-Time (RDT=0kΩ) vs. Temperature
Figure 19. Turn-off Falling Time vs. Temperature
1.2
-40
40
Temperature [°C]
Temperature [°C]
www.fairchildsemi.com
10
FAN7383 Half-Bridge Gate-Drive IC
Typical Characteristics (Continued)
FAN7383 Half-Bridge Gate-Drive IC
Typical Characteristics (Continued)
-6
VS [V]
-8
-10
-12
-14
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Figure 23. Allowable Negative VS Voltage for Signal
Propagation to High Side vs. Temperature
© 2006 Fairchild Semiconductor Corporation
FAN7383 Rev. 1.0.3
www.fairchildsemi.com
11
FAN7383 Half-Bridge Gate-Drive IC
Switching Time Definitions
+15V
10μF
FAN7383
100nF
SD
LO1, 2
1
IN
2
+15V
10μF 100nF
VB
14
SD
HO1
13
3
DT
HO2
12
4
VDD
VS
11
5
LO1
NC
10
6
LO2
NC
9
7
GND
NC
8
HO1, 2
1nF
1nF
FAN7383 Rev:00
Figure 24. Switching Time Test Circuit
IN
HO1, 2
LO1, 2
SD
DT1
Shutdown
DT2
DT2
DT1
Shutdown
DT1
FAN7383 Rev:00
Figure 25. Input / Output Waveforms
IN
50%
50%
tOFF
90%
tON
LO1, 2
10%
90%
HO1, 2
tON
tOFF
10%
FAN7383 Rev:00
Figure 26. Switching Time Waveform Definitions
© 2006 Fairchild Semiconductor Corporation
FAN7383 Rev. 1.0.3
www.fairchildsemi.com
12
FAN7383 Half-Bridge Gate-Drive IC
50%
SD
90%
HO or LO
tSD
FAN7383 Rev:00
Figure 27. Shutdown Waveform Definition
90%
HO
10%
DT1
DT2
90%
LO
MDT= DT1-DT2
10%
FAN7383 Rev:00
Figure 28. Dead-Time Waveform Definition
© 2006 Fairchild Semiconductor Corporation
FAN7383 Rev. 1.0.3
www.fairchildsemi.com
13
1. Normal Operating Consideration
3. Layout Consideration
The FAN7383 is a single PWM input half-bridge gatedrive IC with programmable dead-time and shutdown
function.
For optimum performance of high- and low-side gate
drivers, cannot be achieved without taking due
considerations must be taken during printed circuit board
(PCB) layout.
The dead-time is set with a resistor (RDT) at the DT pin.
The wide dead-time programming range provides the
flexibility to optimize drive signal timing for a selection of
switching devices (MOSFET or IGBT) and applications.
3.1 Supply Capacitors
If the output stages are able to quickly turn on the
switching device with high value of current, the supply
capacitors must be placed as close as possible to the
device pins (VDD and GND for the ground-tied supply, VB
and VS for the floating supply) to minimize parasitic
inductance and resistance.
The turn-on time delay circuitry (Dead-Time)
accommodates resistor values from 0Ω to 200kΩ with a
dead-time proportional to the RDT resistance.
Grounding the DT pin programs the FAN7383 to drive
both outputs with minimum dead time.
3.2 Gate Drive Loop
If the SD pin voltage decrease below 1.2V in normal
operation, the IC enters the shutdown mode.
Current loops behave like an antenna, able to receive
and transmit noise. To reduce the noise coupling/
emission and improve the power switch turn-on and off
performances, gate drive loops must be reduced as
much as possible.
2. Under-Voltage Lockout (UVLO)
The FAN7383 has an under-voltage lockout (UVLO)
protection circuitry for high and low side channels to
prevent malfunction when VDD or VBS is lower than the
specified threshold voltage. The UVLO circuitry monitors
the supply voltage (VDD) and bootstrap capacitor voltage
(VBS) independently.
3.3 Ground Plane
Ground plane must not be placed under or nearby the
high-voltage floating side to minimize noise coupling.
© 2006 Fairchild Semiconductor Corporation
FAN7383 Rev. 1.0.3
www.fairchildsemi.com
14
FAN7383 Half-Bridge Gate-Drive IC
Typical Application Information
FAN7383 Half-Bridge Gate-Drive IC
Package Dimensions
14-SOP
Dimensions are in millimeters unless otherwise noted.
MIN
#8
MAX0.10
MAX0.004
1.80
MAX
0.071
5.72
0.225
8°
3.95 ±0.20
0.156 ±0.008
0~
+0.10
0.20 -0.05
+0.004
0.008 -0.002
6.00 ±0.30
0.236 ±0.012
1.27
0.050
#7
+0.10
0.406 -0.05
+0.004
0.016 -0.002
#14
8.70
MAX
0.343
#1
8.56 ±0.20
0.337 ±0.008
(
0.47
)
0.019
1.55 ±0.10
0.061 ±0.004
0.05
0.002
0.60 ±0.20
0.024 ±0.008
January 2001, Rev. A
Figure 29. 14-Lead Small Outline Package (SOP)
© 2006 Fairchild Semiconductor Corporation
FAN7383 Rev. 1.0.3
www.fairchildsemi.com
15
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APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER
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which, (a) are intended for surgical implant into the body or
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when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
2. A critical component in any component of a life support,
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In Design
This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
design.
Obsolete
Not In Production
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I23
© 2006 Fairchild Semiconductor Corporation
FAN7383 Rev. 1.0.3
www.fairchildsemi.com
16
FAN7383 Half-Bridge Gate-Drive IC
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