CY7C1329 64K x 32 Synchronous-Pipelined Cache RAM Features All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise is 4.2 ns (133-MHz device). • Supports 133-MHz bus for Pentium and PowerPC operations with zero wait states • Fully registered inputs and outputs for pipelined operation The CY7C1329 supports either the interleaved burst sequence used by the Intel Pentium processor or a linear burst sequence used by processors such as the PowerPC. The burst sequence is selected through the MODE pin. Accesses can be initiated by asserting either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC) at clock rise. Address advancement through the burst sequence is controlled by the ADV input. A 2-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. • 64K x 32 common I/O architecture • Single 3.3V power supply • Fast clock-to-output times — 4.2 ns (for 133-MHz device) — 5.5 ns (for 100-MHz device) • User-selectable burst counter supporting Intel® Pentium interleaved or linear burst sequences • Separate processor and controller address strobes Byte Write operations are qualified with the four Byte Write Select (BW[3:0]) inputs. A Global Write Enable (GW) overrides all Byte Write inputs and writes data to all four bytes. All writes are conducted with on-chip synchronous self-timed Write circuitry. • Synchronous self-timed writes • Asynchronous output enable • JEDEC-standard 100-lead TQFP pinout • “ZZ” Sleep Mode option and Stop Clock option Functional Description The CY7C1329 is a 3.3V, 64K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic. Logic Block Diagram MODE (A[1:0]) 2 BURST Q0 CE COUNTER Q1 CLR CLK ADV ADSC ADSP A[15:0] GW Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to provide proper data during depth expansion, OE is masked during the first clock of a Read cycle when emerging from a deselected state. 16 14 ADDRESS CE REGISTER D D BWE BW 3 Q 16 14 64K × 32 Memory Array DQ[31:24] Q BYTEWRITE REGISTERS D DQ[23:16] Q BYTEWRITE REGISTERS BW2 D Q DQ[15:8] BYTEWRITE REGISTERS D Q DQ[7:0] BYTEWRITE REGISTERS BW1 BW0 CE1 CE2 CE3 32 32 D ENABLE Q CE REGISTER CLK D Q ENABLE DELAY REGISTER CLK OUTPUT REGISTERS CLK INPUT REGISTERS CLK OE ZZ SLEEP CONTROL DQ[31:0] Cypress Semiconductor Corporation Document #: 38-05279 Rev. *B • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised March 31, 2004 CY7C1329 Pin Configuration BYTE2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 CY7C1329 NC DQ15 DQ14 VDDQ VSSQ DQ13 DQ12 DQ11 DQ10 VSSQ VDDQ DQ9 DQ8 VSS NC VDD ZZ DQ7 DQ6 VDDQ VSSQ DQ5 DQ4 DQ3 DQ2 VSSQ VDDQ DQ1 DQ0 NC BYTE1 BYTE0 MODE A5 A4 A3 A2 A1 A0 NC NC VSS VDD NC NC A10 A11 A12 A13 A14 A15 NC 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 BYTE3 NC DQ16 DQ17 VDDQ VSSQ DQ18 DQ19 DQ20 DQ21 VSSQ VDDQ DQ22 DQ23 NC VDD NC VSS DQ24 DQ25 VDDQ VSSQ DQ26 DQ27 DQ28 DQ29 VSSQ VDDQ DQ30 DQ31 NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A6 A7 CE1 CE2 BW3 BW2 BW1 BW0 CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A8 A9 100-pin TQFP Selection Guide 7C1329-133 Maximum Access Time 7C1329-100 Unit 4.2 5.5 ns Maximum Operating Current Commercial 325 310 mA Maximum CMOS Standby Current Commercial 5 5 mA Document #: 38-05279 Rev. *B Page 2 of 15 CY7C1329 Pin Definitions Pin Number Name I/O Description 49–44, 81,82, A[15:0] 99, 100, 32–37 InputSynchronous Address Inputs used to select one of the 64K address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the 2-bit counter. 96–93 BW[3:0] InputSynchronous Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes to the SRAM. Sampled on the rising edge of CLK. 88 GW InputSynchronous Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global Write is conducted (ALL bytes are written, regardless of the values on BW[3:0] and BWE). 87 BWE InputSynchronous Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a Byte Write. 89 CLK Input-Clock Clock input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. 98 CE1 InputSynchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. 97 CE2 InputSynchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. 92 CE3 InputSynchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. 86 OE InputOutput Enable, asynchronous input, active LOW. Controls the direction of the Asynchronous I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the first clock of a Read cycle when emerging from a deselected state. 83 ADV InputSynchronous Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically increments the address in a burst cycle. 84 ADSP InputSynchronous Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A[15:0] is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. 85 ADSC InputSynchronous Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A[15:0] is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. 64 ZZ InputZZ “sleep” Input. This active HIGH input places the device in a non-time-critical Asynchronous “sleep” condition with data integrity preserved. 29, 28, 25–22, DQ[31:0] 19, 18,13,12, 9–6, 3, 2, 79, 78, 75–72, 69, 68, 63, 62 59–56, 53, 52 I/OSynchronous 15, 41, 65, 91 VDD Power Supply Power supply inputs to the core of the device. Should be connected to 3.3V power supply. Ground Ground for the core of the device. Should be connected to ground of the system. I/O Power Supply Power supply for the I/O circuitry. Should be connected to a 3.3V power supply. I/O Ground Ground for the I/O circuitry. Should be connected to ground of the system. 17, 40, 67, 90 VSS 4, 11, 20, 27, VDDQ 54, 61, 70, 77 5, 10, 21, 26, VSSQ 55, 60, 71, 76 31 Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[15:0] during the previous clock rise of the Read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ[31:0] are placed in a three-state condition. MODE 1, 14, 16, 30, NC 38, 39, 42, 43, 50, 51, 66, 80 Document #: 38-05279 Rev. *B InputStatic – Selects burst order. When tied to GND selects linear burst sequence. When tied to VDDQ or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. No Connects. Page 3 of 15 CY7C1329 Introduction Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 4.2 ns (133-MHz device). The CY7C1329 supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486 processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte Write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BW[3:0]) inputs. A Global Write Enable (GW) overrides all Byte Write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed Write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) CE1, CE2, CE3 are all asserted active, and (3) the Write signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs (A[15:0]) is stored into the address advancement logic and the Address Register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the Output Registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within 4.2 ns (133-MHz device) if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always three-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single Read cycles are supported. Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output will three-state immediately. Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1, CE2, CE3 are all asserted active. The address presented to A[15:0] is loaded into the address register and the address advancement logic while being delivered to the RAM core. The Document #: 38-05279 Rev. *B Write signals (GW, BWE, and BW0–BW3) and ADV inputs are ignored during this first cycle. ADSP triggered Write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQ[31:0] inputs is written into the corresponding address location in the RAM core. If GW is HIGH, then the Write operation is controlled by BWE and BW[3:0] signals. The CY7C1329 provides Byte Write capability that is described in the Write Cycle Description table. Asserting the Byte Write Enable input (BWE) with the selected Byte Write (BW[3:0]) input will selectively write to only the desired bytes. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because the CY7C1329 is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ[31:0] inputs. Doing so will three-state the output drivers. As a safety precaution, DQ[31:0] are automatically three-stated whenever a Write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC Write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) CE1, CE2, CE3 are all asserted active, and (4) the appropriate combination of the Write inputs (GW, BWE, and BW[3:0]) are asserted active to conduct a Write to the desired byte(s). ADSC triggered Write accesses require a single clock cycle to complete. The address presented to A[15:0] is loaded into the address register and the address advancement logic while being delivered to the RAM core. The ADV input is ignored during this cycle. If a global Write is conducted, the data presented to the DQ[31:0] is written into the corresponding address location in the RAM core. If a Byte Write is conducted, only the selected bytes are written. Bytes not selected during a Byte Write operation will remain unaltered. A Synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because the CY7C1329 is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ[31:0] inputs. Doing so will three-state the output drivers. As a safety precaution, DQ[31:0] are automatically three-stated whenever a Write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1329 provides a two-bit wraparound counter, fed by A[1:0], that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both Read and Write burst operations are supported. Page 4 of 15 CY7C1329 Sleep Mode Interleaved Burst Sequence First Address Second Address Third Address Fourth Address A[1:0] A[1:0] A[1:0] A[1:0] 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Linear Burst Sequence First Address Second Address Third Address Fourth Address A[1:0] A[1:0] A[1:0] A[1:0] 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 ZZ Mode Electrical Characteristics Parameter Description Test Conditions IDDZZ Snooze mode standby current ZZ > VDD − 0.2V tZZS Device operation to ZZ ZZ > VDD − 0.2V tZZREC ZZ recovery time Min. ZZ < 0.2V Max. Unit 3 mA 2tCYC ns 2tCYC ns Cycle Descriptions [1,2,3] ZZ CE3 CE2 CE1 ADSP ADSC ADV OE Unselected Next Cycle None Add. Used L X X 1 X 0 X X Hi-Z DQ X Write Unselected None L 1 X 0 0 X X X Hi-Z X Unselected None L X 0 0 0 X X X Hi-Z X Unselected None L 1 X 0 1 0 X X Hi-Z X Unselected None L X 0 0 1 0 X X Hi-Z X Begin Read External L 0 1 0 0 X X X Hi-Z X Begin Read External L 0 1 0 1 0 X X Hi-Z Read Continue Read Next L X X X 1 1 0 1 Hi-Z Read Continue Read Next L X X X 1 1 0 0 DQ Read Continue Read Next L X X 1 X 1 0 1 Hi-Z Read Continue Read Next L X X 1 X 1 0 0 DQ Read Suspend Read Current L X X X 1 1 1 1 Hi-Z Read Suspend Read Current L X X X 1 1 1 0 DQ Read Suspend Read Current L X X 1 X 1 1 1 Hi-Z Read Suspend Read Current L X X 1 X 1 1 0 DQ Read Begin Write Current L X X X 1 1 1 X Hi-Z Write Notes: 1. X = “Don't Care,” 1 = HIGH, 0 = LOW. 2. Write is defined by BWE, BW[3:0], and GW. See Write Cycle Descriptions table. 3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. Document #: 38-05279 Rev. *B Page 5 of 15 CY7C1329 Cycle Descriptions (continued)[1,2,3] Next Cycle Add. Used ZZ CE3 CE2 CE1 ADSP ADSC ADV OE DQ Write Begin Write Current L X X 1 X 1 1 X Hi-Z Write Begin Write External L 0 1 0 1 0 X X Hi-Z Write Continue Write Next L X X X 1 1 0 X Hi-Z Write Continue Write Next L X X 1 X 1 0 X Hi-Z Write Suspend Write Current L X X X 1 1 1 X Hi-Z Write Suspend Write Current L X X 1 X 1 1 X Hi-Z Write ZZ “sleep” None H X X X X X X X Hi-Z X Write Cycle Descriptions[4,5,6] GW BWE BW3 BW2 BW1 BW0 Read Function 1 1 X X X X Read 1 0 1 1 1 1 Write Byte 0 – DQ[7:0] 1 0 1 1 1 0 Write Byte 1 – DQ[15:8] 1 0 1 1 0 1 Write Bytes 1, 0 1 0 1 1 0 0 Write Byte 2 – DQ[23:16] 1 0 11 0 1 1 Write Bytes 2, 0 1 0 1 0 1 0 Write Bytes 2, 1 1 0 1 0 0 1 Write Bytes 2, 1, 0 1 0 1 0 0 0 Write Byte 3 - DQ[31:24] 1 0 0 1 1 1 Write Bytes 3, 0 1 0 0 1 1 0 Write Bytes 3, 1 1 0 0 1 0 1 Write Bytes 3, 1, 0 1 0 0 1 0 0 Write Bytes 3, 2 1 0 0 0 1 1 Write Bytes 3, 2, 0 1 0 0 0 1 0 Write Bytes 3, 2, 1 1 0 0 0 0 1 Write All Bytes 1 0 0 0 0 0 Write All Bytes 0 X X X X X Document #: 38-05279 Rev. *B Page 6 of 15 CY7C1329 Maximum Ratings Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................... −65°C to +150°C Ambient Temperature with Power Applied.................................................. −55°C to +125°C Supply Voltage on VDD Relative to GND.........−0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[7] .....................................−0.5V to VDDQ + 0.5V Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... >200 mA Operating Range Range Commercial Industrial Ambient Temperature[8] 0°C to +70°C VDD VDDQ 3.3V 3.3V −5%/+10% −5%/+10% -40°C to +85°C DC Input Voltage[7] ..................................−0.5V to VDDQ + 0.5V Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Max. Unit VDD Power Supply Voltage 3.3V −5%/+10% 3.135 3.6 V VDDQ I/O Supply Voltage 3.3V −5%/+10% 3.135 3.6 V VOH Output HIGH Voltage VDD = Min., IOH = −4.0 mA VOL Output LOW Voltage VDD = Min., IOL = 8.0 mA VIH Input HIGH Voltage 2.4 Voltage[7] VIL Input LOW IX Input Load Current Except ZZ and MODE GND ≤ VI ≤ VDDQ Input Current of MODE Input = VSS V 2.0 VDDQ + 0.3V V –0.3 0.8 V −5 5 µA 5 Input = VSS Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled IDD VDD Operating Supply Current VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC Automatic CS Power-down Current—TTL Inputs Max. VDD, Device Deselected, VIN ≥ VIH or VIN ≤ VIL f = fMAX = 1/tCYC ISB1 µA µA –5 30 µA 5 µA 7.5-ns cycle, 133 MHz 325 mA 10-ns cycle, 100 MHz 260 mA Input = VDDQ IOZ µA –30 Input = VDDQ Input Current of ZZ V 0.4 −5 7.5-ns cycle, 133 MHz 60 mA 10-ns cycle, 100 MHz 50 mA ISB2 Automatic CS Max. VDD, Device Deselected, Power-down VIN ≤ 0.3V or VIN > VDDQ – 0.3V, Current—CMOS Inputs f = 0 All speeds 5 mA ISB3 Automatic CS Max. VDD, Device Deselected, or Power-down VIN ≤ 0.3V or VIN > VDDQ – 0.3V Current—CMOS Inputs f = fMAX = 1/tCYC 7.5-ns cycle, 133 MHz 40 mA 10-ns cycle, 100 MHz 30 mA 25 mA ISB4 Automatic CS Power-down Current—TTL Inputs Max. VDD, Device Deselected, VIN ≥ VIH or VIN ≤ VIL, f = 0 Notes: 4. X = “Don't Care,” 1 = Logic HIGH, 0 = Logic LOW. 5. The SRAM always initiates a Read cycle when ADSP asserted, regardless of the state of GW, BWE, or BW[3:0]. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to three-state. OE is a “don't care” for the remainder of the Write cycle. 6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle DQ = High-Z when OE is inactive or when the device is deselected, and DQ = data when OE is active. 7. Minimum voltage equals –2.0V for pulse durations of less than 20 ns. 8. TA is the case temperature. Document #: 38-05279 Rev. *B Page 7 of 15 CY7C1329 Capacitance[9] Parameter Description Test Conditions CIN Input Capacitance CCLK Clock Input Capacitance CI/O Input/Output Capacitance TA = 25°C, f = 1 MHz, VDD = 3.3V, VDDQ = 3.3V Max. Unit 4 pF 4 pF 4 pF AC Test Loads and Waveforms R = 317Ω 3.3V OUTPUT ALL INPUT PULSES OUTPUT Z0 = 50Ω RL = 50Ω 3.3V 5 pF INCLUDING JIG AND SCOPE VL = 1.5V (a) R = 351Ω GND 10% [10] 90% 10% 90% < 3.3 ns < 3.3 ns (b) (c) Switching Characteristics Over the Operating Range[11,12,13] -133 Parameter Description Min. -100 Max. Min. Max. Unit tCYC Clock Cycle Time 7.5 10 ns tCH Clock HIGH 1.9 3.2 ns tCL Clock LOW 1.9 3.2 ns tAS Address Set-up Before CLK Rise 1.5 2.5 ns tAH Address Hold After CLK Rise 0.5 tCO Data Output Valid After CLK Rise tDOH Data Output Hold After CLK Rise 1.5 2.0 ns tADS ADSP, ADSC Set-up Before CLK Rise 1.5 2.5 ns tADH ADSP, ADSC Hold After CLK Rise 0.5 0.5 ns tWES BWE, GW, BW[3:0] Set-up Before CLK Rise 1.5 2.5 ns tWEH BWE, GW, BW[3:0] Hold After CLK Rise 0.5 0.5 ns tADVS ADV Set-up Before CLK Rise 1.5 2.5 ns tADVH ADV Hold After CLK Rise 0.5 0.5 ns tDS Data Input Set-up Before CLK Rise 1.5 2.5 ns tDH Data Input Hold After CLK Rise 0.5 0.5 ns tCES Chip Select Set-up 1.5 2.5 ns tCEH Chip Select Hold After CLK Rise 0.5 tCHZ Clock to High-Z[12] 1.5 tCLZ [12] Clock to Low-Z tEOHZ OE HIGH to Output High-Z[12, 13] 0.5 4.2 0.5 3.5 0 [12, 13] tEOLZ OE LOW to Output Low-Z tEOV OE LOW to Output Valid[12] ns 5.0 1.5 ns 5 0 3.5 0 ns ns 5.5 0 4.2 ns ns ns 5.0 ns Notes: 9. Tested initially and after any design or process changes that may affect these parameters. 10. Input waveform should have a slew rate of 1V/ns. 11. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and load capacitance. Shown in (a) and (b) of AC Test Loads. 12. tCHZ, tCLZ, tEOV, tEOLZ, and tEOHZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 13. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ. Document #: 38-05279 Rev. *B Page 8 of 15 CY7C1329 Switching Waveforms Write Cycle Timing[14, 15] Single Write Burst Write Pipelined Write tCH tCYC Unselected CLK tADH tADS tCL ADSP ignored with CE1 inactive ADSP tADH tADS ADSC initiated Write ADSC tADVH tADVS ADV tAS ADD ADV Must Be Inactive for ADSP Write WD1 WD3 WD2 tAH GW tWS tWH WE tCES tWH tWS tCEH CE1 masks ADSP CE1 tCES tCEH Unselected with CE2 CE2 CE3 tCES tCEH OE tDH tDS Data- High-Z In 1a 1a 2a = UNDEFINED 2b 2c 2d 3a High-Z = DON’T CARE Notes: 14. WE is the combination of BWE, BW[3:0] and GW to define a Write cycle (see Write Cycle Descriptions table). 15. WDx stands for Write Data to Address X. Document #: 38-05279 Rev. *B Page 9 of 15 CY7C1329 Switching Waveforms (continued) Read Cycle Timing[14, 16] Burst Read Single Read tCYC Unselected tCH Pipelined Read CLK tADH tADS tCL ADSP ignored with CE1 inactive ADSP tADS ADSC initiated Read ADSC tADVS tADH Suspend Burst ADV tADVH tAS ADD RD1 RD3 RD2 tAH GW tWS tWS tWH WE tCES tCEH tWH CE1 masks ADSP CE1 Unselected with CE2 CE2 tCES tCEH CE3 tCES OE tDOE tCEH tOEHZ tDOH DataOut tCO 1a 1a 2a 2b 2c 2c 2d 3a tCLZ = DON’T CARE = UNDEFINED tCHZ Note: 16. RDx stands for Read Data from Address X. Document #: 38-05279 Rev. *B Page 10 of 15 CY7C1329 Switching Waveforms (continued) Read/Write Cycle Timing[14,15,16, 17] Single Read tCYC Single Write Unselected Burst Read tCH Pipelined Read CLK tADH tADS tCL ADSP ignored with CE1 inactive ADSP tADS ADSC tADVS tADH ADV tAS ADD tADVH RD1 WD2 RD3 tAH GW tWS tWS tWH WE tCES tCEH tWH CE1 masks ADSP CE1 CE2 tCES tCEH CE3 tCES OE DataIn/Out tCEH tDOE tOEHZ tOELZ tCO See Note 17 1a 1a Out tDS tDH 2a In 2a Out = DON’T CARE = UNDEFINED 3a Out tDOH 3b Out 3c Out 3d Out TCHZ Note: 17. Data bus is driven by SRAM, but data is not guaranteed. Document #: 38-05279 Rev. *B Page 11 of 15 CY7C1329 Switching Waveforms (continued) Pipeline Timing[18,19] tCH tCYC tCL CLK tAS ADD RD1 tADS RD2 RD3 WD1 RD4 WD2 WD3 WD4 tADH ADSC initiated Reads ADSC ADSP initiated Reads ADSP ADV tCEH tCES CE1 CE tWEH tWES WE ADSP ignored with CE1 HIGH OE tCLZ Data In/Out 1a Out 2a Out 3a Out 4a Out 1a In 2a In tCO Back to Back Reads = DON’T CARE tDOH 3a In 4a D(C) In tCHZ = UNDEFINED Notes: 18. Device originally deselected. 19. CE is the combination of CE2 and CE3. All chip selects need to be active in order to select the device. Document #: 38-05279 Rev. *B Page 12 of 15 CY7C1329 Switching Waveforms (continued) ZZ Mode Timing[20, 21] CLK ADSP HIGH ADSC CE1 LOW CE2 HIGH CE3 ZZ tZZS IDD IDD(active) tZZREC IDDZZ I/Os Three-state Ordering Information Speed (MHz) Ordering Code Package Name Package Type 133 CY7C1329-133AC A101 100-lead Thin Quad Flat Pack 100 CY7C1329-100AC A101 100-lead Thin Quad Flat Pack CY7C1329-100AI A101 100-lead Thin Quad Flat Pack Operating Range Commercial Industrial Notes: 20. Device must be deselected when entering ZZ mode. See Cycle Description table for all possible signal conditions to deselect the device. 21. I/Os are in three-state when exiting ZZ sleep mode. Document #: 38-05279 Rev. *B Page 13 of 15 CY7C1329 Package Diagram 100-lead Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 51-85050-*A i486 is a trademark, and Intel and Pentium are registered trademarks, of Intel Corporation. PowerPC is a registered trademark of IBM Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05279 Rev. *B Page 14 of 15 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1329 Document History Page Document Title: CY7C1329 64K x 32 Synchronous-Pipelined Cache RAM Document Number:38-05279 REV. ECN NO Issue Date Orig. of Change ** 114388 03/25/02 DSG Description of changes Changed from Spec number: 38-00561 to 38-05279 *A 114499 04/11/02 GLC Changed to 1.5 set-up *B 212291 See ECN VBL Updated ordering info: added -100AI Added Industrial to Operating Range section, delete -75 from AC characteristics table Document #: 38-05279 Rev. *B Page 15 of 15