FAN73833
Half-Bridge Gate-Drive IC
Features
Description
Floating Channel for Bootstrap Operation to +600V
The FAN73833 is a half-bridge gate-drive IC for driving
MOSFETs and IGBTs, operating up to +600V.
Typically 350mA/650mA Sourcing/Sinking Current
Driving Capability for Both Channels
Extended Allowable Negative VS Swing to -9.8V for
Signal Propagation at VDD=VBS=15V
3.3V and 5V Input Logic Compatible
Fairchild’s high-voltage process and common-mode
noise canceling technique provide stable operation of
high-side driver under high-dv/dt noise circumstances.
An advanced level-shift circuit allows high-side gate
driver operation up to VS=-9.8V (typical) for VBS=15V.
Outputs in Phase with Input Signals
Built-in UVLO Functions for Both Channels
Built-in Shoot-Through Prevention Circuit
Built-in Common-Mode dv/dt Noise Canceling Circuit
Internal Dead-Time: 400ns Typical
The UVLO circuits for both channels prevent malfunction
when VDD and VBS are lower than the specified threshold voltage.
Output drivers typically source/sink 350mA/650mA,
respectively, which is suitable for all kinds of half- and
full-bridge inverters.
Applications
SMPS
Motor Drive Inverter
8-SOP
Fluorescent Lamp Ballast
HID Ballast
Ordering Information
Part Number
FAN73833M
FAN73833MX
Package
Operating
Temperature Range
8-SOP
-40°C to +125°C
Eco Status
RoHS
Packing Method
Tube
Tape & Reel
For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
© 2008 Fairchild Semiconductor Corporation
FAN73833 • Rev. 1.0.0
www.fairchildsemi.com
FAN73833 — Half-Bridge Gate-Drive IC
May 2008
FAN73833 — Half-Bridge Gate-Drive IC
Typical Application Circuit
RBOOT
Up to 600V
DBOOT
VDD
LIN
1 LIN
VB 8
HIN
2 HIN
HO 7
3 VDD
VS 6
CBOOT
4 COM
Load
LO 5
Figure 1. Application Circuit for Half-Bridge
Internal Block Diagram
8
VB
7
HO
6
VS
3
VDD
5
LO
4
COM
UVLO
HIN
R
S
Q
HS(ON/OFF)
2
UVLO
100K
SHOOT-THOUGH
PREVENTION
LS(ON/OFF)
1
100K
DELAY
DEAD TIME
{ 400ns }
DRIVER
LIN
R
DRIVER
PULSE
GENERATOR
SCHMITT
TRIGGER INPUT
NOISE
CANCELLER
Figure 2. Functional Block Diagram
© 2008 Fairchild Semiconductor Corporation
FAN73833 • Rev.1.0.0
www.fairchildsemi.com
2
FAN73833 — Half-Bridge Gate-Drive IC
Pin Configuration
1
HIN
2
VDD
3
COM
4
FAN73833
LIN
8
VB
7
HO
6
VS
5
LO
Figure 3. Pin Configuration (Top View)
Pin Definitions
Pin #
Name
Description
1
LIN
Logic Input for Low-Side Driver
2
HIN
Logic Input for High-Side Driver
3
VDD
Low-Side Supply Voltage
4
COM
Logic Ground and Low-Side Driver Return
5
LO
Low-Side Driver Output
6
VS
High-Side Floating Supply Return
7
HO
High-Side Driver Output
8
VB
High-Side Floating Supply
© 2008 Fairchild Semiconductor Corporation
FAN73833 • Rev.1.0.0
www.fairchildsemi.com
3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only. TA=25°C, unless otherwise specified.
Symbol
Parameter
VS
High-side Offset Voltage
VB
High-side Floating Supply Voltage
Min.
Max.
Unit
VB-25
VB+0.3
V
-0.3
625.0
V
VS-0.3
VB+0.3
V
VHO
High-side Floating Output Voltage HO
VDD
Low-side and Logic-fixed Supply Voltage
-0.3
25.0
V
VLO
Low-side Output Voltage LO
-0.3
VDD+0.3
V
VIN
Logic Input Voltage (HIN/LIN)
-0.3
VDD+0.3
V
VDD-25
VDD+0.3
V
COM
Logic Ground and Low-side Driver Return
dVS/dt
Allowable Offset Voltage Slew Rate
50
V/ns
0.625
W
Thermal Resistance, Junction-to-Ambient
200
°C/W
TJ
Junction Temperature
+150
°C
TSTG
Storage Temperature
+150
°C
PD
Power Dissipation(1)(2)(3)
θJA
-55
Notes:
1. Mounted on 76.2 x 114.3 x 1.6mm PCB (FR-4 glass epoxy material).
2. Refer to the following standards:
JESD51-2: Integral circuits thermal test method environmental conditions - natural convection;
JESD51-3: Low effective thermal conductivity test board for leaded surface mount packages
3. Do not exceed PD under any circumstances.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
Max.
Unit
VB
High-side Floating Supply Voltage
VS+15
VS+20
V
VS
High-side Floating Supply Offset Voltage
6-VDD
600
V
VDD
Low-side Supply Voltage
15
20
V
VHO
High-side (HO) Output Voltage
VS
VB
V
VLO
Low-side (LO) Output Voltage
COM
VDD
V
VIN
Logic Input Voltage (HIN/LIN)
COM
VDD
V
TA
Ambient Temperature
-40
+125
°C
© 2008 Fairchild Semiconductor Corporation
FAN73833 • Rev.1.0.0
www.fairchildsemi.com
4
FAN73833 — Half-Bridge Gate-Drive IC
Absolute Maximum Ratings
VBIAS (VDD, VBS)=15.0V, and TA=25°C, unless otherwise specified. The VIN and IIN parameters are referenced to COM.
The VO and IO parameters are referenced to VS and COM and are applicable to the respective outputs HO and LO.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
SUPPLY CURRENT SECTION
IQBS
Quiescent VBS Supply Current
VIN=0V or 5V
35
100
µA
IQDD
Quiescent VDD Supply Current
VIN=0V or 5V
80
200
µA
IPBS
Operating VBS Supply Current
fIN=20kHz, rms Value
420
750
µA
IPDD
Operating VDD Supply Current
fIN=20kHz, rms Value
420
750
µA
ILK
Offset Supply Leakage Current
VB=VS=600V
10
µA
POWER SUPPLY SECTION
VDDUV+
VBSUV+
VDD and VBS Supply Under-Voltage
Positive-going Threshold
8.2
9.2
10.1
V
VDDUVVBSUV-
VDD and VBS Supply Under-Voltage
Negative-going Threshold
7.2
8.3
9.3
V
VDDUVH
VBSUVH
VDD and VBS Supply Under-Voltage
Lockout Hysteresis
0.9
V
GATE DRIVER OUTPUT SECTION
VOH
High-level Output Voltage, VBIAS-VO
IO=20mA
VOL
Low-level Output Voltage, VO
IO+
Output High Short-Circuit Pulse
Current(4)
VO=0V, VIN=5V with PW<10µs
250
350
mA
IO-
Output Low Short-Circuit Pulse
Current(4)
VO=15V, VIN=0V with PW<10µs
500
650
mA
VS
Allowable Negative VS Pin Voltage for
IN Signal Propagation to HO
-9.8
1.0
V
0.6
V
-7.0
V
LOGIC INPUT SECTION
VIH
Logic "1" Input Voltage
2.5
VIL
Logic "0" Input Voltage
IIN+
Logic "1" Input Bias Current
VIN=5V
IIN-
Logic "0" Input Bias Current
VIN=0V
RPD
Input Pull-down Resistance
V
50
1.0
V
100
µA
2.0
µA
100
KΩ
Note:
4. This parameter is guaranteed by design.
Dynamic Electrical Characteristics
VBIAS (VDD, VBS)=15.0V, VS=COM, CL=1000pF, and TA = 25°C, unless otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
270
ns
tON
Turn-on Propagation Delay Time
VS=0V
150
tOFF
Turn-off Propagation Delay Time
VS=0V
140
250
ns
tR
Turn-on Rising Time
50
100
ns
tF
Turn-off Falling Time
30
80
ns
DT
Dead Time
450
580
ns
© 2008 Fairchild Semiconductor Corporation
FAN73833 • Rev.1.0.0
330
www.fairchildsemi.com
5
FAN73833 — Half-Bridge Gate-Drive IC
Electrical Characteristics
300
250
250
200
200
tOFF [ns]
tON [ns]
300
150
150
100
100
50
50
0
-40
-20
0
20
40
60
80
100
0
-40
120
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 4. Turn-on Propagation Delay vs. Temp.
Figure 5. Turn-off Propagation Delay vs. Temp.
120
80
100
tF [ns]
tR [ns]
60
80
60
40
40
20
20
0
-40
-20
0
20
40
60
80
100
0
-40
120
-20
0
Temperature [°C]
700
100
600
80
500
40
300
20
0
20
40
60
80
100
0
-40
120
Temperature [°C]
80
100
120
-20
0
20
40
60
80
100
120
Temperature [°C]
Figure 8. Dead Time vs. Temp.
© 2008 Fairchild Semiconductor Corporation
FAN73833 • Rev.1.0.0
60
60
400
-20
40
Figure 7. Turn-off Fall Time vs. Temp.
IIN+[μA]
DT [ns]
Figure 6. Turn-on Rise Time vs. Temp.
200
-40
20
Temperature [°C]
Figure 9. Logic Input High Bias Current vs. Temp.
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6
FAN73833 — Half-Bridge Gate-Drive IC
Typical Characteristics
100
160
80
IQBS [μA]
IQDD [μA]
200
120
80
40
0
-40
60
40
20
-20
0
20
40
60
80
100
0
-40
120
-20
0
Temperature [°C]
750
750
600
600
450
300
150
60
80
100
120
450
300
150
-20
0
20
40
60
80
100
0
-40
120
-20
0
Temperature [°C]
20
40
60
80
100
120
Temperature [°C]
Figure 12. Operating VDD Supply Current vs. Temp.
Figure 13. Operating VBS Supply Current vs. Temp.
9.2
10.0
8.8
VDDUV- [V]
9.6
VDDUV+ [V]
40
Figure 11. Quiescent VBS Supply Current
vs. Temp.
IPBS [μA]
IPDD [μA]
Figure 10. Quiescent VDD Supply Current
vs. Temp.
0
-40
20
Temperature [°C]
9.2
8.4
8.0
8.8
7.6
8.4
-40
-20
0
20
40
60
80
100
7.2
-40
120
Figure 14. VDD UVLO+ vs. Temp.
© 2008 Fairchild Semiconductor Corporation
FAN73833 • Rev.1.0.0
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 15. VDD UVLO- vs. Temp.
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7
FAN73833 — Half-Bridge Gate-Drive IC
Typical Characteristics (Continued)
9.2
9.6
8.8
VBSUV- [V]
VBSUV+ [V]
10.0
9.2
8.4
8.0
8.8
7.6
8.4
-40
-20
0
20
40
60
80
100
7.2
-40
120
-20
0
Temperature [°C]
20
40
60
80
100
120
Temperature [°C]
Figure 16. VBS UVLO+ vs. Temp.
Figure 17. VBS UVLO- vs. Temp.
1.0
0.6
0.5
0.8
VOL [V]
VOH [V]
0.4
0.6
0.4
0.3
0.2
0.2
0.0
-40
0.1
-20
0
20
40
60
80
100
0.0
-40
120
-20
0
Temperature [°C]
3.0
3.0
2.5
2.5
2.0
2.0
1.5
1.0
0.5
0.5
0
20
40
60
80
100
0.0
-40
120
Temperature [°C]
80
100
120
-20
0
20
40
60
80
100
120
Temperature [°C]
Figure 20. Logic High Input Voltage vs. Temp.
© 2008 Fairchild Semiconductor Corporation
FAN73833 • Rev. 1.0.0
60
1.5
1.0
-20
40
Figure 19. Low-Level Output Voltage vs. Temp.
VIL [V]
VIH [V]
Figure 18. High-Level Output Voltage vs. Temp.
0.0
-40
20
Temperature [°C]
Figure 21. Logic Low Input Voltage vs. Temp.
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8
FAN73833 — Half-Bridge Gate-Drive IC
Typical Characteristics (Continued)
FAN73833 — Half-Bridge Gate-Drive IC
Typical Characteristics (Continued)
0
-2
VS [V]
-4
-6
-8
-10
-12
-14
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Figure 22. Allowable Negative VS Voltage vs. Temp.
© 2008 Fairchild Semiconductor Corporation
FAN73833 • Rev. 1.0.0
www.fairchildsemi.com
9
1. Protection Function
2. Switching Time Diagram
1.1 Under-Voltage Lockout (UVLO)
The high- and low-side drivers include under-voltage
lockout (UVLO) protection circuitry for each channel that
monitors the supply voltage (VDD) and bootstrap capacitor voltage (VBS) independently. It can be designed to
prevent malfunction when VDD and VBS are lower than
the specified threshold voltage. The UVLO hysteresis
prevent chattering during power supply transitions.
LIN
50%
50%
More than
dead time
HIN
50%
More than
dead time
50%
50%
tOFF
tOFF
90%
90%
LO
1.2 Shoot-Through Prevention Function
tON
10%
tOFF
The shoot-through prevention circuitry monitors the highand low-side control inputs. It can be designed to prevent
outputs of high and low side from turning on at same
time, as shown Figure 23 and 24.
90%
tON
HO
10%
Figure 25. Switching Time Definition
HIN
LIN
Shoot-Through Prevent
HO
After DT
LO
After DT
Figure 23. Waveforms for Shoot-Through Prevention
HIN
LIN
Shoot-Through Prevent
HO
After DT
LO
Figure 24. Waveforms for Shoot-Through Prevention
© 2008 Fairchild Semiconductor Corporation
FAN73833 • Rev. 1.0.0
www.fairchildsemi.com
10
FAN73833 — Half-Bridge Gate-Drive IC
Application Information
FAN73833 — Half-Bridge Gate-Drive IC
Physical Dimensions
.
5.00
4.80
A
0.65
3.81
8
5
B
6.20
5.80
PIN ONE
INDICATOR
1.75
4.00
3.80
1
5.60
4
1.27
(0.33)
0.25
M
1.27
C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
0.25
0.10
1.75 MAX
0.25
0.19
C
0.51
0.33
0.50 x 45
0.25
R0.10
0.10 C
OPTION A - BEVEL EDGE
GAGE PLANE
R0.10
OPTION B - NO BEVEL EDGE
0.36
NOTES: UNLESS OTHERWISE SPECIFIED
8
0
0.90
0.406
pdip8_dim.pdf
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08AREV13
SEATING PLANE
(1.04)
DETAIL A
SCALE: 2:1
Figure 26. 8-Lead Small Outline Package (SOP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2008 Fairchild Semiconductor Corporation
FAN73833 • Rev.1.0.0
www.fairchildsemi.com
11
FAN73833 — Half-Bridge Gate-Drive IC
© 2008 Fairchild Semiconductor Corporation
FAN73833 • Rev. 1.0.0
www.fairchildsemi.com
12