19-1571; Rev 0; 12/99 Low-Cost, +5V, Serial-Input, Voltage-Output, 14-Bit DAC Features The MAX5544 serial-input, voltage-output, 14-bit monotonic digital-to-analog converter (DAC) operates from a single +5V supply. The DAC output is unbuffered, resulting in low 0.3mA supply current and low 1LSB offset error. The DAC output range is 0V to VREF. The DAC latch accepts a 16-bit serial word. A power-on reset circuit clears the DAC output to 0V (unipolar mode) when power is initially applied. ♦ Full 14-Bit Performance Without Adjustments The 10MHz 3-wire serial interface is SPI™/QSPI™/ MICROWIRE™ compatible and interfaces directly with optocouplers for applications requiring isolation. The MAX5544 is available in an 8-pin SO package. ♦ SPI/QSPI/MICROWIRE-Compatible Serial Interface ♦ +5V Single-Supply Operation ♦ Low Power: 1.5mW ♦ 1µs Settling Time ♦ Unbuffered Voltage Output Directly Drives 60kΩ Loads ♦ Power-On Reset Circuit Clears DAC Output to 0V (unipolar mode) ♦ Schmitt Trigger Inputs for Direct Optocoupler Interface Applications High-Resolution Offset and Gain Adjustment Ordering Information PART TEMP. RANGE PIN-PACKAGE Industrial Process Control MAX5544CSA 0°C to +70°C 8 SO Automated Test Equipment MAX5544ESA -40°C to +85°C 8 SO Data Acquisition Systems Functional Diagram Pin Configuration TOP VIEW VDD MAX5544 OUT 1 AGND 2 REF 14-BIT DAC CS DIN SCLK 16-BIT DATA LATCH OUT 8 VDD MAX5544 6 DIN REF 3 CS 4 AGND 7 DGND 5 SCLK SO CONTROL LOGIC SERIAL INPUT REGISTER DGND SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. MAX5544 General Description MAX5544 Low-Cost, +5V, Serial-Input, Voltage-Output, 14-Bit DAC ABSOLUTE MAXIMUM RATINGS VDD to DGND............................................................-0.3V to +6V CS, SCLK, DIN to DGND..........................................-0.3V to +6V REF to AGND...............................................-0.3V to (VDD +0.3V) AGND to DGND.....................................................-0.3V to +0.3V OUT to AGND, DGND.................................. ............-0.3V to VDD Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70°C) 8-Pin SO (derate 5.88mW/°C above +70°C)................471mW Operating Temperature Ranges MAX5544CSA .....................................................0°C to +70°C MAX5544ESA ..................................................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) ................................ +300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +5V ±5%, VREF = +2.5V, VAGND = VDGND = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE—ANALOG SECTION (RL = ∞) Resolution N 14 Differential Nonlinearity DNL Guaranteed monotonic Integral Nonlinearity INL VDD = 5V Zero-Code Offset Error ZSE Zero-Code Tempco ZSTC Gain Error (Note 1) Bits ±0.5 ±1.0 LSB ±4 ±8 LSB TA = +25°C ±1 TA = TMIN to TMAX ±2 TA = TMIN to TMAX ±0.05 ppm/°C TA = +25°C ±5 TA = TMIN to TMAX ±10 Gain-Error Tempco ±0.1 DAC Output Resistance ROUT (Note 2) Power-Supply Rejection PSR 4.75V ≤ VDD ≤ 5.25V Reference Input Range VREF (Note 3) Reference Input Resistance (Note 4) RREF LSB LSB ppm/°C 6.25 kΩ ±1.0 LSB 3.0 V REFERENCE INPUT 2.0 11.5 kΩ DYNAMIC PERFORMANCE—ANALOG SECTION (RL = ∞) Voltage-Output Slew Rate Output Settling Time 2 SR CL = 10pF (Note 5) 1 To ± /2LSB of FS, CL = 10pF 25 V/µs 1 µs _______________________________________________________________________________________ Low-Cost, +5V, Serial-Input, Voltage-Output, 14-Bit DAC (VDD = +5V ±5%, VREF = +2.5V, VAGND = VDGND = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DAC Glitch Impulse Major-carry transition 10 nVs Digital Feedthrough Code = 0000 hex, CS = VDD, SCLK = VDIN = 0 to VDD levels 10 nVs DYNAMIC PERFORMANCE—REFERENCE SECTION Reference -3dB Bandwidth BW Reference Feedthrough Signal-to-Noise Ratio Reference Input Capacitance Code = FFFC hex 1 MHz Code = 0000 hex, VREF = 1Vp-p at 100kHz 1 mVp-p 83 dB SNR CIN Code = 0000 hex 75 Code = FFFC hex 120 pF STATIC PERFORMANCE—DIGITAL INPUTS Input High Voltage VIH Input Low Voltage VIL 2.4 V 0.8 V Input Current IIN VIN = 0 ±1 µA Input Capacitance CIN (Note 6) 10 pF Hysteresis Voltage VH 0.40 V POWER SUPPLY Positive Supply Range VDD Positive Supply Current IDD 4.75 0.3 Power Dissipation PD 1.5 5.25 V 1.1 mA mW TIMING CHARACTERISTICS (VDD = +5V ±5%, VREF = +2.5V, VAGND = VDGND = 0, CMOS inputs, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 10 MHz SCLK Frequency fCLK SCLK Pulse Width High tCH 45 ns SCLK Pulse Width Low tCL 45 ns tCSS0 45 ns 45 ns 30 ns CS Low to SCLK High Setup CS High to SCLK High Setup tCSS1 SCLK High to CS Low Hold tCSH0 SCLK High to CS High Hold tCSH1 45 ns DIN to SCLK High Setup tDS 40 ns DIN to SCLK High Hold tDH 0 ns VDD High to CS Low (power-up delay) Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: (Note 6) 20 µs Gain error tested at VREF = +2.0V, +2.5V, and +3.0V. ROUT tolerance is typically ±20%. Min/max ranges guaranteed by gain-error test. Operation outside min/max limits will result in degraded performance. Reference input resistance is code dependent, minimum at 8554 hex. Slew-rate value is measured from 0% to 63%. Guaranteed by design. Not production tested. _______________________________________________________________________________________ 3 MAX5544 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (VDD = +5V, VREF = +2.5V, TA = +25°C, unless otherwise noted.) SUPPLY CURRENT vs. TEMPERATURE SUPPLY CURRENT (mA) 0.35 0.30 0.32 0.31 0.30 0.29 0.28 0.27 0.25 0.26 0.20 0 20 40 60 80 0.05 0 -0.05 -0.10 -0.15 100 0 1 2 TEMPERATURE (°C) 3 4 5 -60 6 -20 DIFFERENTIAL NONLINEARITY vs. TEMPERATURE 0.20 100 140 100 140 16k 20k GAIN ERROR vs. TEMPERATURE 0.20 MAX5544-05 0.30 MAX5544-04 0.30 60 TEMPERATURE (°C) REFERENCE VOLTAGE (V) INTEGRAL NONLINEARITY vs. TEMPERATURE 20 MAX5544-06 -20 0.10 -0.20 0.25 -40 MAX5544-03 0.15 ZERO-CODE OFFSET ERROR (LSB) 0.34 0.33 0.40 0.20 MAX5544-02 MAX5544-01 0.35 0.45 SUPPLY CURRENT (mA) ZERO-CODE OFFSET ERROR vs. TEMPERATURE SUPPLY CURRENT vs. REFERENCE VOLTAGE 0.50 0.15 0.20 DNL (LSB) 0 -0.10 0 -DNL -0.10 -0.20 20 60 100 140 -0.20 -60 -20 20 60 100 TEMPERATURE (°C) TEMPERATURE (°C) INTEGRAL NONLINEARITY vs. CODE DIFFERENTIAL NONLINEARITY vs. CODE 0.125 140 5k 10k DAC CODE 15k 20k 60 160 0 -0.125 -0.250 20 200 REFERENCE CURRENT (µA) DNL (LSB) -0.125 -20 REFERENCE CURRENT vs. CODE 0.125 0 -60 TEMPERATURE (°C) 0.250 MAX5544-07 0.250 0 -0.05 -0.15 -0.30 -20 0 MAX5544-09 -0.30 -60 0.05 -0.10 -INL -0.20 4 +DNL MAX5544-08 INL (LSB) 0.10 +INL GAIN ERROR (LSB) 0.10 0.10 INL (LSB) MAX5544 Low-Cost, +5V, Serial-Input, Voltage-Output, 14-Bit DAC 120 80 40 0 -0.250 0 5k 10k DAC CODE 15k 20k 0 4k 8k 12k DAC CODE _______________________________________________________________________________________ Low-Cost, +5V, Serial-Input, Voltage-Output, 14-Bit DAC FULL-SCALE STEP RESPONSE (fSCLK = 10MHz) MAX5544-11 MAX5544-10 FULL-SCALE STEP RESPONSE (fSCLK = 20MHz) OUT 500mV/div OUT 500mV/div 1µs/div 400ns/div CL = 13pF RL = ∞ CL = 13pF RL = ∞ MAJOR-CARRY OUTPUT GLITCH MAX5544-13 MAX5544-12 DIGITAL FEEDTHROUGH CS 5V/div SCLK 5V/div OUT AC-COUPLED 100mV/div OUT AC-COUPLED 50mV/div 2µs/div CODE = 0000 hex 2µs/div ______________________________________________________________Pin Description PIN NAME 1 OUT FUNCTION 2 AGND 3 REF Voltage Reference Input. Connect to external +2.5V reference. 4 CS Chip-Select Input 5 SCLK 6 DIN 7 DGND 8 VDD DAC Output Voltage Analog Ground Serial-Clock Input. Duty cycle must be between 40% and 60%. Serial-Data Input Digital Ground +5V Supply Voltage _______________________________________________________________________________________ 5 MAX5544 Typical Operating Characteristics (continued) (VDD = +5V, VREF = +2.5V, TA = +25°C, unless otherwise noted.) MAX5544 Low-Cost, +5V, Serial-Input, Voltage-Output, 14-Bit DAC Detailed Description The MAX5544 voltage-output, 14-bit digital-to-analog converter (DAC) offers 14-bit monotonicity with less than 1LSB differential linearity error. Serial-data transfer minimizes the number of package pins required. The MAX5544 is composed of two matched DAC sections, with a 12-bit inverted R-2R DAC forming the 12LSBs and the 4MSBs derived from 15 identically matched resistors. This architecture allows the lowest glitch energy to be transferred to the DAC output on major-carry transitions. It also decreases the DAC output impedance by a factor of eight compared to a standard R-2R ladder, allowing unbuffered operation in medium-load applications. Figure 1 is the timing diagram. Digital Interface The MAX5544 digital interface is a standard 3-wire connection compatible with SPI/QSPI/MICROWIRE interfaces. The chip-select input (CS) frames the serial data loading at the data input pin (DIN). Immediately following CS’s high-to-low transition, the data is shifted synchronously and latched into the input register on the rising edge of the serial-clock input (SCLK). After 16 data bits (14 data bits, plus two sub-bits set to zero) have been loaded into the serial input register, it transfers its contents to the DAC latch on CS’s low-to-high transition (Figure 2). Note that if CS does not remain low during the entire 16 SCLK cycles, data will be corrupted. In this case, reload the DAC latch with a new 16-bit word. External Reference The MAX5544 operates with external voltage references from 2V to 3V. The reference voltage determines the DAC’s full-scale output voltage. Power-On Reset The MAX5544 has a power-on reset circuit to set the DAC’s output to 0V in unipolar mode when VDD is first applied. This ensures that unwanted DAC output voltages will not occur immediately following a system power-up, such as after power loss. In bipolar mode, the DAC output is set to -VREF. ;;;;;;;; ;;;;;;;;; ; ; ;; tCSH1 CS tCSHO tCSSO tCH tCSS1 tCL SCLK tDH tDS D13 DIN D12 S0 Figure 1. Timing Diagram CS DAC UPDATED SCLK SUB-BITS DIN D13 D12 D11 D10 D9 D8 D7 D6 MSB D5 D4 D3 D2 D1 D0 S1 S0 LSB Figure 2. 3-Wire Interface Timing Diagram 6 _______________________________________________________________________________________ Low-Cost, +5V, Serial-Input, Voltage-Output, 14-Bit DAC Reference and Analog Ground Inputs The MAX5544 operates with external voltage references from 2V to 3V, and maintains 14-bit performance with proper reference selection and application. Ideally, the reference’s temperature coefficient should be less than 1.5ppm/°C to maintain 14-bit accuracy to within 1LSB over the commercial (0°C to +70°C) temperature range. Since this converter is designed as an inverted R-2R voltage-mode DAC, the input resistance seen by the voltage reference is code dependent. The worstcase input-resistance variation is from 11.5kΩ (at code 8555 hex) to 200kΩ (at code 0000 hex). The maximum change in load current for a 2.5V reference is 2.5V / 11.5kΩ = 217µA; therefore, the required load regulation is 28ppm/mA for a maximum error of 0.1LSB. This implies a reference output impedance of <71mΩ. In addition, the impedance of the signal path from the voltage reference to the reference input must be kept low because it contributes directly to the load-regulation error. The requirement for a low-impedance voltage reference is met with capacitor bypassing at the reference inputs and ground. A 0.1µF ceramic capacitor with short leads between REF and AGND provides high-frequency bypassing. A surface-mount ceramic chip capacitor is preferred because it has the lowest inductance. An additional 10µF between REF and AGND provides lowfrequency bypassing. A low-ESR tantalum, film, or organic semiconductor capacitor works well. Leaded capacitors are acceptable because impedance is not as critical at lower frequencies. The circuit can benefit from even larger bypassing capacitors, depending on the stability of the external reference with capacitive loading. If separate force and sense lines are not used, connect the appropriate force and sense pins together close to the package. AGND must also be low impedance, as load-regulation errors will be introduced by excessive AGND resistance. As in all high-resolution, high-accuracy applications, separate analog and digital ground planes yield the best results. Connect DGND to AGND at the AGND pin to form the “star” ground for the DAC system. For the best possible performance, always refer remote DAC loads to this system ground. Unbuffered Operation Unbuffered operation reduces power consumption as well as offset error contributed by the external output buffer. The R-2R DAC output is available directly at OUT, allowing 14-bit performance from +VREF to AGND without degradation at zero-scale. The DAC’s output impedance is also low enough to drive medium loads (RL > 60kΩ) without degradation of INL or DNL; only the gain error is increased by externally loading the DAC output. External Output Buffer Amplifier In unipolar mode, the output amplifier is used in a voltage-follower connection. The DAC’s output resistance is constant and is independent of input code; however, the output amplifier’s input impedance should still be as high as possible to minimize gain errors. The DAC’s output capacitance is also independent of input code, thus simplifying stability requirements on the external amplifier. In single-supply applications, precision amplifiers with input common-mode ranges including AGND are available; however, their output swings do not normally include the negative rail (AGND) without significant performance degradation. A single-supply op amp, such as the MAX495, is suitable if the application does not use codes near zero. Since the LSBs for a 14-bit DAC are extremely small (152.6µV for VREF = 2.5V), pay close attention to the external amplifier’s input specification. The input offset voltage can degrade the zero-scale error and might require an output offset trim to maintain full accuracy if the offset voltage is greater than 1/2LSB. Similarly, the input bias current multiplied by the DAC output resistance (typically 6.25kΩ) contributes to the zero-scale error. Temperature effects also must be taken into consideration. Over the commercial temperature range, the offset voltage temperature coefficient (referenced to +25°C) must be less than 1.7µV/°C to add less than 1/2LSB of zero-scale error. The external amplifier’s input resistance forms a resistive divider with the DAC output resistance, which results in a gain error. To contribute less than 1/2LSB of gain error, the input resistance typically must be greater than: 6.25kΩ / 1 1 = 205MΩ 2 214 The settling time is affected by the buffer input capacitance, the DAC’s output capacitance, and PC board capacitance. The typical DAC output voltage settling time is 1µs for a full-scale step. Settling time can be significantly less for smaller step changes. Assuming a single time-constant exponential settling response, a full-scale step takes 10.4 time constants to settle to within 1/2LSB of the final output voltage. The time constant is equal to the DAC output resistance multiplied by the total output capacitance. The DAC output capacitance is typically 10pF. Any additional output capacitance will increase the settling time. _______________________________________________________________________________________ 7 MAX5544 Applications Information MAX5544 Low-Cost, +5V, Serial-Input, Voltage-Output, 14-Bit DAC The external buffer amplifier’s gain-bandwidth product is important because it increases the settling time by adding another time constant to the output response. The effective time constant of two cascaded systems, each with a single time-constant response, is approximately the root square sum of the two time constants. The DAC output’s time constant is 1µs / 10.4 = 96ns, ignoring the effect of additional capacitance. If the time constant of an external amplifier with 1MHz bandwidth is 1 / 2π (1MHz) = 159ns, then the effective time constant of the combined system is: 2 2 96ns + 159ns = 186ns ( ) ( ) This suggests that the settling time to within 1/2LSB of the final output voltage, including the external buffer amplifier, will be approximately 10.4 • 186ns = 1.93µs. Digital Inputs and Interface Logic The digital interface for the 14-bit DAC is based on a 3wire standard that is SPI/QSPI/MICROWIRE compatible. The three digital inputs (CS, DIN, and SCLK) load the digital input data serially into the DAC. All of the digital inputs include Schmitt-trigger buffers to accept slow-transition interfaces. This means that optocouplers can interface directly to the MAX5544 without additional external logic. The digital inputs are TTL/ CMOS-logic compatible. Unipolar Configuration Figure 3 shows the MAX5544 configured for unipolar operation with an external op amp. The op amp is set for unity gain, and Table 1 shows the codes for this circuit. +2.5V +5V Table 1. Unipolar Code Table DAC LATCH CONTENTS MSB ANALOG OUTPUT, VOUT LSB 1111 1111 1111 11(00) VREF • (16,383 / 16,384) 1000 0000 0000 00(00) VREF • (8192 / 16,384) = 1/2VREF 0000 0000 0000 01(00) VREF • (1 / 16,834) 0000 0000 0000 00(00) 0V Power-Supply Bypassing and Ground Management For optimum system performance, use PC boards with separate analog and digital ground planes. Wire-wrap boards are not recommended. Connect the two ground planes together at the low-impedance power-supply source. Connect DGND and AGND together at the IC. The best ground connection can be achieved by connecting the DAC’s DGND and AGND pins together and connecting that point to the system analog ground plane. If the DAC’s DGND is connected to the system digital ground, digital noise may get through to the DAC’s analog portion. Bypass VDD with a 0.1µF ceramic capacitor connected between V DD and AGND. Mount it with short leads close to the device. Ferrite beads can also be used to further isolate the analog and digital power supplies. Chip Information TRANSISTOR COUNT: 2209 SUBSTRATE CONNECTED TO DGND 10µF 0.1µF 0.1µF MC68XXXX VDD PCS0 CS MOSI DIN SCLK SCLK REF MAX495 MAX5544 DGND OUT UNIPOLAR OUT EXTERNAL OP AMP AGND Figure 3. Typical Operating Circuit Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.