ISL54200 ® Data Sheet January 24, 2007 FN6408.0 USB 2.0 High/Full Speed Multiplexer Features The Intersil ISL54200 dual 2:1 multiplexer IC is a single supply part that can operate from a single 2.7V to 5.5V supply. It contains two SPDT (Single Pole/Double Throw) switches configured as a DPDT. The part was designed for switching between USB High-Speed and USB Full-Speed sources in portable battery powered products. • High Speed (480Mbps) and Full Speed (12Mbps) Signaling Capability per USB 2.0 • 1.8V Logic Compatible (2.7V to +3.6V supply) • Enable Pin to Open all Switches • -3dB Frequency - HSx Switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880MHz - FSx Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550MHz The 7Ω normally-closed (NC) FSx switches can swing rail to rail and were specifically designed to pass USB full speed data signals (12Mbps) that range from 0V to 3.6V. The 4.5Ω normally-open (NO) HSx switches have high bandwidth and low capacitance and were specifically designed to pass USB high speed data signals (480Mbps) with minimal distortion. • Cross-talk @ 1MHz . . . . . . . . . . . . . . . . . . . . . . . . . -70dB • OFF Isolation @ 100kHz . . . . . . . . . . . . . . . . . . . . . -98dB • Single Supply Operation (VDD) . . . . . . . . . . . . 2.7V to 5.5V The part can be used in Personal Media Players and other portable battery powered devices that need to switch between a high-speed transceiver and a full-speed transceiver while connected to a single USB host (computer). • Available in Ultra-thin µTQFN and TDFN Packages The digital logic inputs are 1.8V logic compatible when operated with a 2.7V to 3.6V supply. The part has an enable pin to open all switches. It can be used to facilitate proper bus disconnect and connection when switching between the USB sources. • MP3 and other Personal Media Players • Pb-Free Plus Anneal (RoHS Compliant) Applications • Cellular/Mobile Phones • PDA’s • Digital Cameras and Camcorders The ISL54200 is available in a 10 Ld 3mmx3mm TDFN and a small 10 Ld 2.1mmx1.6mm µTQFN packages. It operates over a temperature range of -40 to +85°C. Application Block Diagram 3.3V µCONTROLLER VDD ISL54200 IN USB CONNECTOR EN LOGIC CIRCUITRY VBUS 4MΩ HSD1 D- HSD2 USB HIGH-SPEED TRANSCEIVER COMD1 D+ FSD1 USB FULL-SPEED FSD2 TRANSCEIVER COMD2 GND GND PORTABLE MEDIA DEVICE 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL54200 Pinouts ISL54200 (10 LD µTQFN) TOP VIEW EN ISL54200 (10 LD TDFN TOP VIEW 10 VDD LOGIC CONTROL 1 4M 10 EN IN 2 9 HSD1 COMD1 3 8 HSD2 COMD2 4 7 FSD1 GND 5 6 FSD2 4M 9 HSD1 2 8 HSD2 COMD1 3 7 FSD1 COMD2 4 6 FSD2 VDD 1 IN LOGIC CONTROL GND 5 NOTE: 1. ISL54200 Switches Shown for IN = Logic “0” and EN = Logic “1”. Ordering Information PART NUMBER (Note) PART MARKING TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # ISL54200IRZ 200Z -40 to +85 10 Ld 3x3 TDFN L10.3x3A ISL54200IRZ-T 200Z -40 to +85 10 Ld 3x3 TDFN Tape and Reel L10.3x3A ISL54200IRUZ-T FM -40 to +85 10 Ld 2.1x1.6mm μTQFN Tape and Reel L10.2.1x1.6A NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Truth Table Pin Descriptions ISL54200 ISL54200 EN IN FSD1, FSD2 HSD1, HSD2 PIN NO. NAME 1 0 ON OFF 1 VDD 1 1 OFF ON 2 IN 0 X OFF OFF 3 COMD1 USB Common Port 4 COMD2 USB Common Port 5 GND Ground Connection 6 FSD1 Full Speed USB Differential Port 7 FSD2 Full Speed USB Differential Port 8 HSD1 High Speed USB Differential Port 9 HSD2 High Speed USB Differential Port 10 EN Logic “0” when ≤0.5V, Logic “1” when ≥1.4V with a 2.7V to 3.6V Supply. X = Don’t Care 2 FUNCTION Power Supply Select Logic Control Input Bus Switch Enable FN6408.0 January 24, 2007 ISL54200 Absolute Maximum Ratings Thermal Information VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 6.0V Input Voltages FSD2, FSD1, HSD2, HSD1 (Note 2) . . . . . - 1V to ((VDD) +0.3V) IN, EN (Note 2). . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((VDD) +0.3V) Output Voltages COMD1, COMD2 (Note 2) . . . . . . . . . . . . . . . . . . . . . . . -1V to 5V Continuous Current (HSD2, HSD1, FSD2, FSD1). . . . . . . . . ±40mA Peak Current (HSD2, HSD1, FSD2, FSD1) (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . ±100mA ESD Rating: HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>7kV MM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>400V CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.4kV Thermal Resistance (Typical, Note 3) qJA (°C/W) 10 Ld 3x3 TDFN Package . . . . . . . . . . . . . . . . . . . . 55 10 Ld µTQFN Package . . . . . . . . . . . . . . . . . . . . . . 140 Maximum Junction Temperature (Plastic Package). . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C Operating Conditions Temperature Range ISL54200IRZ and ISL54200IRUZ . . . . . . . . . . . . . . -40°C to +85°C VDD Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 2. Signals on FSD1, FSD2, HSD1, HSD2, COMD1, COMD2, EN, IN exceeding VDD or GND by specified amount are clamped. Limit current to maximum current ratings. 3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications - 2.7V to 3.6V Supply Test Conditions: VDD = +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V, VENH = 1.4V, VENL = 0.5V, (Notes 4, 6), Unless Otherwise Specified PARAMETER TEST CONDITIONS TEMP (°C) MIN (Note 5) TYP MAX (Note 5) UNITS ANALOG SWITCH CHARACTERISTICS NC Switches (FSD1, FSD2) Analog Signal Range, VANALOG VDD = 3.3V, IN = 0V, EN = 3.3V Full 0 - VDD V ON Resistance, r(ON) VDD = 3.3V, IN = 0.5V, EN = 1.4V, ICOMx = 40mA, VFSD1 or VFSD2 = 0V to 3.3V, (See Figure 4) +25 - 7 10 Ω Full - - 15 Ω r(ON) Matching Between Channels, VDD = 3.3V, IN = 0.5V, EN = 1.4V, ICOMx = 40mA, Δr(ON) VFSD1 or VFSD2 = Voltage at max r(ON)over signal range of 0V to 3.3V, (Note 8) +25 - 0.1 0.35 Ω Full - - 0.4 Ω r(ON) Flatness, rFLAT(ON) VDD = 3.3V, IN = 0.5V, EN = 1.4V, ICOMx = 40mA, VFSD1 or VFSD2 = 0V to 3.3V, (Note 7) +25 - 4 6 Ω Full - - 8 Ω V+ = 3.6V, IN = 3.6V, EN = 0V and 3.6V, VCOMx = 0.3V, 3V, VFSX = 3V, 0.3V +25 -20 2 20 nA Full -70 - 70 nA V+ = 3.6V, IN = 0V, EN = 3.6V, VCOMx = 0.3V, 3V, VFSX = 0.3V, 3V +25 -20 2 20 nA Full -70 - 70 nA Analog Signal Range, VANALOG VDD = 3.3V, IN = 3.3V, EN = 3.3V Full 0 - VDD V ON Resistance, r(ON) VDD = 3.3V, IN = 1.4V, EN = 1.4V, ICOMx = 1mA, VHSD2 or VHSD1 = 3.3V (See Figure 3) +25 - 20 30 Ω Full - - 35 Ω VDD = 3.3V, IN = 1.4V, EN = 1.4V, ICOMx = 40mA, VHSD2 or VHSD1 = 0V to 400mV (See Figure 3) +25 - 4.5 6 Ω Full - - 8 Ω r(ON) Matching Between Channels, VDD = 3.3V, IN = 1.4V, EN = 1.4V, ICOMx = 40mA, Δr(ON) VHSD2 or VHSD1= Voltage at max r(ON), Voltage at max r(ON) over signal range of 0V to 400mV (Note 8) +25 - 0.01 0.1 Ω Full - - 0.5 Ω r(ON) Flatness, rFLAT(ON) +25 - 0.4 1 Ω Full - - 1.5 Ω OFF Leakage Current, IFSX(OFF) ON Leakage Current, IFSX(ON) NO Switches (HSD1, HSD2) ON Resistance, r(ON) VDD = 3.3V, IN = 1.4V, EN = 1.4V, ICOMx = 40mA, VHSD2 or VHSD1 = 0V to 400mV, (Note 7) 3 FN6408.0 January 24, 2007 ISL54200 Electrical Specifications - 2.7V to 3.6V Supply Test Conditions: VDD = +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V, VENH = 1.4V, VENL = 0.5V, (Notes 4, 6), Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS OFF Leakage Current, IHSD2(OFF) or IHSD1(OFF) VDD = 3.6V, IN = 0V, EN = 0 and 3.6V, VCOMD1 or VCOMD2 = 3V, 0.3V, VHSD2 or VHSD1 = 0.3V, 3V ON Leakage Current, IHSD2(ON) or VDD = 3.6V, IN = 3.6V, EN = 3.6V, VCOMD1 or IHSD1(ON) VCOMD2 = 0.3V, 3.0V, VHSD2 or VHSD1 = 0.3V, 3.0V TEMP (°C) MIN (Note 5) TYP MAX (Note 5) UNITS +25 -20 2 20 nA Full -70 - 70 nA +25 -20 2 20 nA Full -70 - 70 nA DYNAMIC CHARACTERISTICS Turn-ON Time, tON VDD = 3.3V, RL = 45Ω, CL = 10pF, (See Figure 1) +25 - 25 - ns Turn-OFF Time, tOFF VDD = 3.3V, RL = 45Ω, CL = 10pF, (See Figure 1) +25 - 15 - ns Break-Before-Make Time Delay, tD VDD = 3.3V, RL = 45Ω, CL = 10pF, (See Figure 2) +25 - 7 - ns Skew, tSKEW (HSx Switch) VDD = 3.3V, IN = 3.3V, EN = 3.3V, RL = 45Ω, CL = 10pF, tR = tF = 720ps at 480Mbps, (Duty Cycle = 50%) (See Figure 7) +25 - 50 - ps Total Jitter, tJ (HSx Switch) VDD =3.3V, IN = 3.3V, EN = 3.3V, RL = 45Ω, CL = 10pF, tR = tF = 720ps at 480Mbps +25 - 210 - ps Propagation Delay, tPD (HSx Switch) VDD = 3.3V, IN = 3.3V, EN = 3.3V, RL = 45Ω, CL = 10pF, (See Figure 7) +25 - 250 - ps Skew, tSKEW (FSx Switch) VDD = 3.3V, IN = 0V, EN = 3.3V, RL = 39Ω, CL = 50pF, tR = tF = 12ns at 12Mbps, (Duty Cycle = 50%) (See Figure 7) +25 - 0.15 - ns Rise /Fall Time Mismatch, tM (FSx Switch) VDD = 3.3V, IN = 0V, EN = 3.3V, RL = 39Ω, CL = 50pF, tR = tF = 12ns at 12Mbps, (Duty Cycle = 50%) +25 - 10 - % Total Jitter, tJ (FSx Switch) VDD = 3.3V, IN = 0V, EN = 3.3V, RL = 39Ω, CL = 50pF, tR = tF = 12ns at 12Mbps +25 - 1.6 - ns Propagation Delay, tPD (FSx Switch) VDD = 3.3V, IN = 0V, EN = 3.3V, RL = 39Ω, CL = 50pF, (See Figure 7 +25 - 0.9 - ns Crosstalk VDD = 3.3V, RL = 45Ω, f = 1MHz (See Figure 6) +25 - -70 - dB OFF Isolation VDD = 3.3V, RL = 45Ω, f = 100kHz +25 - -98 - dB FSx Switch -3dB Bandwidth Signal = -10dBm, 1.0VDC offset, RL = 45Ω, CL = 5pF +25 - 880 - MHz HSx Switch -3dB Bandwidth Signal = -10dBm, 0.2VDC offset, RL = 45Ω, CL = 5pF +25 - 550 - MHz HSx OFF Capacitance, CHSxOFF f = 1MHz, VDD = 3.3V, IN = 0V, EN = 3.3V, VHSD1 or VHSD2 = VCOMx = 0V, (See Figure 5) +25 - 6 - pF FSx OFF Capacitance, CFSxOFF f = 1MHz, VDD = 3.3V, IN = 3.3V, EN = 3.3V, VFSD1 or VFSD2 = VCOMx = 0V, (See Figure 5) +25 - 9 - pF COM ON Capacitance, CCOMX(ON) f = 1MHz, VDD = 3.3V, IN = 3.3V, EN = 3.3V, VHSD1 or VHSD2 = VCOMx = 0V, (See Figure 5) +25 - 12 - pF COM ON Capacitance, CCOMX(ON) f = 1MHz, VDD = 3.3V, IN = 0V, EN = 3.3V, VFSD1 or VFSD2 = VCOMx = 0V, (See Figure 5) +25 - 15 - pF Full 2.7 - 5.5 V +25 - 20 60 nA Full - - 80 nA POWER SUPPLY CHARACTERISTICS Power Supply Range, VDD Positive Supply Current, IDD VDD = 3.6V, IN = 0V or 3.6V, EN = 0V or 3.6V 4 FN6408.0 January 24, 2007 ISL54200 Electrical Specifications - 2.7V to 3.6V Supply Test Conditions: VDD = +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V, VENH = 1.4V, VENL = 0.5V, (Notes 4, 6), Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS TEMP (°C) MIN (Note 5) TYP MAX (Note 5) UNITS DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL, VENL VDD = 2.7V to 3.6V Full - - 0.5 V Input Voltage High, VINH, VENH VDD = 2.7V to 3.6V Full 1.4 - - V Input Current, IINL, IENL VDD = 3.6V, IN = 0V, EN = 0V Full - 10 - nA Input Current, IINH VDD = 3.6V, IN = 3.6 Full - 10 - nA Input Current, IENH VDD = 3.6V, EN = 3.6 Full - 1 - μA NOTES: 4. VLOGIC = Input voltage to perform proper function. 5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 6. Parameters with limits are 100% tested at +25°C. Limits across the full temperature range are guaranteed by design and correlation. 7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range 8. r(ON) matching between channels is calculated by subtracting the channel with the highest max r(ON) value from the channel with lowest max r(ON) value, between HSD2 and HSD1 or between FSD2 and FSD1. Test Circuits and Waveforms LOGIC INPUT 50% VINL VINPUT tOFF SWITCH INPUT VINPUT SWITCH INPUT EN VOUT HSx or FSx COMx IN VOUT 90% SWITCH OUTPUT VDD tr < 20ns tf < 20ns VINH 90% VIN GND RL 45W CL 10pF 0V tON Logic input waveform is inverted for switches that have the opposite logic sense. FIGURE 1A. MEASUREMENT POINTS Repeat test for all switches. CL includes fixture and stray capacitance. RL --------------------------V OUT = V (INPUT) R + r L ( ON ) FIGURE 1B. TEST CIRCUIT FIGURE 1. SWITCHING TIMES 5 FN6408.0 January 24, 2007 ISL54200 Test Circuits and Waveforms (Continued) VDD VINH C EN LOGIC INPUT FSD1 or FSD2 VINPUT VINL VOUT COMx HSD1 or HSD2 SWITCH OUTPUT VOUT CL 10pF RL 45Ω IN 90% GND VIN 0V tD Repeat test for all switches. CL includes fixture and stray capacitance. FIGURE 2B. TEST CIRCUIT FIGURE 2A. MEASUREMENT POINTS FIGURE 2. BREAK-BEFORE-MAKE TIME VDD VDD C C r(ON) = V1/ICOMx r(ON) = V1/40mA HSx FSx VHSX VFSX IN V1 ICOMx 1.4V IN V1 0.5V 40mA COMx GND COMx EN GND 1.4V EN 1.4V Repeat test for all switches. Repeat test for all switches. FIGURE 3. HSx Switch r(ON) TEST CIRCUIT 6 FIGURE 4. FSx Switch r(ON) TEST CIRCUIT FN6408.0 January 24, 2007 ISL54200 Test Circuits and Waveforms (Continued) VDD VDD C C EN EN SIGNAL GENERATOR HSx or FSx HSx IN IMPEDANCE ANALYZER IN VINL OR VINH COMx GND 45Ω COMx VIN FSx COMx ANALYZER N.C. GND RL Signal direction through switch is reversed, worst case values are recorded. Repeat test for all switches. Repeat test for all switches. FIGURE 6. CROSSTALK TEST CIRCUIT FIGURE 5. CAPACITANCE TEST CIRCUIT VDD C tri EN 90% DIN+ 10% VIN 50% tskew_i DIN- VIN 15.8Ω DIN+ 90% 50% COMD2 143Ω 10% 15.8Ω DIN- tfi tro OUT+ D2 CL COMD1 OUT- D1 CL 143Ω 45Ω 45Ω 90% 10% OUT+ OUT- GND 50% tskew_o 50% 90% 10% tf0 |tro-tri| Delay Due to Switch for Rising Input and Rising Output Signals. |tfo-tfi| Delay Due to Switch for Falling Input and Falling Output Signals. |tskew_0| Change in Skew through the Switch for Output Signals. |tskew_i| Change in Skew through the Switch for Input Signals. FIGURE 7B. TEST CIRCUIT FIGURE 7A. MEASUREMENT POINTS FIGURE 7. SKEW TEST 7 FN6408.0 January 24, 2007 ISL54200 Application Block Diagram 3.3V µCONTROLLER VDD ISL54200 IN USB CONNECTOR EN LOGIC CIRCUITRY VBUS 4MΩ HSD1 D- HSD2 USB HIGH-SPEED TRANSCEIVER COMD1 D+ FSD1 USB FULL-SPEED FSD2 TRANSCEIVER COMD2 GND GND PORTABLE MEDIA DEVICE Detailed Description The ISL54200 device is a dual single pole/double throw (SPDT) analog switch that operates from a single DC power supply in the range of 2.7V to 5.5V. It was designed to function as dual 2-to-1 multiplexer to select between a USB high-speed transceiver and a USB full-speed transceiver in portable battery powered products. It is offered in a TDFN package and a small µTQFN package for use in MP3 players, cameras, PDAs, cellphones, and other personal media players. The device has an enable pin to open all switches. The part consist of two 7Ω full speed (FSx) switches and two 4.5Ω high speed (HSx) switches. The FSx switches can swing from 0V to VDD. They were designed to pass USB fullspeed (12Mbps) differential data signals with minimal distortion. The HSx switches have high bandwidth and low capacitance to pass USB high-speed (480Mbps) differential data signals with minimal edge and phase distortion. The ISL54200 was designed for MP3 players, cameras, cellphones, and other personal media player applications that have both high-speed and full-speed transceivers and need to multiplex between these USB sources to a single USB host (computer). A typical application block diagram of this functionality is shown above. A detailed description of the two types of switches are provided in the sections below. FSx Switches (FSD1, FSD2) The two FSx switches (FSD1, FSD2) are bidirectional switches that can pass rail-to-rail signals. When powered with a 3.3V supply, these switches have a nominal r(ON) resistance of 7Ω over the signal range of 0V to 3.3V. They 8 were specifically designed to pass USB full-speed (12Mbps) differential signals and meet the USB 2.0 full-speed signal quality specifications. See eye diagram Figure 8. The FSx switches can also pass USB high speed signals (480Mbps) but do not quite meet the USB 2.0 high speed signal quality eye diagram compliance requirement. The maximum signal range for the FSx switches is from -1.5V to VDD. The signal voltage should not be allowed to exceed the VDD voltage rail or go below ground by more than -1.5V. When operated with a 2.7V to 3.6V supply, the FSx switches are active (turned ON) whenever the IN logic control voltage is ≤0.5V and the EN logic voltage ≥1.4V. HSx Switches (HSD1, HSD2) The two HSx switches (HSD2, HSD1) are bidirectional switches that can pass rail-to-rail signals. When powered with a 3.3V supply these switches have a nominal r(ON) of 4.5Ω over the signal range of 0V to 400mV with a r(ON) flatness of 0.4Ω. The r(ON) matching between the HSD1 and HSD2 switches over this signal range is only 0.01Ω ensuring minimal impact by the switches to USB high speed signal transitions. As the signal level increases the r(ON) switch, resistance increases. At signal level of 3.3V the switch resistance is nominally 20Ω. The HSx switches were specifically designed to pass USB 2.0 high-speed (480Mbps) differential signals typically in the range of 0V to 400mV. They have low capacitance and high bandwidth to pass the USB high-speed signals with minimum edge and phase distortion to meet USB 2.0 high speed signal quality specifications. See high-speed eye diagrams Figures 9 and 10. FN6408.0 January 24, 2007 ISL54200 The HSx switches can also pass USB full-speed signals (12Mbps) with minimal distortion and meet all the USB requirements for USB 2.0 full-speed signaling. See fullspeed eye diagram Figure 11. The maximum signal range for the HSx switches is from -1.5V to VDD. The signal voltage should not be allow to exceed the VDD voltage rail or go below ground by more than -1.5V. The HSx switches are active (turned ON) whenever the IN voltage is ≥1.4V and the EN logic voltage ≥1.4V when operated with a 2.7V to 3.6V supply. ISL54200 Operation computer. The device will be able to transmit and receive data from the computer at a data rate of 12Mbps. High-speed Mode If the IN pin = Logic “1” and EN pin = Logic “1” the part will go into high-speed mode. In high-speed mode the HSD1 and HSD2 switches are ON and the FSD1 and FSD2 switches are OFF (high impedance). When a USB cable from a computer or USB hub is connected at the common USB connector and the part is in the high-speed mode a link will be established between the high-speed driver section of the media player and the computer. The device will be able to transmit and receive data from the computer at a data rate of 480Mbps. The discussion that follows will discuss using the ISL54200 in the typical application shown in the block diagram on page 9. All Switches OFF Mode POWER If the IN pin = Logic “0” or Logic “1” and EN pin = Logic “0” all of the switches will turn OFF (high impedance). The power supply connected at the VDD (pin 1) provides the DC bias voltage required by the ISL54200 part for proper operation. The ISL54200 can be operated with a VDD voltage in the range of 2.7V to 5.5V. When used in a USB application the VDD voltage should be kept in the range of 3.0V to 5.5V to ensure you get the proper signal levels for good signal quality. The all OFF state can be used to switch between the two USB sections of the media player. When disconnecting from one USB device to the other USB device you can momentarily put the ISL54400 switch in the “all off” state in order to get the computer to disconnect from the one device so it can properly connect to the other USB device when that channel is turned ON. A 0.01µF or 0.1µF decoupling capacitor should be connected from the VDD pin to ground to filter out any power supply noise from entering the part. The capacitor should be located as close to the VDD pin as possible. LOGIC CONTROL The state of the ISL54200 device is determined by the voltage at the IN pin (pin 2) and the EN pin (pin 10). IN is only active when the EN pin is logic “1” (High). Refer to“Truth Table” on page 2. The EN pin is internally pulled low through a 4MΩ resistor to ground. For logic “0” (Low) it can be driven low or allowed to Float. The IN pin must be driven low or high and cannot be left floating. Logic control voltage levels: EN = Logic “0” (Low) when VEN ≤0.5V or Floating. EN = Logic “1” (High) when VEN ≥1.4V IN = Logic “0” (Low) when VIN ≤0.5V. IN = Logic “1” (High) when VIN ≥1.4V Full-speed Mode If the IN pin = Logic “0” and EN pin = Logic “1” the part will be in the full-speed mode. In this mode the FSD1 and FSD2 switches are ON and the HSD1 and HSD2 switches are OFF (high impedance). In a typical application VDD will be in the range of 2.8V to 3.6V and will be connected to the battery or LDO of the portable media device. When a computer or USB hub is plugged into the common USB connector and the part is in the full-speed mode a link will be established between the full-speed driver section of the media player and the 9 FN6408.0 January 24, 2007 ISL54200 Typical Performance Curves TA = +25°C, Unless Otherwise Specified VOLTAGE (0.5V/DIV) VDD = 3.3V TIME (10ns/DIV.) FIGURE 8. EYE PATTERN: 12MBPS USB SIGNAL WITH FSX SWITCHES IN THE SIGNAL PATH 10 FN6408.0 January 24, 2007 ISL54200 Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued) VOLTAGE (835mV/DIV) VDD = 3.3V TIME (0.2ns/DIV.) FIGURE 9. EYE PATTERN WITH FAREND MASK: 480MBPS USB SIGNAL WITH HSX SWITCHES IN THE SIGNAL PATH 11 FN6408.0 January 24, 2007 ISL54200 Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued) VOLTAGE (835mV/DIV) VDD = 3.3V TIME (0.2ns/DIV.) FIGURE 10. EYE PATTERN WITH NEAREND MASK: 480MBPS USB SIGNAL WITH HSX SWITCHES IN THE SIGNAL PATH 12 FN6408.0 January 24, 2007 ISL54200 Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued) VOLTAGE (0.5V/DIV) VDD = 3.3V TIME (0.2ns/DIV.) FIGURE 11. EYE PATTERN: 12MBPS USB SIGNAL WITH HSX SWITCHES IN THE SIGNAL PATH -10 6 V+ = 3.3V ICOM = 40mA 5.5 -20 -30 NORMALIZED GAIN (dB) 85°C 5 r(ON) (Ω) RL = 45Ω VIN = 0.2VP-P to 2VP-P 25°C 4.5 4 -40°C 3.5 -40 -50 -60 -70 -80 -90 -110 3 0 0.1 0.2 0.3 VCOM (V) FIGURE 12. HSx SWITCH ON RESISTANCE vs SWITCH VOLTAGE 13 0.4 0.001 0.01 0.1 1 FREQUENCY (MHz) 10 100 500 FIGURE 13. OFF-ISOLATION FN6408.0 January 24, 2007 ISL54200 Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued) -10 Die Characteristics -20 RL = 45Ω VIN = 0.2VP-P to 2VP-P SUBSTRATE POTENTIAL (POWERED UP): GND (TDFN Paddle Connection: Tie to GND or Float) NORMALIZED GAIN (dB) -30 -40 TRANSISTOR COUNT: 98 -50 -60 PROCESS: Submicron CMOS -70 -80 -90 -110 0.001 0.01 0.1 1 FREQUENCY (MHz) 10 100 500 FIGURE 14. CROSSTALK 14 FN6408.0 January 24, 2007 ISL54200 Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN) D 6 INDEX AREA A L10.2.1x1.6A B N 10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS E SYMBOL 2X MIN NOMINAL MAX 1 2X 2 0.10 C TOP VIEW C A 0.05 C SEATING PLANE 1 0.45 0.50 0.55 - A1 - - 0.05 - 0.127 REF - b 0.15 0.20 0.25 5 D 2.05 2.10 2.15 - E 1.55 1.60 1.65 - A1 e SIDE VIEW k 0.20 - - L 0.35 0.40 0.45 (DATUM A) PIN #1 ID A A3 0.10 C 4xk 2 NX L 0.50 BSC - NX b e 2 Nd 4 3 Ne 1 3 0 12 - NOTES: 5 BOTTOM VIEW CL (A1) L 5 e SECTION "C-C" TERMINAL TIP C C 4 Rev. 3 6/06 0.10 M C A B 0.05 M C 3 (ND-1) X e - 10 (DATUM B) N-1 - N θ N NX (b) NOTES 0.10 C FOR ODD TERMINAL/SIDE b 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on D and E side, respectively. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Maximum package warpage is 0.05mm. 8. Maximum allowable burrs is 0.076mm in all directions. 9. Same as JEDEC MO-255UABD except: No lead-pull-back, "A" MIN dimension = 0.45 not 0.50mm "L" MAX dimension = 0.45 not 0.42mm. 10. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389. 2.50 1.75 0.05 MIN L 2.00 0.80 0.275 0.10 MIN DETAIL “A” PIN 1 ID 0.50 0.25 LAND PATTERN 10 15 FN6408.0 January 24, 2007 ISL54200 Thin Dual Flat No-Lead Plastic Package (TDFN) L10.3x3A 2X 0.10 C A A 10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE D MILLIMETERS 2X 0.10 C B SYMBOL MIN NOMINAL MAX NOTES A 0.70 0.75 0.80 - A1 - - 0.05 - E A3 6 INDEX AREA TOP VIEW B // A C SEATING PLANE 0.08 C b 0.20 0.25 0.30 5, 8 D 2.95 3.0 3.05 - D2 2.25 2.30 2.35 7, 8 E 2.95 3.0 3.05 - E2 1.45 1.50 1.55 7, 8 e 0.50 BSC - k 0.25 - - - L 0.25 0.30 0.35 8 A3 SIDE VIEW D2 (DATUM B) 0.10 C 0.20 REF 7 8 N 10 2 Nd 5 3 Rev. 3 3/06 D2/2 NOTES: 6 INDEX AREA 1 2 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. NX k 3. Nd refers to the number of terminals on D. (DATUM A) 4. All dimensions are in millimeters. Angles are in degrees. E2 E2/2 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. NX L N N-1 NX b 8 e (Nd-1)Xe REF. BOTTOM VIEW 5 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 0.10 M C A B 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Compliant to JEDEC MO-229-WEED-3 except for D2 dimensions. CL NX (b) (A1) L1 5 9 L e SECTION "C-C" C C TERMINAL TIP FOR ODD TERMINAL/SIDE All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 16 FN6408.0 January 24, 2007