CYPRESS CY2CC910OXI

COMLINK™ SERIES
CY2CC910
1:10 Clock Fanout Buffer
Features
Description
• Low-voltage operation
The Cypress series of network circuits are produced using
advanced 0.35 micron CMOS technology, achieving the industries fastest logic and buffers.
• Full-range support:
— 3.3V
The Cypress CY2CC910 fanout buffer features one input and
ten outputs. Ideal for conversion from/to 3.3V/2.5V/1.8V
— 2.5V
— 1.8V
Designed for Data Communications clock management applications, the large fanout from a single input reduces loading
on the input clock.
• Over voltage tolerant input hot swappable
• 1:10 fanout
• Drives either a 50-Ohm or 75-Ohm load
Cypress employs unique AVCMOS type outputs VOI™
(Variable Output Impedance) that dynamically adjust for
variable impedance matching and eliminate the need for
series damping resistors and reduce noise overall.
• Low-input capacitance
• Low-output skew
• Low-propagation delay
• Typical (tpd < 4 ns)
• High-speed operation:
— 200 [email protected]
— 650 [email protected]/3.3V
• Industrial versions available
• Available packages include: SOIC, SSOP
Pin Configuration
Block Diagram
5
7
VDD
9
4 ,8
1 5 ,2 0
11
IN
1
12
INPUT
(AVCMOS)
2 ,6 ,1 0
1 3 ,1 7
14
16
GND
18
19
Q1
IN
Q2
GND
Q3
Q1
VDD
Q2
Q4
GND
Q5
Q3
VDD
Q4
GND
Q6
1
2
3
4
5
6
7
8
9
10
CY2CC910
3
20
19
18
17
16
15
14
13
12
11
VDD
Q10
Q9
GND
Q8
VDD
Q7
GND
Q6
Q5
20 pin SOIC/SSOP
Q7
Q8
Q9
Q 10
OUTPUT
(AVCMOS)
Cypress Semiconductor Corporation
Document #: 38-07348 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 27, 2005
COMLINK™ SERIES
CY2CC910
Pin Description
Pin Number
Pin Name
Description
1
IN
Input
2,6,10,13,17
4,8,15,20
GND
VDD
Power Supply
3,5,7,9,11,12,14,16,18,19
Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,Q10
Output
Ground
Maximum Ratings[1]
Storage Temperature: ................................. –65°C to +150°C
Supply Voltage to Ground Potential
Ambient Temperature:................................... –40°C to +85°C
(Outputs only) ........................................... –0.5V to VDD + 1V
Supply Voltage to Ground Potential
DC Output Voltage.................................... –0.5V to VDD + 1V
VCC .................................................................. –0.5V to 4.6V
Power Dissipation........................................................ 0.75W
Input ................................................................. –0.5V to 5.8V
Variable Output Impedance Control (VOI™)
Pull Up
Pull Down
3.5
3.5
3
3
2.5
2.5
2
2
1.5
1.5
1
1
0.5
0.5
0
0
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.1
-0.18
-0.16
-0.14
-0.12
-0.08
-0.06
-0.04
-0.02
0
Ioh (A)
Iol (A)
Vdd = 3.3 V
-0.1
Vdd = 2.5 V
Vdd = 3.3 V
Vdd = 1.8 V
Vdd = 2.5 V
Vdd = 1.8 V
Figure 1. Output Voltage vs. Output Current (TA = 25°C)
DC Electrical Characteristics @ 3.3V (see Figure 2)
Parameter
Description
Conditions
Min.
Typ.
2.3
3.3
Max.
Unit
0.5
V
5.8
V
VOH
Output High Voltage
VDD = Min., VIN = VIH or VIL IOH = –12 mA
VOL
Output Low Voltage
VIH
Input High Voltage
VDD = Min., VIN = VIH or VIL IOL = 12 mA
Guaranteed Logic High
Level
VIL
Input Low Voltage
Guaranteed Logic Low Level
0.8
V
IIH
Input High Current
VDD = Max.
VIN = 2.7V
1
µA
IIL
Input Low Current
VDD = Max.
VIN = 0.5V
–1
µA
II
Input High Current
VDD = Max., VIN = VDD(Max.)
20
µA
VIK
Clamp Diode Voltage
VDD = Min., IIN = –18 mA
IOK
Continuous Clamp Current
VDD = Max., VOUT = GND
OOFF
Power-down Disable
VDD = GND, VOUT = < 4.5V
VH
Input Hysteresis
0.2
2
–0.7
V
–1.2
V
–50
mA
100
80
µA
mV
Note:
1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Document #: 38-07348 Rev. *B
Page 2 of 9
COMLINK™ SERIES
CY2CC910
DC Electrical Characteristics @ 2.5V (see Figure 2)
Parameter
VOH
Description
Output High Voltage
Conditions
VDD = Min., VIN = VIH or VIL
Min.
Typ.
Max.
Unit
IOH = –7 mA
1.8
V
IOH = 12 mA
1.6
V
VOL
Output Low Voltage
VDD = Min., VIN = VIH or VIL
VIH
Input High Voltage
Guaranteed Logic High Level
VIL
Input Low Voltage
Guaranteed Logic Low Level
0.8
V
IIH
Input High Current
VDD = Max.
VIN = 2.4V
1
µA
IIL
Input Low Current
VDD = Max.
VIN = 0.5V
–1
µA
II
Input High Current
VDD = Max., VIN = VDD(Max.)
20
µA
VIK
Clamp Diode Voltage
VDD = Min., IIN = –18 mA
IOK
Continuous Clamp Current
VDD = Max., VOUT = GND
OOFF
Power Down Disable
VDD = GND, VOUT = < 4.5V
VH
Input Hysteresis
IOL = 12 mA
0.65
V
5.0
V
1.6
–0.7
–1.2
V
–50
mA
100
80
µA
mV
DC Electrical Characteristics @ 1.8V (see Figure 6)
Parameter
Test Condition[2]
Description
VDD
Supply Voltage
Min.
Max.
Unit
1.71
1.89
V
VIH
Input High Voltage
0.65VDD[1.1]
4.3
V
VIL
Input Low Voltage
–0.3
0.35 VDD[0.6]
V
VOH
Output High Voltage
IOH = –2 mA
VOL
Output Low Voltage
IOH = 2 mA
VDD – 0.45[1.2]
V
0.45
V
Max.
Unit
Capacitance
Parameter
Description
Test Conditions
Typ.
CIN
Input Capacitance
VIN = 0V
2.5
pF
COUT
Output Capacitance
VOUT = 0V
6.5
pF
Power Supply Characteristics (see Figure 2)
Parameter
Description
Test Conditions
∆ICC
Delta ICC Quiescent Power
Supply Current
(IDD @ VDD = Max and VIN = VDD) – (IDD @
VDD = Max and VIN = VDD – 0.6V)
ICCD
Dynamic Power Supply
Current
VDD = Max
Input toggling 50% Duty Cycle, Outputs
Open
IC
Total Power Supply Current
VDD = Max
Input toggling 50% Duty
Cycle, Outputs Open fL = 40 MHZ
Min.
Typ
Max
Unit
50
µA
0.63
mA/
MHz
25
mA
Note:
2. Test load conditions: 500-Ohm to ground with approximately 6-pF total loading and 200-MHz maximum frequency.
Document #: 38-07348 Rev. *B
Page 3 of 9
COMLINK™ SERIES
CY2CC910
High Frequency Parametrics
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
DJ
Jitter, Deterministic
50% duty cycle tW(50–50)
The “point to point load circuit”
| Output Jitter – Input Jitter |
See Figure 4
20
ps
Fmax
3.3V
Maximum frequency
VDD = 3.3V
50% duty cycle tW(50–50)
Standard Load Circuit.
See Figure 2
160
MHz
50% duty cycle tW(50–50)
The “point to point load circuit”
See Figure 4
650
Fmax
2.5V
Maximum frequency
VDD = 2.5V
The “point-to-point load circuit”
VIN = 2.4V/0.0V VOUT = 1.7V/0.7V
See Figure 4
200
MHz
Fmax
1.8V
Maximum frequency
VDD = 1.8V
The “6-pF load circuit”
VIN = 1.7/0.0V VOUT = 1.2V/0.4V
See Figure 6
200
MHz
Fmax(20)
Maximum frequency
VDD = 3.3V
20% duty cycle tW(20-80)
The “point to point load circuit”
VIN = 3.0V/0.0V VOUT = 2.3V/0.4V
See Figure 5
250
MHz
tW
3.3V
Minimum pulse
VDD = 3.3V
The “point-to-point load circuit”
VIN = 3.0V/0.0V F = 100 MHz
VOUT = 2.0V/0.8V
See Figure 4
1
ns
tW
2.5V
Minimum pulse
VDD = 2.5V
The “point-to-point load circuit”
VIN = 2.4V/0.0V F = 100 MHz
VOUT = 1.7V/0.7V
See Figure 4
1
ns
tW
1.8V
Minimum pulse
VDD = 1.8V
The “6-pF load circuit”
VIN = 1.7V/0.0V VOUT = 1.2V/0.4V
See Figure 6
1
ns
AC Switching Characteristics @ 3.3V VDD = 3.3V ± 5%, Temperature = –40°C to +85°C
Parameter
Description
Min.
Typ.
Max.
Unit
1.5
2.7
3.5
ns
1.5
2.7
3.5
tPLH
Propagation Delay – Low to High
tPHL
Propagation Delay – High to Low
tR
Output Rise Time
tF
Output Fall Time
tSK(0)
Output Skew: Skew between outputs of the same package (in
phase).
See Figure 10
0.2
ns
tSK(p)
Pulse Skew: Skew between opposite transitions of the same
output (tPHL – tPLH).
See Figure 9
0.2
ns
tSK(t)
Package Skew: Skew between outputs of different packages at See Figure 11
the same power supply voltage, temperature and package type.
0.4
ns
See Figure 3
0.8
ns
V/ns
0.8
V/ns
AC Switching Characteristics @ 2.5V VDD = 2.5V ± 5%, Temperature = –40°C to +85°C
Parameter
Description
tPLH
Propagation Delay – Low to High
tPHL
Propagation Delay – High to Low
tR
Output Rise Time
tF
Output Fall Time
tSK(0)
Output Skew: Skew between outputs of the same package (in phase).
tSK(p)
tSK(t)
Min. Typ. Max. Unit
See Figure 3
1.5
1.5
2.7
3.5
2.7
3.5
0.8
ns
V/ns
0.8
V/ns
0.2
ns
Pulse Skew: Skew between opposite transitions of the same output (tPHL See Figure 9
– tPLH).
0.2
ns
Package Skew: Skew between outputs of different packages at the same See Figure 11
power supply voltage, temperature and package type.
0.4
ns
Document #: 38-07348 Rev. *B
See Figure 10
ns
Page 4 of 9
COMLINK™ SERIES
CY2CC910
AC Switching Characteristics @ 1.8V VDD = 1.8V ±5%, Temperature = –40°C to +85°C
Parameter
tPLH
tPHL
tR
tF
tSK(0)
tSK(p)
tSK(t)
Description
Propagation Delay – Low to High
Propagation Delay – High to Low
Output Rise Time 20 – 80%
Output Fall Time 20 – 80%
Output Skew: Skew between outputs of the same package (in phase).
Pulse Skew: Skew between opposite transitions of the same output (tPHL
– tPLH).
Package Skew: Skew between outputs of different packages at the same
power supply voltage, temperature and package type.
Min. Typ. Max. Unit
1.5
2.7 3.5
ns
1.5
2.7 3.5
ns
0.2
1.5
ns
0.2
1.5
ns
See Figure 10
0.2
ns
See Figure 9
0.2
ns
See Figure 7
See Figure 11
0.4
ns
Parameter Measurement Information: [email protected]
From Output
Under Test
From Output
Under Test
CL = 50 pF
CL = 3 pF
500 ohm
Figure 2. Load Circuit [3,4,5]
Figure 4. Point to Point Load Circuit[3,4,5]
0.8VDD
tw(50-50)
VDD/2
VDD/2
Input
0V
tPLH
500 ohm
Input
0.8VDD
VDD/2
VDD/2
tPHL
VDD/2
VDD/2
Output
0V
VOH
VOL
Figure 3. Voltage Waveforms Propagation Delay Times[6]
tw(20-80)
Input
0.8VDD
VDD/2
0V
Figure 5. Voltage Waveforms–Pulse Duration[4]
Parameter Measurement Information: [email protected]
From Output
Under Test
tw(50-50)
CL = 6 pF
Input
500 ohm
1.8V
0.9V
0.9V
0V
tw(20-80)
Input
Figure 6. Load Circuit [3,4,5]
1.8V
0.9V
0V
1.8V
0.9V
0.9V
Input
tPLH
Figure 8. Voltage Waveforms–Pulse Duration[4]
0V
tPHL
0.9V
Output
0.9V
VOH
VOL
Figure 7. Voltage Waveforms Propagation
Delay Times[6]
Notes:
3. CL includes probe and jig capacitance.
4. All input pulses are supplied by generators having the following characteristics: PRR < 100 MHz, Z0 = 50Ω, tR < 2.5 ns, tF < 2.5 ns.
5. The outputs are measured one at a time with one transition per measurement.
6. TPLH and TPHL are the same as tpd.
Document #: 38-07348 Rev. *B
Page 5 of 9
COMLINK™ SERIES
CY2CC910
3V
1.5V
INPUT
0V
tPHL
tPLH
VOH
1.5V
OUTPUT
VOL
tsk (P) =
l tPHL - tPLH l
Figure 9. Pulse Skew–tsk(p)
3V
1.5V
INPUT
0V
t PHL1
t PLH1
VOH
1.5V
OUTPUT 1
VOL
tsk (O)
tsk (O)
VOH
1.5V
OUTPUT 2
VOL
t PLH 2
t PLH 2
tsk (P) =
l t PLH2 - t PLH1 l or tPHL2 - t PHL1 l
Figure 10. Output Skew–tsk(0)
3V
1.5V
INPUT
0V
tPHL1
tPLH1
VOH
1.5V
PACKAGE 1 OUTPUT
tsk(t)
tsk(t)
VOL
VOH
1.5V
PACKAGE 2 OUTPUT
VOL
tPLH 2
tsk(t) =
tPLH 2
l tPLH2 - tPLH1 l or tPHL2 - tPHL1 l
Figure 11. Package Skew - tsk(t)
Document #: 38-07348 Rev. *B
Page 6 of 9
COMLINK™ SERIES
CY2CC910
Ordering Information
Part Number
CY2CC910SI
CY2CC910SIT
CY2CC910SC
CY2CC910SCT
CY2CC910OI
CY2CC910OIT
CY2CC910OC
CY2CC910OCT
Lead-free
CY2CC910OXI
CY2CC910OXIT
CY2CC910OXC
CY2CC910OXCT
Document #: 38-07348 Rev. *B
Package Type
20-pin SOIC
20-pin SOIC–Tape and Reel
20-pin SOIC
20-pin SOIC–Tape and Reel
20-pin SSOP
20-pin SSOP–Tape and Reel
20-pin SSOP
20-pin SSOP–Tape and Reel
Product Flow
Industrial, –40° to 85°C
Industrial, –40° to 85°C
Commercial, 0°C to 70°C
Commercial, 0°C to 70°C
Industrial, –40° to 85°C
Industrial, –40° to 85°C
Commercial, 0°C to 70°C
Commercial, 0°C to 70°C
20-pin SSOP
20-pin SSOP–Tape and Reel
20-pin SSOP
20-pin SSOP–Tape and Reel
Industrial, –40° to 85°C
Industrial, –40° to 85°C
Commercial, 0°C to 70°C
Commercial, 0°C to 70°C
Page 7 of 9
COMLINK™ SERIES
CY2CC910
Package Drawing and Dimensions
20-Lead (300-Mil) SOIC S5
PIN 1 ID
10
1
DIMENSIONS IN INCHES [MM] MIN.
MAX.
0.291[7.391]
0.300[7.620]
*
0.394[10.007]
0.419[10.642]
REFERENCE JEDEC MO-119
PACKAGE WEIGHT 0.55 gms
11
20
PART #
S20.3 STANDARD PKG.
SZ20.3 LEAD FREE PKG.
0.026[0.660]
0.032[0.812]
SEATING PLANE
0.497[12.623]
0.513[13.030]
0.092[2.336]
0.105[2.667]
0.050[1.270]
TYP.
*
0.013[0.330]
0.019[0.482]
*
0.004[0.101]
0.004[0.101]
0.0118[0.299]
0.015[0.381]
0.050[1.270]
0.0091[0.231]
0.0125[0.317]
51-85024-*B
20-pin Shrunk Small Outline Package O20
51-85077-*C
VOI is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks
of their respective holders.
Document #: 38-07348 Rev. *B
Page 8 of 9
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
COMLINK™ SERIES
CY2CC910
Document History Page
Document Title: CY2CC910 COMLINKTM SERIES 1:10 Clock Fanout Buffer
Document #: 38-07348
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
114318
05/10/02
TSM
New Data Sheet
*A
119148
10/07/02
RGL
Added 5.8 as the Max. value for VIH in the DC Electrical Characteristics
@3.3V table.
Changed the Max. value of VIH from 5.8 to 5.0 in the DC Electrical Characteristics @2.5V table.
Changed the value of VIH from VDD+0.3 [2.25] to 4.3 in the DC Electrical
Characteristics @1.8V table.
*B
404287
See ECN
RGL
Added Lead-free devices for SSOP
Document #: 38-07348 Rev. *B
Page 9 of 9