CY29973 3.3V 125-MHz Multi-Output Zero Delay Buffer Features Table 1. Frequency Table[1] • Output Frequency up to 125 MHz VC0_SEL FB_SEL2 FB_SEL1 FB_SEL0 FVC0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 8x 12x 16x 20x 16x 24x 32x 40x 4x 6x 8x 10x 8x 12x 16x 20x • 12 Clock Outputs: Frequency Configurable • 350-ps max. Output to Output Skew • Configurable Output Disable • Two Reference Clock Inputs for Dynamic Toggling • Oscillator or PECL Reference Input • Spread Spectrum Compatible • Glitch-free Output Clocks Transitioning • 3.3V Power Supply • Pin Compatible with MPC973 • Industrial Temp. Rang: –40°C to +85°C • 52-Pin TQFP Package Block Diagram Pin Configuration D Q TCLK0 TCLK1 Phase Detector 0 1 0 1 VCO Sync Frz QA0 QA1 LPF TCLK_SEL QA2 QA3 FB_IN D Q Sync Frz QB0 QB1 QB2 FB_SEL2 QB3 MR#/OE Power-On Reset SELA(0,1) D Q Sync Frz D Q Sync Frz /4, /6, /8, /12 2 2 2 FB_SEL(0,1) 2 QC1 /4, /6, /8, /10 /2, /4, /6, /8 /4, /6, /8, /10 /2 0 1 D Q Sync Frz FB_OUT SCLK Data Generator D Q Sync Frz SYNC Output Disable Circuitry 1 2 3 4 5 6 7 8 9 10 11 12 13 CY29973 39 38 37 36 35 34 33 32 31 30 29 28 27 VSS QB0 VDDC QB1 VSS QB2 VDDC QB3 FB_IN VSS FB_OUT VDDC FB_SEL0 14 15 16 17 18 19 20 21 22 23 24 25 26 QC2 QC3 Sync Pulse SDATA QC0 52 51 50 49 48 47 46 45 44 43 42 41 40 VSS MR#/OE SCLK SDATA FB_SEL2 PLL_EN REF_SEL TCLK_SEL TCLK0 TCLK1 PECL_CLK PECL_CLK# VDD FB_SEL1 SYNC VSS QC0 VDDC QC1 SELC0 SELC1 QC2 VDDC QC3 VSS INV_CLK SELB(0,1) SELC(0,1) SELB1 SELB0 SELA1 SELA0 QA3 VDDC QA2 VSS QA1 VDDC QA0 VSS VCO_SEL PECL_CLK PECL_CLK# VCO_SEL PLL_EN REF_SEL 12 INV_CLK Note: 1. x = the reference input frequency, 200 MHz < FVCO < 480 MHz. Cypress Semiconductor Corporation Document #: 38-07291 Rev. *B • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised January 19, 2004 CY29973 Pin Description[2] Pin Name PWR I/O Type Description 11 PECL_CLK I PU PECL Clock Input. 12 PECL_CLK# I PD PECL Clock Input. 9 TCLK0 I PU External Reference/Test Clock Input. 10 TCLK1 I PU External Reference/Test Clock Input. 44, 46, 48, 50 QA(3:0) VDDC O Clock Outputs. See Table 2 on page 3 for frequency selections. 32, 34, 36, 38 QB(3:0) VDDC O Clock Outputs. See Table 2 on page 3 for frequency selections. 16, 18, 21, 23 QC(3:0) VDDC O Clock Outputs. See Table 2 on page 3 for frequency selections. 29 FB_OUT VDDC O Feedback Clock Output. Connect to FB_IN for normal operation. The divider ratio for this output is set by FB_SEL(0:2). See Table 1 on page 1. A bypass delay capacitor at this output will control Input Reference/ Output Banks phase relationships. 25 SYNC VDDC O Synchronous Pulse Output. This output is used for system synchronization. The rising edge of the output pulse is in sync with both the rising edges of QA (0:3) and QC(0:3) output clocks regardless of the divider ratios selected. 42, 43 SELA(1,0) I PU Frequency Select Inputs. These inputs select the divider ratio at QA(0:3) outputs. See Table 2 on page 3. 40, 41 SELB(1,0) I PU Frequency Select Inputs. These inputs select the divider ratio at QB(0:3) outputs. See Table 2 on page 3. 19, 20 SELC(1,0) I PU Frequency Select Inputs. These inputs select the divider ratio at QC(0:3) outputs. See Table 2 on page 3. 5, 26, 27 FB_SEL(2:0) I PU Feedback Select Inputs. These inputs select the divide ratio at FB_OUT output. See Table 1 on page 1. 52 VCO_SEL I PU VCO Divider Select Input. When set LOW, the VCO output is divided by 2. When set HIGH, the divider is bypassed. See Table 1 on page 1. 31 FB_IN I PU Feedback Clock Input. Connect to FB_OUT for accessing the PLL. 6 PLL_EN I PU PLL Enable Input. When asserted HIGH, PLL is enabled. When LOW, PLL is bypassed. 7 REF_SEL I PU Reference Select Input. When HIGH, the PECL inputs are selected. When LOW, TCLK[0:1] are selected. 8 TCLK_SEL I PU TCLK Select Input. When LOW, TCLK0 is selected. When HIGH TCLK1 is selected. 2 MR#/OE I PU Master Reset/Output Enable Input. When asserted LOW, resets all of the internal flip-flops and also disables all of the outputs. When pulled HIGH, releases the internal flip-flops from reset and enables all of the outputs. 14 INV_CLK I PU Inverted Clock Input. When set HIGH, QC(2,3) outputs are inverted. When set LOW, the inverter is bypassed. 3 SCLK I PU Serial Clock Input. Clocks data at SDATA into the internal register. 4 SDATA I PU Serial Data Input. Input data is clocked to the internal register to enable/disable individual outputs. This provides flexibility in power management. 17, 22, 28, 33,37, 45, 49 VDDC 13 VDD 1, 15, 24, 30, VSS 35, 39, 47, 51 3.3V Power Supply for Output Clock Buffers. 3.3V Supply for PLL. Common Ground. Note: 2. A bypass capacitor (0.1µF) should be placed as close as possible to each positive power (<0.2”). If these bypass capacitors are not close to the pins their high frequency filtering characteristics will be cancelled by the lead inductance of the traces. Document #: 38-07291 Rev. *B Page 2 of 8 CY29973 Description Zero Delay Buffer The CY29973 has an integrated PLL that provides low-skew and low-jitter clock outputs for high-performance microprocessors. Three independent banks of four outputs as well as an independent PLL feedback output, FB_OUT, provide exceptional flexibility for possible output configurations. The PLL is ensured stable operation given that the VCO is configured to run between 200 MHz to 480 MHz. This allows a wide range of output frequencies up to125 MHz. When used as a zero delay buffer the CY29973 will likely be in a nested clock tree application. For these applications the CY29973 offers a low voltage PECL clock input as a PLL reference. This allows the user to use LVPECL as the primary clock distribution device to take advantage of its far superior skew performance. The CY29973 then can lock onto the LVPECL reference and translate with near zero delay to low skew outputs. The phase detector compares the input reference clock to the external feedback input. For normal operation, the external feedback input, FB_IN, is connected to the feedback output, FB_OUT. The internal VCO is running at multiples of the input reference clock set by FB_SEL(0:2) and VCO_SEL select inputs, refer to Table 1. The VCO frequency is then divided down to provide the required output frequencies. These dividers are set by SELA(0,1), SELB(0,1), SELC(0,1) select inputs, see Table 2 below. For situations were the VCO needs to run at relatively low frequencies and hence might not be stable, assert VCO_SEL LOW to divide the VCO frequency by 2. This will maintain the desired output relationships, but will provide an enhanced PLL lock range. By using one of the outputs as a feedback to the PLL the propagation delay through the device is eliminated. The PLL works to align the output edge with the input reference edge thus producing a near zero delay. The reference frequency affects the static phase offset of the PLL and thus the relative delay between the inputs and outputs. Because the static phase offset is a function of the reference clock the Tpd of the CY29973 is a function of the configuration used. The CY29973 is also capable of providing inverted output clocks. When INV_CLK is asserted high, QC2 and QC3 output clocks are inverted. These clocks could be used as feedback outputs to the CY29973 or a second PLL device to generate early or late clocks for a specific design. This inversion does not affect the output to output skew. 1. Contain short or ÒruntÓ clock periods. These are clock cycles in which the cycle(s) are shorter in period than either the old or new frequency that is being transitioned to. Glitch-Free Output Frequency Transitions Customarily when output buffers have their internal counter’s changed “on the fly’ their output clock periods will: 2. Contain stretched clock periods. These are clock cycles in which the cycle(s) are longer in period than either the old or new frequency that is being transitioned to. This device specifically includes logic to guarantee that runt and stretched clock pulses do not occur if the device logic levels of any or all of the following pins changed “on the fly” while it is operating: SELA, SELB, SELC, and VCO_SEL. Table 2. Divider Table VCO_SEL SELA1 SELA0 QA SELB1 0 0 0 VCO/8 0 0 VCO/8 0 0 VCO/4 0 0 1 VCO/12 0 1 VCO/12 0 1 VCO/8 0 1 0 VCO/16 1 0 VCO/16 1 0 VCO/12 0 1 1 VCO/24 1 1 VCO/20 1 1 VCO/16 1 0 0 VCO/4 0 0 VCO/4 0 0 VCO/2 1 0 1 VCO/6 0 1 VCO/6 0 1 VCO/4 1 1 0 VCO/8 1 0 VCO/8 1 0 VCO/6 1 1 1 VCO/12 1 1 VCO/10 1 1 VCO/8 SYNC Output In situations were output frequency relationships are not integer multiples of each other the SYNC output provides a signal for system synchronization. The CY29973 monitors the relationship between the QA and the QC output clocks. It provides a low going pulse, one period in duration, one period prior to the coincident rising edges of the QA and QC outputs. Document #: 38-07291 Rev. *B SELB0 QB SELC1 SELC0 QC The duration and the placement of the pulse depend on the higher of the QA and QC output frequencies. The following timing diagram illustrates various waveforms for the SYNC output. Note that the SYNC output is defined for all possible combinations of the QA and QC outputs even though under some relationships the lower frequency clock could be used as a synchronizing signal. Page 3 of 8 CY29973 VCO 1:1 Mode QA QC SYNC 2:1 Mode QA QC SYNC 3:1 Mode QC QA SYNC 3:2 Mode QA QC SYNC 4:1 Mode QC QA SYNC 4:3 Mode QA QC SYNC 6:1 Mode QA QC SYNC Figure 1. Power Management The individual output enable/freeze control of the CY29973 allows the user to implement unique power management schemes into the design. The outputs are stopped in the logic ‘0’ state when the freeze control bits are activated. The serial input register contains one programmable freeze enable bit for 12 of the 14 output clocks. The QC0 and FB_OUT outputs can not be frozen with the serial port, this avoids any potential lock up situation should an error occur in the loading of the serial data. An output is frozen when a logic ‘0’ is programmed and Document #: 38-07291 Rev. *B enabled when a logic ‘1’ is written. The enabling and freezing of individual outputs is done in such a manner as to eliminate the possibility of partial “runt” clocks. The serial input register is programmed through the SDATA input by writing a logic ‘0’ start bit followed by 12 NRZ freeze enable bits. The period of each SDATA bit equals the period of the free running SCLK signal. The SDATA is sampled on the rising edge of SCLK. Page 4 of 8 CY29973 Start Bit D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0-D3 are the control bits for QA0-QA3, respectively D4-D7 are the control bits for QB0-QB3, respectively D8-D10 are the control bits for QC1-QC3, respectively D11 is the control bit for SYNC Figure 2. Document #: 38-07291 Rev. *B Page 5 of 8 CY29973 Maximum Input Current: ................................................± 20 mA Absolute Maximum Conditions [3] Operating Temperature: ................................ –40°C to +85°C This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: Maximum ESD protection ............................................... 2 kV VSS < (Vin or Vout) < VDD Maximum Power Supply: ................................................5.5V Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). Maximum Input Voltage Relative to VSS: ............ VSS – 0.3V Maximum Input Voltage Relative to VDD: ............. VDD + 0.3V Storage Temperature: ................................ –65°C to + 150°C DC Electrical Specifications VDD = 2.9V to 3.6V, VDDC = 3.3V ±10%, TA = –40°C to +85°C Min. Typ. Max. Unit VIL Parameter Input Low Voltage Description VSS – 0.8 V 2.0 – VDD VIH Input High Voltage VPP Peak-to-Peak Input Voltage PECL_CLK VCMR Common Mode Range PECL_CLK[4] Conditions 300 – 1000 V mV VDD – 2.0 – VDD – 0.6 V IIL Input Low Current[5] – – –120 µA IIH Input High Current[5] – – 120 µA – – 0.5 V 2.4 – – V Voltage[6] VOL Output Low VOH Output High Voltage[6] IOL = 20 mA IOH = –20 mA IDDQ Quiescent Supply Current – 10 15 mA IDDA PLL Supply Current VDD only – 15 20 mA IDD Dynamic Supply Current QA and QB @ 60 MHz, QC @ 120 MHz, CL=30 pF – 225 – mA QA and QB @ 25 MHz, QC @ 50 MHz, CL=30 pF – 125 – Cin Input Pin Capacitance – 4 – pF ZOUT Output Impedance 15 18 22 Ω AC Electrical Specifications VDD = 2.9V to 3.6V, VDDC = 3.3V ±10%, TA = –40°C to +85°C [7] Parameter Description Conditions Min. Typ. Max. Unit – 3.0 ns Note 8 – Note 8 MHz Tr/Tf TCLK Input Rise/Fall Fref Reference Input Frequency FrefDC Reference Input Duty Cycle 25 – 75 % Fvco PLL VCO Lock Range 200 – 480 MHz Tlock Maximum PLL lock Time Tr/Tf Output Clocks Rise/Fall Time[9] 0.8V to 2.0V Fout Maximum Output Frequency Q (÷2) – Q (÷4) – Q (÷6) – – 80 Q (÷8) – – 60 TCYCLE/2 – 750 – TCYCLE/2 + 750 FoutDC Output Duty Cycle[9] – – 10 ms 0.15 – 1.2 ns – 125 MHz – 120 ps Notes: 3. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 4. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the VCMR range and the input lies within the VPP specification. 5. Inputs have pull-up/pull-down resistors that effect input current. 6. Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines. 7. Parameters are guaranteed by design and characterization. Not 100% tested in production. 8. Maximum and minimum input reference is limited by VC0 lock range. 9. Outputs loaded with 30pF each. Document #: 38-07291 Rev. *B Page 6 of 8 CY29973 AC Electrical Specifications VDD = 2.9V to 3.6V, VDDC = 3.3V ±10%, TA = –40°C to +85°C (continued)[7] Parameter Description Time[9](all Conditions Min. Typ. Max. Unit tpZL, tpZH Output Enable outputs) 2 – 10 ns tpLZ, tpHZ Output Disable Time[9](all outputs) 2 – 8 ns TCCJ Cycle to Cycle Jitter[9](peak to peak) – ±100 – ps TSKEW Any Output to Any Output Skew[9,10] – 250 350 ps ps Propagation Delay[10,11] Tpd PECL_CLK TCLK0 QFB =(³8) TCLK1 –225 –25 175 –70 130 330 –130 70 270 Ordering Information Part Number Package Type Production Flow CY29973AI 52-pin TQFP Industrial, –40°C to +85°C CY29973AIT 52-pin TQFP Industrial, –40°C to +85°C Package Drawing and Dimensions 52-Lead Thin Plastic Quad Flat Pack (10 x 10 x 1.0 mm) A52B 51-85158-** Notes: 10. 50Ω transmission line terminated into VDD/2. 11. Tpd is specified for a 50MHz input reference. Tpd does not include jitter. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07291 Rev. *B Page 7 of 8 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY29973 Document History Page Document Title: CY29973 3.3V 125-MHz Multi-Output Zero Delay Buffer Document Number: 38-07291 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 111102 02/07/02 BRK New data sheet *A 122883 12/22/02 RBI Added power up requirements to Maximum Ratings *B 200081 See ECN RGL Added ZOUT specifications in the DC Electrical Specs Changed the Package Drawing and Dimension to CY standard Document #: 38-07291 Rev. *B Page 8 of 8