74VHC175 Quad D-Type Flip-Flop tm Features General Description ■ High Speed: fMAX = 210MHz (Typ.) at VCC = 5V ■ Low power dissipation: ICC = 4µA (Max.) at TA = 25°C The VHC175 is an advanced high-speed CMOS device fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. ■ High noise immunity: VNIH = VNIL = 28% VCC (Min.) ■ Power down protection is provided on all inputs ■ Low noise: VOLP = 0.8V (Max.) ■ Pin and function compatible with 74HC175 The VHC175 is a high-speed quad D-type flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW-to-HIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flipflops, independent of the Clock or D inputs, when LOW. An input protection circuit insures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages. Ordering Information Package Number Package Description 74VHC175M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74VHC175SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Order Number 74VHC175MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering number. Connection Diagram Pin Description Pin Names ©1993 Fairchild Semiconductor Corporation 74VHC175 Rev. 1.2 Description D0–D3 Data Inputs CP Clock Pulse Input MR Master Reset Input Q0–Q3 True Outputs Q0–Q 3 Complement Outputs www.fairchildsemi.com 74VHC175 Quad D-Type Flip-Flop May 2007 Functional Description The VHC175 consists of four edge-triggered D flip-flops with individual D inputs and Q and Q outputs. The Clock and Master Reset are common. The four flip-flops will store the state of their individual D inputs on the LOW-toHIGH clock (CP) transition, causing individual Q and Q outputs to follow. A LOW input on the Master Reset (MR) will force all Q outputs LOW and Q outputs HIGH independent of Clock or Data inputs. The VHC175 is useful for general logic applications where a common Master Reset and Clock are acceptable. Truth Table IEEE/IEC Inputs @ tn, MR = H Outputs @ tn+1 Dn Qn Qn L L H H H L H = HIGH Voltage Level L = LOW Voltage Level tn = Bit Time before Clock Pulse tn+1 = Bit Time after Clock Pulse Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©1993 Fairchild Semiconductor Corporation 74VHC175 Rev. 1.2 www.fairchildsemi.com 2 74VHC175 Quad D-Type Flip-Flop Logic Symbol Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Rating VCC Supply Voltage –0.5V to +7.0V VIN DC Input Voltage –0.5V to +7.0V VOUT DC Output Voltage –0.5V to VCC + 0.5V IIK Input Diode Current –20mA IOK Output Diode Current ±20mA IOUT DC Output Current ±25mA ICC DC VCC / GND Current TSTG TL ±50mA Storage Temperature –65°C to +150°C Lead Temperature (Soldering, 10 seconds) 260°C Recommended Operating Conditions(1) The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter VCC Supply Voltage VIN Input Voltage VOUT Output Voltage TOPR Operating Temperature tr , tf Rating 2.0V to +5.5V 0V to +5.5V 0V to VCC –40°C to +85°C Input Rise and Fall Time, VCC = 3.3V ± 0.3V 0ns/V ∼ 100ns/V VCC = 5.0V ± 0.5V 0ns/V ∼ 20ns/V Note: 1. Unused inputs must be held HIGH or LOW. They may not float. ©1993 Fairchild Semiconductor Corporation 74VHC175 Rev. 1.2 www.fairchildsemi.com 3 74VHC175 Quad D-Type Flip-Flop Absolute Maximum Ratings TA = –40°C to +85°C TA = 25°C Symbol Parameter VCC (V) VIH HIGH Level Input Voltage 2.0 Conditions Min. 1.50 3.0–5.5 0.7 x VCC VIL LOW Level Input Voltage VOH HIGH Level Output Voltage Max. 3.0 IOH = –50µA LOW Level Output Voltage 2.0 1.9 2.9 3.0 2.9 4.4 4.5 4.4 IOH = –4mA 2.58 2.48 4.5 IOH = –8mA 3.94 3.80 3.0 VIN = VIH or VIL IOL = 50µA 4.5 0.1 0.1 0.0 0.1 0.1 0.0 IOL = 8mA 4.5 V V 0.0 IOL = 4mA 3.0 V 0.3 x VCC 1.9 3.0 2.0 Units 0.50 0.3 x VCC VIN = VIH or VIL Max. 0.7 x VCC 0.50 3.0–5.5 2.0 Min. 1.50 2.0 4.5 VOL Typ. 0.1 0.1 0.36 0.44 V 0.36 0.44 IIN Input Leakage Current 0–5.5 VIN = 5.5V or GND ±0.1 ±1.0 µA ICC Quiescent Supply Current 5.5 VIN = VCC or GND 4.0 40.0 µA Noise Characteristics TA = 25°C Symbol VCC (V) Typ. Limits Units Quiet Output Maximum Dynamic VOL 5.0 0.4 0.8 V CL = 50pF VOLV(2) Quiet Output Minimum Dynamic VOL 5.0 –0.4 –0.8 V CL = 50pF VIHD(2) Minimum HIGH Level Dynamic Input Voltage 5.0 3.5 V CL = 50pF VILD(2) Maximum LOW Level Dynamic Input Voltage 5.0 1.5 V CL = 50pF VOLP (2) Parameter Conditions Note: 2. Parameter guaranteed by design. ©1993 Fairchild Semiconductor Corporation 74VHC175 Rev. 1.2 www.fairchildsemi.com 4 74VHC175 Quad D-Type Flip-Flop DC Electrical Characteristics TA = –40°C to +85°C TA = 25°C Symbol fMAX tPLH, tPHL tPLH, tPHL Parameter Maximum Clock Frequency Propagation Delay Time, (CP to Qn or Qn) Propagation Delay Time, (MR to Qn or Qn) tOSLH, tOSHL Output to Output Skew CIN Input Capacitance CPD Power Dissipation Capacitance VCC (V) Conditions Min. Typ. Max. Min. 3.3 ± 0.3 CL = 15pF 90 140 75 CL = 50pF 50 75 45 5.0 ± 0.5 CL = 15pF 150 210 125 CL = 50pF 85 115 75 Max. Units MHz MHz 3.3 ± 0.3 CL = 15pF 7.5 11.5 1.0 13.5 CL = 50pF 10.0 15.0 1.0 17.0 5.0 ± 0.5 CL = 15pF 4.8 7.3 1.0 8.5 CL = 50pF 6.3 9.3 1.0 10.5 3.3 ± 0.3 CL = 15pF 6.3 10.1 1.0 12.0 CL = 50pF 8.8 13.6 1.0 15.5 5.0 ± 0.5 CL = 15pF 4.3 6.4 1.0 7.5 CL = 50pF 5.8 8.4 1.0 9.5 3.3 ± 0.3 CL = 50pF 5.0 ± 0.5 CL = 50pF(3) VCC (4) = Open 4 1.5 1.5 1.0 1.0 10 10 44 ns ns ns ns pF pF Notes: 3. Parameter guaranteed by design. tOSLH = |tPLHmax – tPLHmin|; tOSHL =| tPHLmax – tPHLmin|. 4. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained from the equation: ICC (opr.) = CPD • VCC • fIN + ICC/4 (per F/F), and the total CPD when n pcs of the Flip-Flop operate can be calculated by the following equation: CPD (total) = 30 + 14 • n AC Operating Requirements TA = 25°C Symbol Parameter tW(L), tW(H) Minimum Pulse Width (CP) tW(L) tS tH tREC Minimum Pulse Width (MR) Minimum Setup Time (Dn to CP) Minimum Hold Time (Dn to CP) Minimum Removal Time (MR) VCC (V)(5) Typ. TA = –40°C to +85°C Guaranteed Minimum 3.3 5.0 5.0 5.0 5.0 5.0 3.3 5.0 5.0 5.0 5.0 5.0 3.3 5.0 5.0 5.0 4.0 4.0 3.3 1.0 1.0 5.0 1.0 1.0 3.3 5.0 5.0 5.0 5.0 5.0 Units ns ns ns ns ns Note: 5. VCC is 3.3 ± 0.3V or 5.0 ± 0.5V ©1993 Fairchild Semiconductor Corporation 74VHC175 Rev. 1.2 www.fairchildsemi.com 5 74VHC175 Quad D-Type Flip-Flop AC Electrical Characteristics 74VHC175 Quad D-Type Flip-Flop Physical Dimensions Dimensions are in millimeters unless otherwise noted. Figure 1. 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A ©1993 Fairchild Semiconductor Corporation 74VHC175 Rev. 1.2 www.fairchildsemi.com 6 74VHC175 Quad D-Type Flip-Flop Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 2. 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D ©1993 Fairchild Semiconductor Corporation 74VHC175 Rev. 1.2 www.fairchildsemi.com 7 5.00±0.10 4.55 5.90 4.45 7.35 0.65 4.4±0.1 1.45 5.00 0.11 12° MTC16rev4 Figure 3. 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 ©1993 Fairchild Semiconductor Corporation 74VHC175 Rev. 1.2 www.fairchildsemi.com 8 74VHC175 Quad D-Type Flip-Flop Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. ® ACEx Across the board. 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FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Definition Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I26 ©1993 Fairchild Semiconductor Corporation 74VHC175 Rev. 1.2 www.fairchildsemi.com 9 74VHC175 Quad D-Type Flip-Flop TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.