74VHC4040 12-Stage Binary Counter tm Features General Description ■ High speed; fMAX = 210MHz at VCC = 5V ■ Low power dissipation: ICC = 4µA (Max.) at TA = 25°C The VHC4040 is an advanced high-speed CMOS device fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The VHC4040 is a 12-stage counter which increments on the negative edge of the input clock and all outputs are reset to a low level by applying a logical high on the reset input. An input protection circuit insures that 0V to 7V can be applied to the inputs without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages. ■ High noise immunity: VNIH = VNIL = 28% VCC (Min.) ■ Power down protection is provided on all inputs ■ Wide operating voltage range: VCC (Opr.) = 2V – 5.5V ■ Low noise: VOLP = 0.8V (Max.) ■ Pin and function compatible with 74HC4040 Ordering Information Order Number 74VHC4040M 74VHC4040MTC Package Number Package Description M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering number. Connection Diagram Pin Descriptions Pin Names ©1993 Fairchild Semiconductor Corporation 74VHC4040 Rev. 1.3 Description Q0–Q11 Flip-Flop Outputs CP Negative Edged Triggered Clock MR Master Reset www.fairchildsemi.com 74VHC4040 12-Stage Binary Counter May 2007 74VHC4040 12-Stage Binary Counter Logic Symbols IEEE/IEC Logic Diagram ©1993 Fairchild Semiconductor Corporation 74VHC4040 Rev. 1.3 www.fairchildsemi.com 2 74VHC4040 12-Stage Binary Counter Timing Diagram ©1993 Fairchild Semiconductor Corporation 74VHC4040 Rev. 1.3 www.fairchildsemi.com 3 Symbol Parameter Rating VCC Supply Voltage –0.5V to +7.0V VIN DC Input Voltage –0.5V to +7.0V VOUT DC Output Voltage –0.5V to VCC + 0.5V IIK Input Diode Current –20mA IOK Output Diode Current ±20mA IOUT DC Output Current ±25mA ICC DC VCC / GND Current TSTG TL ±75mA Storage Temperature –65°C to +150°C Lead Temperature (Soldering, 10 seconds) 260°C Recommended Operating Conditions(1) The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter VCC Supply Voltage VIN Input Voltage VOUT Output Voltage TOPR Operating Temperature t r, t f Input Rise and Fall Time Rating 2.0V to +5.5V 0V to +5.5V 0V to VCC –40°C to +85°C VCC = 3.3V ±0.3V 0 ∼ 100ns/V VCC = 5.0V ±0.5V 0 ∼ 20ns/V Note: 1. Unused inputs must be held HIGH or LOW. They may not float. ©1993 Fairchild Semiconductor Corporation 74VHC4040 Rev. 1.3 www.fairchildsemi.com 4 74VHC4040 12-Stage Binary Counter Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. TA = –40°C to +85°C TA = 25°C Symbol Parameter VIH HIGH Level Input Voltage VIL LOW Level Input Voltage VOH HIGH Level Output Voltage VCC (V) Conditions Min. 2.0 1.50 3.0 – 5.5 0.7 x VCC 3.0 LOW Level Output Voltage IOH = –50µA Quiescent Supply Current ©1993 Fairchild Semiconductor Corporation 74VHC4040 Rev. 1.3 2.9 3.0 2.9 4.4 4.5 4.4 2.58 2.48 3.94 3.80 4.5 ICC 1.9 IOH = –8mA 3.0 Input Leakage Current 2.0 IOH = –4mA VIN = VIH or VIL IOL = 50µA IOL = 8mA V 0.0 0.1 0.1 0.0 0.1 0.1 0.0 IOL = 4mA V 0.3 x VCC 1.9 4.5 2.0 Units V 0.50 3.0 3.0 Max. 0.7 x VCC 0.3 x VCC VIN = VIH or VIL 4.5 IIN Min. 0.50 3.0 – 5.5 2.0 Max. 1.50 2.0 4.5 VOL Typ. 0.1 0.1 0.36 0.44 V 0.36 0.44 0 – 5.5 VIN = 5.5V or GND ±0.1 ±1.0 µA 5.5 VIN = VCC or GND 4.0 40.0 µA www.fairchildsemi.com 5 74VHC4040 12-Stage Binary Counter DC Electrical Characteristics TA = –40°C to +85°C TA = +25°C Symbol Parameter VCC (V) Conditions tPLH, tPHL Propagation Delay Time to Q1 3.3 ± 0.3 5.0 ± 0.5 tPLH, tPHL tPHL Propagation Delay Time between Stages from Qn to Qn+1 Propagation Delay Time MR–Qn 3.3 ± 0.3 Maximum Clock Frequency 5.0 ± 0.5 3.3 ± 0.3 3.3 ± 0.3 5.0 ± 0.5 CIN Input Capacitance CPD Power Dissipation Capacitance Typ. Max. Min. CL = 15pF 7.5 11.9 1.0 14.0 CL = 50pF 10.0 15.4 1.0 17.5 CL = 15pF 4.8 7.3 1.0 8.5 CL = 50pF 6.3 9.3 1.0 10.5 Max. Units CL = 15pF 2.4 4.4 1.0 5.0 CL = 50pF 1.6 3.1 1.0 3.5 CL = 15pF 8.3 12.8 1.0 15.0 CL = 50pF 10.8 16.3 1.0 18.5 CL = 15pF 5.6 8.6 1.0 10.0 CL = 50pF 7.1 10.6 1.0 12.0 CL = 15pF ns ns CL = 15pF 90 140 75 CL = 50pF 55 80 50 CL = 15pF 150 210 125 CL = 50pF 95 125 80 VCC (2) ns ns CL = 50pF 5.0 ± 0.5 fMAX Min. = Open 4 10 ns ns MHz MHz 10 21 pF pF Note: 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (Opr.) = CPD • VCC • fN + ICC AC Operating Requirements TA = 25°C Symbol Parameter tw(L), tw(H) Minimum Pulse Width (CP) tw(L) Minimum Pulse Width (MR) tREC Minimum Removal Time (MR) ©1993 Fairchild Semiconductor Corporation 74VHC4040 Rev. 1.3 VCC (V) Typ. TA = –40°C to +85°C Guaranteed Minimum 3.3 ± 0.3 5.0 5.0 5.0 ± 0.5 5.0 5.0 3.3 ± 0.3 5.0 5.0 5.0 ± 0.5 5.0 5.0 3.3 ± 0.3 5.0 5.0 5.0 ± 0.5 5.0 5.0 Units ns ns ns www.fairchildsemi.com 6 74VHC4040 12-Stage Binary Counter AC Electrical Characteristics 74VHC4040 12-Stage Binary Counter Physical Dimensions Dimensions are in millimeters unless otherwise noted. Figure 1. 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A ©1993 Fairchild Semiconductor Corporation 74VHC4040 Rev. 1.3 www.fairchildsemi.com 7 5.00±0.10 4.55 5.90 4.45 7.35 0.65 4.4±0.1 1.45 5.00 0.11 12° MTC16rev4 Figure 2. 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 ©1993 Fairchild Semiconductor Corporation 74VHC4040 Rev. 1.3 www.fairchildsemi.com 8 74VHC4040 12-Stage Binary Counter Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. ® ACEx Across the board. Around the world.™ ActiveArray™ Bottomless™ Build it Now™ CoolFET™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ DOME™ 2 E CMOS™ ® EcoSPARK EnSigna™ FACT Quiet Series™ ® FACT ® FAST FASTr™ FPS™ ® FRFET GlobalOptoisolator™ GTO™ HiSeC™ i-Lo™ ImpliedDisconnect™ IntelliMAX™ ISOPLANAR™ MICROCOUPLER™ MicroPak™ MICROWIRE™ Motion-SPM™ MSX™ MSXPro™ OCX™ OCXPro™ ® OPTOLOGIC ® OPTOPLANAR PACMAN™ PDP-SPM™ POP™ ® Power220 ® Power247 PowerEdge™ PowerSaver™ Power-SPM™ ® PowerTrench Programmable Active Droop™ ® QFET QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ RapidConnect™ ScalarPump™ SMART START™ ® SPM STEALTH™ SuperFET™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TCM™ ® The Power Franchise TinyBuck™ ® TinyLogic TINYOPTO™ TinyPower™ TinyWire™ TruTranslation™ µSerDes™ ® UHC UniFET™ VCX™ Wire™ ™ TinyBoost™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I27 ©1993 Fairchild Semiconductor Corporation 74VHC4040 Rev. 1.3 www.fairchildsemi.com 9 74VHC4040 12-Stage Binary Counter TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.