19-3232; Rev 0; 4/04 KIT ATION EVALU LE B A IL A AV Dual, 8-Bit, 165Msps, Current-Output DAC ♦ 2.7V to 3.6V Single Supply ♦ Full Output Swing and Dynamic Performance at 2.7V Supply ♦ Superior Dynamic Performance 67dBc SFDR at fOUT = 40MHz ♦ Programmable Channel Gain Matching ♦ Integrated 1.24V Low-Noise Bandgap Reference ♦ Single-Resistor Gain Control ♦ Interleaved Data Mode ♦ Single-Ended and Differential Clock Input Modes ♦ Miniature 40-Pin Thin QFN Package, 6mm x 6mm ♦ EV Kit Available—MAX5852 EV Kit Ordering Information PART TEMP RANGE PIN-PACKAGE 40 Thin QFN-EP* MAX5852ETL -40°C to +85°C *EP = Exposed paddle. REFO REFR AVDD OUTNB OUTPB AGND TOP VIEW OUTPA Pin Configuration OUTNA The MAX5852 is packaged in a 40-pin thin QFN with exposed paddle (EP) and is specified for the extended (-40°C to +85°C) temperature range. Pin-compatible, lower speed, and higher resolution versions are also available. Refer to the MAX5853 (10 bit, 80Msps), the MAX5851 (8 bit, 80Msps), and the MAX5854 (10 bit, 165Msps) data sheets for more information. See Table 4. ♦ Low Power 190mW with IFS = 20mA at fCLK = 165MHz AVDD The MAX5852 can operate in interleaved data mode to reduce the I/O pin count. This allows the converter to be updated on a single, 8-bit bus. The MAX5852 features digital control of channel gain matching to within ±0.4dB in sixteen 0.05dB steps. Channel matching improves sideband suppression in analog quadrature modulation applications. The onchip 1.24V bandgap reference includes a control amplifier that allows external full-scale adjustments of both channels through a single resistor. The internal reference can be disabled and an external reference may be applied for high-accuracy applications. The MAX5852 features full-scale current outputs of 2mA to 20mA and operates from a 2.7V to 3.6V single supply. The DAC supports three modes of power-control operation: normal, low-power standby, and complete power-down. In power-down mode, the operating current is reduced to 1µA. ♦ 8-Bit, 165Msps Dual DAC AGND The MAX5852 dual, 8-bit, 165Msps digital-to-analog converter (DAC) provides superior dynamic performance in wideband communication systems. The device integrates two 8-bit DAC cores, and a 1.24V reference. The MAX5852 supports single-ended and differential modes of operation. The dynamic performance is maintained over the entire 2.7V to 3.6V power-supply operating range. The analog outputs support a -1.0V to +1.25V compliance voltage. Features 40 39 38 37 36 35 34 33 32 31 30 CVDD DA7/PD 1 DA6/DACEN 2 DA5/IDE 3 28 CLK DA4/REN 4 27 CVDD Communications VSAT, LMDS, MMDS, WLAN, Point-to-Point Microwave Links DA3/G3 5 DA2/G2 6 DA1/G1 7 24 DCE Wireless Base Stations Quadrature Modulation Direct Digital Synthesis (DDS) Instrumentation/ATE DA0/G0 8 23 CW N.C. 9 22 N.C. N.C. 10 21 N.C. 29 CGND 26 CLKXN MAX5852 25 CLKXP DB0 DB1 DB2 DGND DB3 DVDD DB4 DB5 DB7 11 12 13 14 15 16 17 18 19 20 DB6 Applications EP THIN QFN ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX5852 General Description MAX5852 Dual, 8-Bit, 165Msps, Current-Output DAC ABSOLUTE MAXIMUM RATINGS AVDD to AGND ...................................................... -0.3V to +4V DVDD to DGND...................................................... -0.3V to +4V CVDD to CGND...................................................... -0.3V to +4V AVDD to DVDD .............................................................-4V to +4V AVDD to CVDD .............................................................-4V to +4V DVDD to CVDD .............................................................-4V to +4V AGND to DGND.....................................................-0.3V to +0.3V AGND to CGND.....................................................-0.3V to +0.3V DGND to CGND ....................................................-0.3V to +0.3V DA7–DA0, DB7–DB0, CW, DCE to DGND ...............-0.3V to +4V CLK to CGND ..........................................-0.3V to (CVDD + 0.3V) CLKXN, CLKXP to CGND.........................................-0.3V to +4V REFR, REFO to AGND .............................-0.3V to (AVDD + 0.3V) OUTPA, OUTNA to AGND ..........(AVDD - 4.8V) to (AVDD + 0.3V) OUTPB, OUTNB to AGND ..........(AVDD - 4.8V) to (AVDD + 0.3V) Maximum Current into Any Pin (excluding power supplies) ..........................................±50mA Continuous Power Dissipation (TA = +70°C) 40-Pin QFN (derate 26.3mW/°C above +70°C) .........2105mW Operating Temperature Range ..........................-40°C to +85°C Storage Temperature Range ..............................65°C to +150°C Junction Temperature ......................................................+150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 165Msps, differential clock, external reference, VREF = 1.2V, IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA ≥ +25°C guaranteed by production test. TA < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution N 8 Bits Integral Nonlinearity INL RL = 0 -0.25 ±0.05 +0.25 LSB Differential Nonlinearity DNL Guaranteed monotonic, RL = 0 -0.15 ±0.05 +0.15 LSB Offset Error VOS -0.1 ±0.02 +0.1 LSB Gain Error (See Also Gain Error Definition Section) GE Gain-Error Temperature Drift Internal reference (Note1) -10 ±1.5 +8 External reference -5.5 ±0.7 +5.0 Internal reference ±150 External reference ±100 %FSR ppm/°C DYNAMIC PERFORMANCE fCLK = 165MHz, AOUT = -1dBFS Spurious-Free Dynamic Range to Nyquist SFDR fCLK = 100MHz, AOUT = -1dBFS fCLK = 25MHz, AOUT = -1dBFS Spurious-Free Dynamic Range Within a Window Multitone Power Ratio to Nyquist 2 SFDR MTPR fOUT = 10MHz 64.3 67 fOUT = 20MHz 66 fOUT = 40MHz 67 fOUT = 10MHz 67 fOUT = 20MHz 67 fOUT = 30MHz 66 fOUT = 1MHz 64 fCLK = 165MHz, fOUT = 10MHz, AOUT = -1dBFS, span = 10MHz 68 fCLK = 100MHz, fOUT = 5MHz, AOUT = -1dBFS, span = 4MHz 70 fCLK = 25MHz, fOUT = 1MHz, AOUT = -1dBFS, span = 2MHz 67 8 tones at 400kHz spacing, fCLK = 78MHz, fOUT = 15MHz to 18.2MHz 63 _______________________________________________________________________________________ dBc dBc dBc Dual, 8-Bit, 165Msps, Current-Output DAC (AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 165Msps, differential clock, external reference, VREF = 1.2V, IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA ≥ +25°C guaranteed by production test. TA < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS 8 tones at 2.1MHz spacing, fCLK = 165MHz, fOUT = 28.3MHz to 45.2MHz, span = 50MHz Multitone Spurious-Free Dynamic Range Within a Window fCLK = 165MHz, AOUT = -1dBFS Total Harmonic Distortion to Nyquist (2nd- Through 8th-Order Harmonics Included) THD fCLK = 100MHz, AOUT = -1dBFS fCLK = 25MHz, AOUT = -1dBFS Output Channel-to-Channel Isolation fOUT = 10MHz Channel-to-Channel Gain Mismatch Channel-to-Channel Phase Mismatch Signal-to-Noise Ratio to Nyquist Maximum DAC Conversion Rate MIN SNR fDAC tS MAX 61 fOUT = 10MHz -71 fOUT = 20MHz -72 fOUT = 40MHz -72 fOUT = 10MHz -71 fOUT = 20MHz -74 fOUT = 30MHz -69 fOUT = 1MHz -69 UNITS dBc dBc 90 dB fOUT = 10MHz, G[3:0] = 1000 0.025 dB fOUT = 10MHz 0.05 Degrees fCLK = 165MHz, fOUT = 10MHz, IFS = 20mA 50.5 fCLK = 165MHz, fOUT = 10MHz, IFS = 5mA 50.5 fCLK = 65MHz, fOUT = 10MHz, IFS = 20mA 51 fCLK = 65MHz, fOUT = 10MHz, IFS = 5mA 51 Interleaved mode disabled, IDE = 0 165 200 Interleaved mode enabled, IDE = 1 82.5 100 Glitch Impulse Output Settling Time TYP dB Msps 5 pV•s ns To ±0.1% error band (Note 3) 12 Output Rise Time 10% to 90% (Note 3) 2.2 ns Output Fall Time 90% to 10% (Note 3) 2.2 ns ANALOG OUTPUT Full-Scale Output Current Range IFS Output Voltage Compliance Range Output Leakage Current Shutdown or standby mode 2 20 mA -1.00 +1.25 V -5 +5 µA 1.32 V REFERENCE Internal-Reference Output Voltage VREFO REN = 0 1.13 1.24 _______________________________________________________________________________________ 3 MAX5852 ELECTRICAL CHARACTERISTICS (continued) MAX5852 Dual, 8-Bit, 165Msps, Current-Output DAC ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 165Msps, differential clock, external reference, VREF = 1.2V, IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA ≥ +25°C guaranteed by production test. TA < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.) PARAMETER SYMBOL Internal-Reference Supply Rejection CONDITIONS MIN TYP MAX UNITS AVDD varied from 2.7V to 3.6V 0.5 mV/V REN = 0 ±50 ppm/°C Internal-Reference Output Drive Capability REN = 0 50 µA External-Reference Input Voltage Range REN = 1 Internal-Reference OutputVoltage Temperature Drift Current Gain TCVREFO 0.10 IFS/IREF 1.2 1.32 32 V mA/mA LOGIC INPUTS (DA7–DA0, DB7–DB0, CW) Digital Input-Voltage High VIH Digital Input-Voltage Low VIL Digital Input Current IIN Digital Input Capacitance CIN 0.65 x DVDD V -1 0.3 x DVDD V +1 µA 3 pF SINGLE-ENDED CLOCK INPUT/OUTPUT AND DCE INPUT (CLK, DCE) Digital Input-Voltage High VIH DCE = 1 Digital Input-Voltage Low VIL DCE = 1 Digital Input Current IIN DCE = 1 Digital Input Capacitance CIN DCE = 1 Digital Output-Voltage High VOH DCE = 0, ISOURCE = 0.5mA, Figure 1 Digital Output-Voltage Low VOL DCE = 0, ISINK = 0.5mA, Figure 1 0.65 x CVDD V -1 0.3 x CVDD V +1 µA 3 pF 0.9 x CVDD V 0.1 x CVDD V DIFFERENTIAL CLOCK INPUTS (CLKXP/CLKXN) Differential Clock Input Internal Bias Differential Clock Input Swing CVDD/2 V 5 kΩ 0.5 Clock Input Impedance Measured single ended V POWER REQUIREMENTS Analog Power-Supply Voltage AVDD 2.7 3 3.6 V Digital Power-Supply Voltage DVDD 2.7 3 3.6 V Clock Power-Supply Voltage CVDD 2.7 3 3.6 V 4 _______________________________________________________________________________________ Dual, 8-Bit, 165Msps, Current-Output DAC (AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 165Msps, differential clock, external reference, VREF = 1.2V, IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA ≥ +25°C guaranteed by production test. TA < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.) PARAMETER Analog Supply Current (Note 2) SYMBOL IAVDD MAX IFS = 20mA, single-ended clock mode 43.2 46 IFS = 20mA, differential clock mode 43.2 IFS = 2mA, differential clock mode 5 IFS = 20mA, single-ended clock mode 6 IFS = 20mA, differential clock mode 6 Single-ended clock mode (DCE = 1) 13.8 Differential clock mode (DCE = 0) 23.7 ISTANDBY IAVDD + IDVDD+ ICVDD 3.1 ISHDN IAVDD + IDVDD + ICVDD 1 Clock Supply Current (Note 2) ICVDD Total Power Dissipation (Note 2) TYP 5 IDVDD Total Shutdown Current MIN IFS = 2mA, single-ended clock mode Digital Supply Current (Note 2) Total Standby Current CONDITIONS PTOT Single-ended clock mode (DCE = 1) IFS = 20mA 190 IFS = 2mA 74 Differential clock mode (DCE = 0) IFS = 20mA 219 IFS = 2mA 104 Standby 9.3 Shutdown UNITS mA 6.9 16.5 3.7 mA mA mA µA 209 mW 11.1 0.003 TIMING CHARACTERISTICS (Figure 5, Figure 6) Propagation Delay 1 Single-ended clock mode (DCE = 1) 1.2 Differential clock mode (DCE = 0) 2.7 Single-ended clock mode (DCE = 1) 0.8 Differential clock mode (DCE = 0) -0.5 Clock cycles DAC Data to CLK Rise/Fall Setup Time (Note 4) tDCS DAC Data to CLK Rise/Fall Hold Time (Note 4) tDCH Control Word to CW Rise Setup Time tCS 2.5 ns Control Word to CW Rise Hold Time tCW 2.5 ns CW High Time tCWH 5 ns CW Low Time tCWL 5 ns DACEN = 1 to VOUT Stable Time (Coming Out of Standby) tSTB ns ns 3 µs _______________________________________________________________________________________ 5 MAX5852 ELECTRICAL CHARACTERISTICS (continued) MAX5852 Dual, 8-Bit, 165Msps, Current-Output DAC ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 165Msps, differential clock, external reference, VREF = 1.2V, IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA ≥ +25°C guaranteed by production test. TA < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.) PARAMETER SYMBOL PD = 0 to VOUT Stable Time (Coming Out of Power-Down) tSHDN Maximum Clock Frequency at CLKXP/CLKXN Input fCLK Clock High Time tCXH Clock Low Time CLKXP Rise to CLK Output Rise Delay CLKXP Fall to CLK Output Fall Delay Note 1: Note 2: Note 3: Note 4: CONDITIONS MIN TYP UNITS 500 µs 200 MHz CLKXP or CLKXN input 1.5 ns tCXL CLKXP or CLKXN input 1.5 ns tCDH DCE = 0 2.7 ns tCDL DCE = 0 2.7 ns 165 Including the internal reference voltage tolerance and reference amplifier offset. fDAC = 165Msps, fOUT = 10MHz. Measured single-ended with 50Ω load and complementary output connected to AGND. Guaranteed by design, not production tested. 0.5mA TO OUTPUT PIN 1.6V 5pF 0.5mA Figure 1. Load Test Circuit for CLK Outputs 6 MAX _______________________________________________________________________________________ Dual, 8-Bit, 165Msps, Current-Output DAC SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (fCLK = 100MHz) 0dBFS 70 75 75 55 -6dBFS 50 -12dBFS 65 SFDR (dBc) 60 60 55 -12dBFS 50 60 55 45 45 40 40 40 35 35 35 30 30 10 20 30 40 50 60 70 80 30 0 90 -6dBFS -12dBFS 50 45 0 0dBFS 70 65 SFDR (dBc) 10 15 20 25 30 35 40 45 50 5 0 2 4 6 8 10 12 14 fOUT (MHz) fOUT (MHz) SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (fCLK = 200MHz) SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (fCLK = 165MHz) SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (fCLK = 165MHz) 0dBFS -6dBFS 70 80 75 80 IFS = 10mA 70 55 -12dBFS 50 65 60 SFDR (dBc) SFDR (dBc) 60 IFS = 5mA 55 IFS = 20mA 50 60 45 40 40 40 35 35 35 30 30 30 0 10 20 30 40 50 60 70 90 0 10 20 30 75 70 0 -10 60 55 50 -30 -60 40 -80 35 -90 30 -100 35 60 70 80 90 -50 -70 10 60 85 fOUT1 fOUT2 -40 45 TEMPERATURE (°C) fOUT1 = 4.8541MHz, fOUT2 = 5.0555MHz -20 AMPLITUDE (dBm) 65 -15 50 TWO-TONE INTERMODULATION DISTORTION (fCLK = 165MHz, 2.5MHz WINDOW) MAX5852 toc07 80 40 fOUT (MHz) SPURIOUS-FREE DYNAMIC RANGE vs. TEMPERATURE (fCLK = 165MHz) SFDR (dBc) 80 fOUT (MHz) fOUT (MHz) -40 AVDD = DVDD = CVDD = 2.7V 50 45 10 20 30 40 50 60 70 80 90 100 AVDD = DVDD = CVDD = 3V 55 45 0 AVDD = DVDD = CVDD = 3.3V 70 65 65 AVDD = DVDD = CVDD = 3.6V 75 MAX5852 toc08 75 MAX5852 toc04 80 MAX5852 toc06 fOUT (MHz) MAX5852 toc05 SFDR (dBc) -6dBFS 70 65 SFDR (dBc) 0dBFS 80 MAX5852 toc02 75 80 MAX5852 toc01 80 SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (fCLK = 25MHz) MAX5852 toc03 SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (fCLK = 165MHz) 2fOUT2 - fOUT1 2fOUT1 - fOUT2 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 6.0 fOUT (MHz) _______________________________________________________________________________________ 7 MAX5852 Typical Operating Characteristics (AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, external reference, differential clock, IFS = 20mA, differential output, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, external reference, differential clock, IFS = 20mA, differential output, TA = +25°C, unless otherwise noted.) SINGLE-TONE SFDR (fCLK = 165MHz, 10MHz WINDOW) fT6 -40 fT2 fT7 -50 fT8 fT1 -60 -20 -40 -50 -60 -30 -40 -50 -60 -70 -70 -80 -80 -90 -90 -90 -100 -100 -100 11.7 -70 -80 4 21.7 31.7 41.7 51.7 61.7 fOUT (MHz) fT5 = 38.7002MHz fT1 = 28.3667MHz fT6 = 41.0333MHz fT2 = 30.3667MHz fT7 = 43.2000MHz fT3 = 32.7001MHz fT8 = 45.3667MHz fT4 = 34.5333MHz 5 6 7 8 9 10 11 12 13 14 fOUT = 0.9667MHz AOUT = -1dBFS 3.8 4.8 4.3 SINGLE-TONE SFDR (fCLK = 165MHz, NYQUIST WINDOW) 0 -10 -20 -30 -30 AMPLITUDE (dBm) -40 -50 -60 -70 -80 fOUT = 9.9159MHz AOUT = -1dBFS -40 -50 -60 -70 -80 -90 -100 -90 -110 -100 -120 0.1 0.5 0.9 1.3 1.7 8.25MHz/div 0.5 2.1 fOUT (MHz) fOUT (MHz) INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE 0.10 MAX5852 toc14 0.20 0.15 0.08 0.05 0.05 0.03 DNL (LSB) 0.10 0 0 -0.05 -0.03 -0.10 -0.05 -0.15 -0.08 -0.20 82.5 MAX5852 toc15 AMPLITUDE (dBm) -20 INL (LSB) 3.3 -0.10 0 32 64 96 128 160 192 224 256 DIGITAL INPUT CODE 5.3 fOUT (MHz) MAX5852 toc12 0 -10 2.8 fOUT (MHz) SINGLE-TONE SFDR (fCLK = 25MHz, 2MHz WINDOW) 8 -20 -30 MAX5852 toc13 fT3 fOUT = 4.8667MHz AOUT = -1dBFS -10 AMPLITUDE (dBm) -30 0 MAX5852 toc10 -20 fOUT = 9.1667MHz AOUT = -1dBFS -10 AMPLITUDE (dBm) fT5 fT4 0 MAX5852 toc09 0 -10 SINGLE-TONE SFDR (fCLK = 100MHz, 4MHz WINDOW) MAX5852 toc11 EIGHT-TONE SFDR PLOT (fCLK = 165MHz, 50MHz WINDOW) AMPLITUDE (dBm) MAX5852 Dual, 8-Bit, 165Msps, Current-Output DAC 0 32 64 96 128 160 192 224 256 DIGITAL INPUT CODE _______________________________________________________________________________________ 5.8 6.3 6.8 Dual, 8-Bit, 165Msps, Current-Output DAC POWER DISSIPATION vs. SUPPLY VOLTAGES (fCLK = 165MHz, fOUT = 10MHz) DIFFERENTIAL CLOCK DRIVE 190 180 SINGLE-ENDED CLOCK DRIVE 220 210 200 190 170 150 160 70 95 120 1.21460 1.21450 1.21440 1.21430 1.21420 1.21410 2.70 170 145 1.21470 2.85 3.00 3.15 3.30 3.45 1.21400 2.70 3.60 2.85 SUPPLY VOLTAGES (V) fCLK (MHz) REFERENCE VOLTAGE vs. TEMPERATURE 3.00 3.15 3.30 3.45 3.60 SUPPLY VOLTAGES (V) DYNAMIC RESPONSE RISE TIME MAX5852 toc20 1.220 MAX5852 toc19 45 1.218 REFERENCE VOLTAGE (V) 20 SINGLE-ENDED CLOCK DRIVE 180 160 1.21480 1.216 1.214 100mV/div 1.212 1.210 1.208 1.206 1.204 -40 -15 10 35 60 10ns/div 85 TEMPERATURE (°C) SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (fCLK = 165MHz) DYNAMIC RESPONSE FALL TIME MAX5852 toc21 80 MAX5852 toc22 170 230 75 0dBFS 70 65 100mV/div SFDR (dBc) 200 DIFFERENTIAL CLOCK DRIVE REFERENCE VOLTAGE (V) 210 240 1.21490 MAX5852 toc17 250 POWER DISSIPATION (mW) 220 POWER DISSIPATION (mW) 260 MAX5852 toc16 230 REFERENCE VOLTAGE vs. SUPPLY VOLTAGES MAX5852 toc18 POWER DISSIPATION vs. CLOCK FREQUENCY (fOUT = 10MHz, AOUT = 0dBFS) 60 55 50 -6dBFS -12dBFS 45 40 SINGLE-ENDED CLOCK DRIVE 35 30 10ns/div 0 10 20 30 40 50 60 70 80 90 fOUT (MHz) _______________________________________________________________________________________ 9 MAX5852 Typical Operating Characteristics (continued) (AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, external reference, differential clock, IFS = 20mA, differential output, TA = +25°C, unless otherwise noted.) Dual, 8-Bit, 165Msps, Current-Output DAC MAX5852 Pin Description PIN NAME 1 DA7/PD 2 3 FUNCTION Channel A Input Data Bit 7 (MSB)/Power-Down DA6/DACEN Channel A Input Data Bit 6/DAC Enable Control DA5/IDE Channel A Input Data Bit 5/Interleaved Data Enable 4 DA4/REN Channel A Input Data Bit 4/Reference Enable. Setting REN = 0 enables the internal reference. Setting REN = 1 disables the internal reference. 5 DA3/G3 Channel A Input Data Bit 3/Channel A Gain Adjustment Bit 3 6 DA2/G2 Channel A Input Data Bit 2/Channel A Gain Adjustment Bit 2 7 DA1/G1 Channel A Input Data Bit 1/Channel A Gain Adjustment Bit 1 Channel A Input Data Bit 0 (LSB)/Channel A Gain Adjustment Bit 0 8 DA0/G0 9, 10, 21, 22 N.C. No Connection. Do not connect to these pins. 11 DB7 Channel B Input Data Bit 7 (MSB) 12 DB6 Channel B Input Data Bit 6 13 DB5 Channel B Input Data Bit 5 14 DB4 Channel B Input Data Bit 4 15 DB3 16 DVDD Digital Power Input. See the Power Supplies, Bypassing, Decoupling, and Layout section for more details. 17 DGND Digital Ground 18 DB2 Channel B Input Data Bit 2 19 DB1 Channel B Input Data Bit 1 20 DB0 Channel B Input Data Bit 0 (LSB) 23 CW Active-Low Control Word Write Pulse. The control word is latched on the rising edge of CW. 24 DCE Active-Low Differential Clock Enable Input. Drive DCE low to enable differential clock inputs CLKXP and CLKXN. Drive DCE high to disable the differential clock inputs and enable the singleended CLK input. 25 CLKXP Positive Differential Clock Input. With DCE = 0, CLKXP and CLKXN are enabled. With DCE = 1, CLKXP and CLKXN are disabled. Connect CLKXP to CGND when the differential clock is disabled. 26 CLKXN Negative Differential Clock Input. With DCE = 0, CLKXP and CLKXN are enabled. With DCE = 1, CLKXP and CLKXN are disabled. Connect CLKXN to CVDD when the differential clock is disabled. 27, 30 CVDD Clock Power Input. See the Power Supplies, Bypassing, Decoupling, and Layout section for more details. 28 CLK Single-Ended Clock Input/Output. With the differential clock disabled (DCE = 1), CLK becomes a singleended conversion clock input. With the differential clock enabled (DCE = 0), CLK is a single-ended output that mirrors differential clock inputs CLKXP and CLKXN. See the Clock Modes section for more information on CLK. 29 CGND Clock Ground 31 REFO Reference Input/Output. REFO serves as a reference input when the internal reference is disabled. If the internal 1.24V reference is enabled, REFO serves as an output for the internal reference. When the internal reference is enabled, bypass REFO to AGND with a 0.1µF capacitor. 10 Channel B Input Data Bit 3 ______________________________________________________________________________________ Dual, 8-Bit, 165Msps, Current-Output DAC PIN NAME FUNCTION 32 REFR Full-Scale Current Adjustment. To set the output full-scale current, connect an external resistor RSET between REFR and AGND. The output full-scale current is equal to 32 x VREFO/RSET. 33, 39 AVDD Analog Power Input. See the Power Supplies, Bypassing, Decoupling, and Layout section for more details. 34 OUTNB Channel B Negative Analog Current Output 35 OUTPB Channel B Positive Analog Current Output 36, 40 AGND Analog Ground 37 OUTNA Channel A Negative Analog Current Output 38 OUTPA — EP Channel A Positive Analog Current Output Exposed Paddle. Connect EP to the common point of all ground planes. Detailed Description DVDD DGND ANALOG POWER MANAGEMENT DIGITAL POWER MANAGEMENT AVDD AGND CW MAX5852 DA1/G1 DA2/G2 DA3/G3 DA4/REN DA5/IDE DA6/DACEN DACA INPUT REGISTER CONTROL WORD DA0/G0 INPUT DATA INTERLEAVER DB4 DB5 DB6 DACB INPUT REGISTER DB3 The MAX5852 features three modes of operation: normal, standby, and power-down (Table 2). These modes allow efficient power management. In power-down, the MAX5852 consumes only 1µA of supply current. Wake-up time from standby mode to normal DAC operation is 3µs. IDE OPERATING MODE CONTROLLER DB0 DB2 G0 G1 G2 G3 CHANNEL A GAIN CONTROL DA7/PD DB1 OUTPA OUTNA 8-BIT DACA DACEN PD Programming the DAC OUTPB OUTNB 8-BIT DACB DB7 DCE CLKXP CLKXN CLK CVDD CGND The MAX5852 dual, high-speed, 8-bit, current-output DAC provides superior performance in communication systems requiring low-distortion analog-signal reconstruction. The MAX5852 combines two DACs and an onchip 1.24V reference (Figure 2). The current outputs of the DACs can be configured for differential or singleended operation. The full-scale output current range is adjustable from 2mA to 20mA to optimize power dissipation and gain control. The MAX5852 accepts an input data and a DAC conversion rate of 165MHz. The inputs are latched on the rising edge of the clock whereas the output latches on the following rising edge. REFO CLOCK DISTRIBUTION 1.24V REFERENCE AND CONTROL AMPLIFIER CLOCK POWER MANAGEMENT REN REFR RSET AGND An 8-bit control word routed through channel A’s data port programs the gain matching, reference, and the operational mode of the MAX5852. The control word is latched on the rising edge of CW. CW is independent of the DAC clock. The DAC clock can always remain running, when the control word is written to the DAC. Table 1 and Table 2 represent the control word format and function. The gain on channel A can be adjusted to achieve gain matching between two channels in a user’s system. The gain on channel A can be adjusted from -0.4dB to +0.35dB in steps of 0.05dB by using bits G3 to G0 (see Table 3). Figure 2. Simplified Diagram ______________________________________________________________________________________ 11 MAX5852 Pin Description (continued) MAX5852 Dual, 8-Bit, 165Msps, Current-Output DAC Table 1. Control Word Format and Function MSB LSB PD DACEN REN IDE CONTROL WORD PD G2 G1 G0 FUNCTION Power-Down. The part enters power-down mode if PD = 1. DACEN DAC Enable. When DACEN = 0 and PD = 0, the part enters standby mode. IDE Interleaved Data Mode. IDE = 1 enables the interleaved data mode. In this mode, digital data for both channels is applied through channel A in a multiplexed fashion. Channel B data is written on the falling edge of the clock signal and channel A data is written on the rising edge of the clock signal. REN Reference Enable Bit. REN = 0 activates the internal reference. REN = 1 disables the internal reference and requires the user to apply an external reference between 0.1V to 1.32V. G3 Bit 3 (MSB) of Gain Adjust Word G2 Bit 2 of Gain Adjust Word G1 Bit 1 of Gain Adjust Word G0 Bit 0 (LSB) of Gain Adjust Word Table 2. Configuration Modes PD DACEN IDE REN Normal operation; noninterleaved inputs; internal reference active 0 1 0 0 Normal operation; noninterleaved inputs; internal reference disabled 0 1 0 1 Normal operation; interleaved inputs; internal reference disabled 0 Standby Power-down Power-up MODE 1 1 1 0 0 X X 1 X X X 0 1 X X Device Power-Up and States of Operation At power-up, the MAX5852’s default configuration is internal reference, noninterleaved input mode with a gain of 0dB and a fully operational converter. In shutdown, the MAX5852 consumes only 1µA of supply current, and in standby the current consumption is 3.1mA. Wake-up time from standby mode to normal operation is 3µs. Clock Modes X = Don’t care. Table 3. Gain Difference Setting 12 G3 GAIN ADJUSTMENT ON CHANNEL A (dB) G3 G2 G1 G0 +0.4 0 0 0 0 0 1 0 0 0 -0.35 1 1 1 1 The MAX5852 allows both single-ended CMOS and differential clock mode operation, and supports update rates of up to 165Msps. These modes are selected through an active-low control line called DCE. In singleended clock mode (DCE = 1), the CLK pin functions as an input, which accepts a user-provided single-ended clock signal. Data is written to the converter on the rising edge of the clock. The DAC outputs (previous data) are updated simultaneously on the same edge. If the DCE pin is pulled low, the MAX5852 will operate in differential clock mode. In this mode, the clock signal has to be applied to differential clock input pins CLKXP/CLKXN. The differential input accepts an input range of ≥0.5VP-P and a common-mode range of 1V to (CVDD - 0.5V), making the part ideal for low- input amplitude clock drives. CLKXP/CLKXN also help to minimize the jitter, and allow the user to connect a crystal oscillator directly to MAX5852. ______________________________________________________________________________________ Dual, 8-Bit, 165Msps, Current-Output DAC 10µF MAX4040 1.24V BANDGAP REFERENCE AGND 1.24V BANDGAP REFERENCE AVDD MAX6520 CCOMP* REFR CURRENTSOURCE ARRAY IREF IFS AGND IREF = EXTERNAL 1.2V REFERENCE REFR MAX5852 Figure 3. Setting IFS with the Internal 1.24V Reference and the Control Amplifier The CLK pin now becomes an output, and provides a single-ended replica of the differential clock signal, which may be used to synchronize the input data. Data is written to the device on the rising edge of the CLK signal. Internal Reference and Control Amplifier The MAX5852 provides an integrated 50ppm/°C, 1.24V, low-noise bandgap reference that can be disabled and overridden with an external reference voltage. REFO serves either as an external reference input or an integrated reference output. If REN =0, the internal reference is selected and REFO provides a 1.24V (50µA) output. Buffer REFO with an external amplifier, when driving a heavy load. The MAX5852 also employs a control amplifier designed to simultaneously regulate the full-scale output current (I FS ) for both outputs of the devices. Calculate the output current as: IFS = 32 ✕ IREF where I REF is the reference output current (I REF = VREFO / RSET) and IFS is the full-scale output current. R SET is the reference resistor that determines the amplifier output current of the MAX5852 (Figure 3). This current is mirrored into the current-source array where IFS is equally distributed between matched current segments and summed to valid output current readings for the DACs. CURRENTSOURCE ARRAY IREF IFS AGND RSET AGND *COMPENSATION CAPACITOR (CCOMP ≈ 100nF) REN = 1 REFO RSET RSET 0.1µF REN = 0 REFO VREF MAX5852 AVDD OPTIONAL EXTERNAL BUFFER FOR HEAVIER LOADS MAX5852 AGND Figure 4. MAX5852 with External Reference External Reference To disable the internal reference of the MAX5852, set REN = 1. Apply a temperature-stable, external reference to drive the REFO pin and set the full-scale output (Figure 4). For improved accuracy and drift performance, choose a fixed-output voltage reference such as the 1.2V, 25ppm/°C MAX6520 bandgap reference. Detailed Timing The MAX5852 accepts an input data and the DAC conversion rate of up to 165Msps. The input latches on the rising edge of the clock, whereas the output latches on the following rising edge. Figure 5 depicts the write cycle of the two DACs in noninterleaved mode. The MAX5852 can also operate in an interleaved data mode. Programming the IDE bit with a high level activates this mode (Tables 1 and 2). In interleaved mode, data for both DAC channels is written through input port A. Channel B data is written on the falling edge of the clock signal and then channel A data is written on the following rising edge of the clock signal. Both DAC outputs (channel A and B) are updated simultaneously on the next following rising edge of the clock. In interleaved data mode, the maximum input data rate per channel is half of the rate in noninterleaved mode. The interleaved data mode is attractive for applications where lower data rates are acceptable and interfacing on a single 8-bit bus is desired (Figure 6). ______________________________________________________________________________________ 13 MAX5852 Dual, 8-Bit, 165Msps, Current-Output DAC tCXH tCXL CLKXN CLKXP tCDL tCDH CLK OUTPUT tCWL CW tDCS DA0–DA7 DACA - 1 tCS tDCH DACA + 1 DACA tCW CONTROL WORD DACA + 2 DACA + 3 OUTNA DACA - 1 DACA DACA + 1 DACA + 2 XXXX (CONTROL WORD DATA) DACA + 3 OUTPA tDCS DB0–DB7 DACB - 1 tDCH DACB + 1 DACB DACB + 2 XXXX DACB + 3 OUTNB DACB - 1 DACB DACB + 1 DACB + 2 XXXX OUTPB Figure 5. Timing Diagram for Noninterleaved Data Mode (IDE = 0) tCXL tCXH CLKXN CLKXP tCDL tCDH CLK OUTPUT tCWL CW tDCS DA0–DA7 DACA tDCH DACB + 1 tDCS tDCH DACA + 1 tCS tCW CONTROL WORD DACB + 2 DACA + 2 OUTNA DACA - 1 DACA DACA + 1 DACB - 1 DACB DACB + 1 OUTPA OUTNB OUTPB Figure 6. Timing Diagram for Interleaved Data Mode (IDE = 1) 14 ______________________________________________________________________________________ DACB + 3 Dual, 8-Bit, 165Msps, Current-Output DAC AVDD DVDD CVDD 50Ω OUTPA DA0–DA7 MAX5852 AVDD DVDD CVDD VOUTA, SINGLE ENDED 50Ω DA0–DA7 1/2 OUTPA 1/2 100Ω MAX5852 8 MAX5852 8 OUTNA OUTNA 50Ω 50Ω OUTPB DB0–DB7 50Ω 50Ω VOUTB, SINGLE ENDED DB0–DB7 1/2 100Ω 8 MAX5852 8 OUTPB 1/2 MAX5852 OUTNB OUTNB 50Ω 50Ω AGND DGND CGND Figure 7. Application with Output Transformer (Coilcraft TTWB3010-1) Performing Differential-to-Single-Ended Conversion Applications Information Differential-to-Single-Ended Conversion The MAX5852 exhibits excellent dynamic performance to synthesize a wide variety of modulation schemes, including high-order QAM modulation with OFDM. Figure 7 shows a typical application circuit with output transformers performing the required differential-to-single-ended signal conversion. In this configuration, the MAX5852 operates in differential mode, which reduces even-order harmonics, and increases the available output power. Differential DC-Coupled Configuration Figure 8 shows the MAX5852 output operating in differential, DC-coupled mode. This configuration can be used in communications systems employing analog quadrature upconverters and requiring a baseband sampling, dual-channel, high-speed DAC for I/Q synthesis. In these applications, information bandwidth can AGND DGND CGND Figure 8. Application with DC-Coupled Differential Outputs extend from 10MHz down to several hundred kilohertz. DC-coupling is desirable to eliminate long discharge time constants that are problematic with large, expensive coupling capacitors. Analog quadrature upconverters have a DC common-mode input requirement of typically 0.7V to 1.0V. The MAX5852 differential I/Q outputs can maintain the desired full-scale level at the required 0.7V to 1.0V DC common-mode level when powered from a single 2.85V (±5%) supply. The MAX5852 meets this low-power requirement with minimal reduction in dynamic range while eliminating the need for level-shifting resistor networks. Power Supplies, Bypassing, Decoupling, and Layout Grounding and power-supply decoupling strongly influence the MAX5852 performance. Unwanted digital crosstalk can couple through the input, reference, power-supply, and ground connections, which can affect dynamic specifications, like signal-to-noise ratio ______________________________________________________________________________________ 15 MAX5852 Dual, 8-Bit, 165Msps, Current-Output DAC or spurious-free dynamic range. In addition, electromagnetic interference (EMI) can either couple into or be generated by the MAX5852. Observe the grounding and power-supply decoupling guidelines for highspeed, high-frequency applications. Follow the powersupply and filter configuration to realize optimum dynamic performance. Use of a multilayer printed circuit (PC) board with separate ground and power-supply planes is recommended. Run high-speed signals on lines directly above the ground plane. The MAX5852 has separate analog and digital ground buses (AGND, CGND, and DGND, respectively). Provide separate analog, digital, and clock ground sections on the PC board with only one point connecting the three planes. The ground connection points should be located underneath the device and connected to the exposed paddle. Run digital signals above the digital ground plane and analog/clock signals above the analog/clock ground plane. Digital signals should be kept away from sensitive analog, clock, and reference inputs. Keep digital signal paths short and metal trace lengths matched to avoid propagation delay and data skew mismatch. The MAX5852 includes three separate power-supply inputs: analog (AV DD ), digital (DV DD ), and clock (CVDD). Use a single linear regulator power source to branch out to three separate power-supply lines (AVDD, DV DD , CV DD ) and returns (AGND, DGND, CGND). Filter each power-supply line to the respective return line using LC filters comprising ferrite beads and 10µF capacitors. Filter each supply input locally with 0.1µF ceramic capacitors to the respective return lines. Note: To maintain the dynamic performance of the Electrical Characteristics, ensure the voltage difference between DV DD , AV DD , and CV DD does not exceed 150mV. Thermal Characteristics and Packaging Thermal Resistance 40-lead thin QFN-EP: θJA = 38°C/W The MAX5852 is packaged in a 40-pin thin QFN-EP package, providing greater design flexibility, increased thermal efficiency, and optimized AC performance of the DAC. The EP enables the implementation of grounding techniques, which are necessary to ensure highest performance operation. In this package, the data converter die is attached to an EP lead frame with the back of this frame exposed at the package bottom surface, facing the PC board side of the package. This allows a solid attachment of the package to the PC board with standard infrared (IR) flow soldering techniques. A specially created land pattern on the PC board, matching the size of the EP (4.1mm ✕ 4.1mm), ensures the proper attachment and grounding of the DAC. Designing vias* into the land area and implementing large ground planes in the PC board design allows for highest performance operation of the DAC. Use an array of 3 ✕ 3 vias (≤0.3mm diameter per via hole and 1.2mm pitch between via holes) for this 40-pin thin QFN-EP package (package code: T4066-1). Dynamic Performance Parameter Definitions Total Harmonic Distortion (THD) THD is the ratio of the RMS sum of all essential harmonics (within a Nyquist window) of the input signal to the fundamental itself. This can be expressed as: 2 2 2 2 V2 + V3 + V4 ... + ...VN THD = 20 × log V1 where V1 is the fundamental amplitude, and V2 through VN are the amplitudes of the 2nd through Nth order harmonics. The MAX5852 uses the first seven harmonics for this calculation. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio of RMS amplitude of the carrier frequency (maximum signal component) to the RMS value of their next-largest spectral component. SFDR is usually measured in dBc with respect to the carrier frequency amplitude or in dBFS with respect to the DAC’s full-scale range. Depending on its test condition, SFDR is observed within a predefined window or to Nyquist. Multitone Power Ratio (MTPR) A series of equally spaced tones are applied to the DAC with one tone removed from the center of the range. MTPR is defined as the worst-case distortion (usually a 3rd-order harmonic product of the fundamental frequencies), which appears as the largest spur at the frequency of the missing tone in the sequence. This test can be performed with any number of input tones; however, four and eight tones are among the most common test conditions for CDMA- and GSM/EDGE-type applications. *Vias connect the land pattern to internal or external copper planes. 16 ______________________________________________________________________________________ Dual, 8-Bit, 165Msps, Current-Output DAC Static Performance Parameter Definitions Integral Nonlinearity (INL) Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. For a DAC, the deviations are measured at every individual step. Differential Nonlinearity (DNL) Differential nonlinearity (DNL) is the difference between an actual step height and the ideal value of 1 LSB. A DNL error specification no more negative than -1 LSB guarantees monotonic transfer function. Offset Error Offset error is the current flowing from positive DAC output when the digital input code is set to zero. Offset error is expressed in LSBs. Gain Error A gain error is the difference between the ideal and the actual full-scale output current on the transfer curve, after nullifying the offset error. This error alters the slope of the transfer function and corresponds to the same percentage error in each step. The ideal current is defined by reference voltage at 32 x VREFO / RSET. Settling Time The settling time is the amount of time required from the start of a transition until the DAC output settles to its new output value to within the converter’s specified accuracy. Glitch Impulse A glitch is generated when a DAC switches between two codes. The largest glitch is usually generated around the midscale transition, when the input pattern transitions from 011…111 to 100…000. This occurs due to timing variations between the bits. The glitch impulse is found by integrating the voltage of the glitch at the midscale transition over time. The glitch impulse is usually specified in pV-s. Table 4. Part Selection Table PART SPEED (Msps) RESOLUTION MAX5851 80 8 bit, dual MAX5852 165 8 bit, dual MAX5853 80 10 bit, dual MAX5854 165 10 bit, dual Chip Information TRANSISTOR COUNT: 9035 PROCESS: CMOS ______________________________________________________________________________________ 17 MAX5852 Intermodulation Distortion (IMD) The two-tone IMD is the ratio expressed in dBc of either output tone to the worst 3rd-order (or higher) IMD products. Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) QFN THIN 6x6x0.8.EPS MAX5852 Dual, 8-Bit, 165Msps, Current-Output DAC D2 D CL D/2 b D2/2 k E/2 E2/2 (NE-1) X e E CL E2 k e L (ND-1) X e e L CL CL L1 L L e A1 A2 e A PACKAGE OUTLINE 36, 40, 48L THIN QFN, 6x6x0.8mm 21-0141 E 1 2 NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT FOR 0.4mm LEAD PITCH PACKAGE T4866-1. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. PACKAGE OUTLINE 36, 40, 48L THIN QFN, 6x6x0.8mm 21-0141 E 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.