1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 SST39SF010A / 020A / 0405.0V 1Mb / 2Mb / 4Mb (x8) MPF memories Data Sheet FEATURES: • Organized as 128K x8 / 256K x8 / 512K x8 • Single 4.5-5.5V Read and Write Operations • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Low Power Consumption (typical values at 14 MHz) – Active Current: 10 mA (typical) – Standby Current: 30 µA (typical) • Sector-Erase Capability – Uniform 4 KByte sectors • Fast Read Access Time: – 45 ns – 70 ns • Latched Address and Data • Fast Erase and Byte-Program – Sector-Erase Time: 18 ms (typical) – Chip-Erase Time: 70 ms (typical) – Byte-Program Time: 14 µs (typical) – Chip Rewrite Time: 2 seconds (typical) for SST39SF010A 4 seconds (typical) for SST39SF020A 8 seconds (typical) for SST39SF040 • Automatic Write Timing – Internal VPP Generation • End-of-Write Detection – Toggle Bit – Data# Polling • TTL I/O Compatibility • JEDEC Standard – Flash EEPROM Pinouts and command sets • Packages Available – 32-lead PLCC – 32-lead TSOP (8mm x 14mm) – 32-pin PDIP PRODUCT DESCRIPTION The SST39SF010A/020A/040 are CMOS Multi-Purpose Flash (MPF) manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39SF010A/020A/040 devices write (Program or Erase) with a 4.5-5.5V power supply. The SST39SF010A/020A/040 devices conform to JEDEC standard pinouts for x8 memories. Featuring high performance Byte-Program, the SST39SF010A/020A/040 devices provide a maximum Byte-Program time of 20 µsec. These devices use Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed typical endurance of 10,000 cycles. Data retention is rated at greater than 100 years. function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. To meet high density, surface mount requirements, the SST39SF010A/020A/040 are offered in 32-lead PLCC and 32-lead TSOP packages. A 600 mil, 32-pin PDIP is also available. See Figures 1, 2, and 3 for pin assignments. The SST39SF010A/020A/040 devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly improve performance and reliability, while lowering power consumption. They inherently use less energy during erase and program than alternative flash technologies. The total energy consumed is a ©2003 Silicon Storage Technology, Inc. S71147-06-000 8/04 1 The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet Device Operation is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase can be determined using either Data# Polling or Toggle Bit methods. See Figure 9 for timing waveforms. Any commands written during the SectorErase operation will be ignored. Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. Chip-Erase Operation The SST39SF010A/020A/040 provide Chip-Erase operation, which allows the user to erase the entire memory array to the “1s” state. This is useful when the entire device must be quickly erased. Read The Read operation of the SST39SF010A/020A/040 is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram (Figure 4) for further details. The Chip-Erase operation is initiated by executing a sixbyte Software Data Protection command sequence with Chip-Erase command (10H) with address 5555H in the last byte sequence. The internal Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the internal Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 10 for timing diagram, and Figure 18 for the flowchart. Any commands written during the ChipErase operation will be ignored. Byte-Program Operation The SST39SF010A/020A/040 are programmed on a byteby-byte basis. Before programming, the sector where the byte exists must be fully erased. The Program operation is accomplished in three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load byte address and byte data. During the ByteProgram operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed, within 20 µs. See Figures 5 and 6 for WE# and CE# controlled Program operation timing diagrams and Figure 15 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands written during the internal Program operation will be ignored. Write Operation Status Detection The SST39SF010A/020A/040 provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE# which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Sector-Erase Operation The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The sector architecture is based on uniform sector size of 4 KByte. The SectorErase operation is initiated by executing a six-byte command load sequence for Software Data Protection with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The sector address is latched on the falling edge of the sixth WE# pulse, while the command (30H) ©2003 Silicon Storage Technology, Inc. S71147-06-000 2 8/04 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet Data# Polling (DQ7) Software Data Protection (SDP) When the SST39SF010A/020A/040 are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs. During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Data# Polling timing diagram and Figure 16 for a flowchart. The SST39SF010A/020A/040 provide the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of a series of threebyte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte load sequence. The SST39SF010A/ 020A/040 devices are shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to read mode, within TRC. Product Identification The Product Identification mode identifies the device as the SST39SF040, SST39SF010A, or SST39SF020A and manufacturer as SST. This mode may be accessed by software operations. Users may wish to use the software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, Table 4 for software operation, Figure 11 for the software ID entry and read timing diagram and Figure 17 for the ID entry command sequence flowchart. Toggle Bit (DQ6) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 0s and 1s, i.e., toggling between 0 and 1. When the internal Program or Erase operation is completed, the toggling will stop. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector- or ChipErase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 8 for Toggle Bit timing diagram and Figure 16 for a flowchart. TABLE 1: PRODUCT IDENTIFICATION Address Data 0000H BFH SST39SF010A 0001H B5H SST39SF020A 0001H B6H SST39SF040 0001H B7H Manufacturer’s ID Data Protection Device ID The SST39SF010A/020A/040 provide both hardware and software features to protect nonvolatile data from inadvertent writes. T1.2 1147 Hardware Data Protection Product Identification Mode Exit/Reset Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle. In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Exit ID command sequence, which returns the device to the Read operation. Please note that the software reset command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 12 for timing waveform and Figure 17 for a flowchart. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 2.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. ©2003 Silicon Storage Technology, Inc. S71147-06-000 3 8/04 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet FUNCTIONAL BLOCK DIAGRAM SuperFlash Memory X-Decoder Memory Address Address Buffers & Latches Y-Decoder CE# I/O Buffers and Data Latches Control Logic OE# WE# DQ7 - DQ0 A4 A3 A17 WE# VDD A18 A16 A15 A12 A17 A4 NC A5 WE# A5 VDD A5 WE# 6 VDD A6 NC A6 NC A6 A16 5 A15 A7 A16 A7 A15 A7 A12 SST39SF020A SST39SF010A SST39SF040 SST39SF020A SST39SF010A A12 SST39SF040 1147 B1.2 4 3 2 1 32 31 30 29 SST39SF010A SST39SF020A SST39SF040 A14 A14 28 A13 A13 A13 7 27 A8 A8 A8 A4 8 26 A9 A9 A9 A3 A3 9 25 A11 A11 A11 A2 A2 A2 10 24 OE# OE# OE# A1 A1 A1 11 23 A10 A10 A10 A0 A0 A0 12 22 CE# CE# CE# DQ0 DQ0 DQ0 13 21 14 15 16 17 18 19 20 DQ7 DQ7 DQ7 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 DQ2 VSS DQ3 DQ4 DQ5 DQ6 32-lead PLCC Top View DQ1 SST39SF040 SST39SF020A SST39SF010A A14 1147 32-plcc P2.4 FIGURE 1: PIN ASSIGNMENTS FOR 32-LEAD PLCC ©2003 Silicon Storage Technology, Inc. S71147-06-000 4 8/04 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet SST39SF040 SST39SF020A A11 A9 A8 A13 A14 A17 WE# VDD A18 A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 A17 WE# VDD NC A16 A15 A12 A7 A6 A5 A4 SST39SF010A A11 A9 A8 A13 A14 NC WE# VDD NC A16 A15 A12 A7 A6 A5 A4 SST39SF010A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Standard Pinout Top View Die Up SST39SF020A OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 SST39SF040 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 1147 32-tsop P1.1 FIGURE 2: PIN ASSIGNMENTS FOR 32-LEAD TSOP (8MM X 14MM) SST39SF040 SST39SF020A SST39SF010A A18 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS SST39SF010A SST39SF020A 1 2 3 4 5 32-pin 6 PDIP 7 8 Top View 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD WE# NC A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VDD WE# A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 SST39SF040 VDD WE# A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 1147 32-pdip P3.2 FIGURE 3: PIN ASSIGNMENTS FOR 32-PIN PDIP ©2003 Silicon Storage Technology, Inc. S71147-06-000 5 8/04 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet TABLE 2: PIN DESCRIPTION Symbol Pin Name Functions AMS1-A0 Address Inputs To provide memory addresses. During Sector-Erase AMS-A12 address lines will select the sector. DQ7-DQ0 Data Input/output To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. CE# Chip Enable To activate the device when CE# is low. OE# Output Enable To gate the data output buffers. WE# Write Enable To control the Write operations. VDD Power Supply To provide 5.0V supply (4.5-5.5V) VSS Ground NC No Connection Unconnected pins. T2.2 1147 1. AMS = Most significant address AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040 TABLE 3: OPERATION MODES SELECTION Mode CE# OE# WE# Read Program DQ Address VIL VIL VIL VIH VIH DOUT AIN VIL DIN AIN X1 Sector address, XXH for Chip-Erase Erase VIL VIH VIL Standby VIH X X High Z X X VIL X High Z/ DOUT X X X VIH High Z/ DOUT X VIL VIL VIH Write Inhibit Product Identification Software Mode See Table 4 T3.3 1147 1. X can be VIL or VIH, but no other value. ©2003 Silicon Storage Technology, Inc. S71147-06-000 6 8/04 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet TABLE 4: SOFTWARE COMMAND SEQUENCE Command Sequence 1st Bus Write Cycle Addr1 Data 2nd Bus Write Cycle Addr1 Data 3rd Bus Write Cycle Addr1 4th Bus Write Cycle Data Addr1 Data Data 5th Bus Write Cycle 6th Bus Write Cycle Addr1 Data Addr1 Data Byte-Program 5555H AAH 2AAAH 55H 5555H A0H BA2 Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SAX3 30H 5555H AAH 2AAAH 55H 5555H 10H Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H Software ID Entry4,5 5555H AAH 2AAAH 55H 5555H 90H 2AAAH 55H 5555H F0H Software ID Exit6 XXH F0H Software ID Exit6 5555H AAH T4.2 1147 1. Address format A14-A0 (Hex), Addresses AMS-A15 can be VIL or VIH, but no other value, for the Command sequence. AMS = Most significant address AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040 2. BA = Program Byte address 3. SAX for Sector-Erase; uses AMS-A12 address lines 4. The device does not remain in Software Product ID mode if powered down. 5. With AMS-A1 = 0; SST Manufacturer’s ID = BFH, is read with A0 = 0, SST39SF010A Device ID = B5H, is read with A0 = 1 SST39SF020A Device ID = B6H, is read with A0 = 1 SST39SF040 Device ID = B7H, is read with A0 = 1 6. Both Software ID Exit operations are equivalent Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Through Hold Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA 1. Outputs shorted for no more than one second. No more than one output shorted at a time. OPERATING RANGE Range Commercial Industrial Ambient Temp VDD 0°C to +70°C 4.5-5.5V -40°C to +85°C 4.5-5.5V AC CONDITIONS OF TEST Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF for 45 ns Output Load . . . . . . . . . . . . . . . . . . . . . CL = 100 pF for 70 ns See Figures 13 and 14 ©2003 Silicon Storage Technology, Inc. S71147-06-000 7 8/04 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet TABLE 5: DC OPERATING CHARACTERISTICS VDD = 4.5-5.5V1 Limits Symbol Parameter IDD Power Supply Current Min Max Units Test Conditions Address input=VILT/VIHT, at f=1/TRC Min VDD=VDD Max Read2 25 mA CE#=VIL, OE#=WE#=VIH, all I/Os open Program and Erase 35 mA CE#=WE#=VIL, OE#=VIH ISB1 Standby VDD Current (TTL input) 3 mA CE#=VIH, VDD=VDD Max ISB2 Standby VDD Current (CMOS input) 100 µA CE#=VIHC, VDD=VDD Max ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max VIL Input Low Voltage 0.8 V VDD=VDD Min VIH Input High Voltage 2.0 V VDD=VDD Max VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max VOL Output Low Voltage VOH Output High Voltage 0.4 2.4 V IOL=2.1 mA, VDD=VDD Min V IOH=-400 µA, VDD=VDD Min T5.10 1147 1. Typical conditions for the Active Current shown on the front data sheet page are average values at 25°C (room temperature), and VDD = 5V for SF devices. Not 100% tested. 2. Values are for 70 ns conditions. See the Multi-Purpose Flash Power Rating application note for further information. TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol TPU-READ Parameter 1 TPU-WRITE1 Minimum Units Power-up to Read Operation 100 µs Power-up to Program/Erase Operation 100 µs T6.1 1147 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 7: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open) Parameter Description Test Condition Maximum CI/O1 I/O Pin Capacitance VI/O = 0V 12 pF Input Capacitance VIN = 0V 6 pF CIN 1 T7.0 1147 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 8: RELIABILITY CHARACTERISTICS Symbol NEND 1,2 Parameter Minimum Specification Units Endurance 10,000 Cycles JEDEC Standard A117 100 Years JEDEC Standard A103 100 + IDD mA JEDEC Standard 78 TDR1 Data Retention ILTH1 Latch Up Test Method T8.2 1147 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a higher minimum specification. ©2003 Silicon Storage Technology, Inc. S71147-06-000 8 8/04 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet AC CHARACTERISTICS TABLE 9: READ CYCLE TIMING PARAMETERS VDD = 4.5-5.5V SST39SF010A/020A/040-45 Symbol Parameter Min 45 Max SST39SF010A/020A/040-70 Min Max Units TRC Read Cycle Time TCE Chip Enable Access Time 45 70 ns TAA Address Access Time 45 70 ns TOE Output Enable Access Time 25 35 ns TCLZ1 TOLZ1 TCHZ1 TOHZ1 TOH1 CE# Low to Active Output 0 0 ns OE# Low to Active Output 0 0 ns 70 ns CE# High to High-Z Output 15 25 ns OE# High to High-Z Output 15 25 ns Output Hold from Address Change 0 0 ns T9.4 1147 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 10: PROGRAM/ERASE CYCLE TIMING PARAMETERS Symbol Parameter Min Max Units TBP Byte-Program Time TAS Address Setup Time 0 TAH Address Hold Time 30 ns TCS WE# and CE# Setup Time 0 ns TCH WE# and CE# Hold Time 0 ns TOES OE# High Setup Time 0 ns TOEH OE# High Hold Time 10 ns TCP CE# Pulse Width 40 ns TWP WE# Pulse Width 40 ns TWPH1 WE# Pulse Width High 30 ns TCPH1 CE# Pulse Width High 30 ns TDS Data Setup Time 40 ns TDH1 Data Hold Time 0 TIDA1 Software ID Access and Exit Time TSE Sector-Erase 25 ms TSCE Chip-Erase 100 ms 20 µs ns ns 150 ns T10.1 1147 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2003 Silicon Storage Technology, Inc. S71147-06-000 9 8/04 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet TAA TRC ADDRESS AMS-0 TCE CE# TOE OE# TOHZ TOLZ VIH WE# HIGH-Z DQ7-0 TCHZ TOH TCLZ HIGH-Z DATA VALID DATA VALID 1147 F03.1 Note: AMS = Most significant address AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040 FIGURE 4: READ CYCLE TIMING DIAGRAM INTERNAL PROGRAM OPERATION STARTS TBP 5555 TAH ADDRESS AMS-0 2AAA 5555 ADDR TDH TWP WE# TAS TDS TWPH OE# TCH CE# TCS DQ7-0 AA SW0 55 SW1 A0 SW2 DATA BYTE (ADDR/DATA) 1147 F04.1 Note: AMS = Most significant address AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040 FIGURE 5: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM ©2003 Silicon Storage Technology, Inc. S71147-06-000 10 8/04 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet INTERNAL PROGRAM OPERATION STARTS TBP 5555 TAH ADDRESS AMS-0 2AAA 5555 ADDR TDH TCP CE# TAS TDS TCPH OE# TCH WE# TCS DQ7-0 AA SW0 55 SW1 A0 SW2 DATA BYTE (ADDR/DATA) 1147 F05.1 Note: AMS = Most significant address AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040 FIGURE 6: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM ADDRESS AMS-0 TCE CE# TOES TOEH OE# TOE WE# DQ7 D D# D# D 1147 F06.1 Note: AMS = Most significant address AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040 FIGURE 7: DATA# POLLING TIMING DIAGRAM ©2003 Silicon Storage Technology, Inc. S71147-06-000 11 8/04 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet ADDRESS AMS-0 TCE CE# TOES TOE TOEH OE# WE# DQ6 Note TWO READ CYCLES WITH SAME OUTPUTS Note: Toggle bit output is always high first. AMS = Most significant address AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040 1147 F07.1 FIGURE 8: TOGGLE BIT TIMING DIAGRAM TSE SIX-BYTE CODE FOR SECTOR-ERASE 5555 ADDRESS AMS-0 2AAA 5555 5555 2AAA SAX CE# OE# TWP WE# DQ7-0 AA 55 80 AA 55 30 SW0 SW1 SW2 SW3 SW4 SW5 1147 F08.1 Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 10) SAX = Sector Address AMS = Most significant address AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040 FIGURE 9: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM ©2003 Silicon Storage Technology, Inc. S71147-06-000 12 8/04 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet TSCE SIX-BYTE CODE FOR CHIP-ERASE 5555 ADDRESS AMS-0 2AAA 5555 5555 2AAA 5555 CE# OE# TWP WE# DQ7-0 AA 55 80 AA 55 10 SW0 SW1 SW2 SW3 SW4 SW5 1147 F17.1 Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 10) SAX = Sector Address AMS = Most significant address AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040 FIGURE 10: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM Three-byte Sequence for Software ID Entry ADDRESS A14-0 5555 2AAA 5555 0000 0001 CE# OE# TIDA TWP WE# TWPH DQ7-0 AA 55 SW0 SW1 TAA BF 90 Device ID SW2 1147 F09.2 Device ID = B5H for SST39SF010A, B6H for SST39SF020A, and B7H for SST39SF040 FIGURE 11: SOFTWARE ID ENTRY AND READ ©2003 Silicon Storage Technology, Inc. S71147-06-000 13 8/04 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET ADDRESS A14-0 DQ7-0 5555 2AAA AA 5555 55 F0 TIDA CE# OE# TWP WE# TWHP SW0 SW1 SW2 1147 F10.0 FIGURE 12: SOFTWARE ID EXIT AND RESET ©2003 Silicon Storage Technology, Inc. S71147-06-000 14 8/04 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 1147 F11.1 AC test inputs are driven at VIHT (3.0V) for a logic “1” and VILT (0V) for a logic “0”. Measurement reference points for inputs and outputs are VIT (1.5V) and VOT (1.5V). Input rise and fall times (10% ↔ 90%) are <5 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE 13: AC INPUT/OUTPUT REFERENCE WAVEFORMS VDD TO TESTER RL HIGH TO DUT CL RL LOW 1147 F12.0 FIGURE 14: A TEST LOAD EXAMPLE ©2003 Silicon Storage Technology, Inc. S71147-06-000 15 8/04 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet Start Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: A0H Address: 5555H Load Byte Address/Byte Data Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed 1147 F13.1 FIGURE 15: BYTE-PROGRAM ALGORITHM ©2003 Silicon Storage Technology, Inc. S71147-06-000 16 8/04 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet Internal Timer Toggle Bit Data# Polling Byte Program/Erase Initiated Byte Program/Erase Initiated Byte Program/Erase Initiated Read byte Read DQ7 Wait TBP, TSCE, or TSE Read same byte Program/Erase Completed No Is DQ7 = true data? Yes No Does DQ6 match? Program/Erase Completed Yes Program/Erase Completed 1147 F14.0 FIGURE 16: WAIT OPTIONS ©2003 Silicon Storage Technology, Inc. S71147-06-000 17 8/04 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet Software Product ID Entry Command Sequence Software Product ID Exit & Reset Command Sequence Load data: AAH Address: 5555H Load data: AAH Address: 5555H Load data: F0H Address: XXH Load data: 55H Address: 2AAAH Load data: 55H Address: 2AAAH Wait TIDA Load data: 90H Address: 5555H Load data: F0H Address: 5555H Return to normal operation Wait TIDA Wait TIDA Read Software ID Return to normal operation 1147 F15.1 FIGURE 17: SOFTWARE PRODUCT COMMAND FLOWCHARTS ©2003 Silicon Storage Technology, Inc. S71147-06-000 18 8/04 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet Chip-Erase Command Sequence Sector-Erase Command Sequence Load data: AAH Address: 5555H Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: 55H Address: 2AAAH Load data: 80H Address: 5555H Load data: 80H Address: 5555H Load data: AAH Address: 5555H Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: 55H Address: 2AAAH Load data: 10H Address: 5555H Load data: 30H Address: SAX Wait TSCE Wait TSE Chip erased to FFH Sector erased to FFH 1147 F16.1 FIGURE 18: ERASE COMMAND SEQUENCE ©2003 Silicon Storage Technology, Inc. S71147-06-000 19 8/04 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet PRODUCT ORDERING INFORMATION SST 39 XX SF 010A XX XXXX - 45 - XXX - 4C XX NH - XXX E X Environmental Attribute E = non-Pb Package Modifier H = 32 pins or leads Package Type N = PLCC P = PDIP W = TSOP (type 1, die up, 8mm x 14mm) Temperature Range C = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C Minimum Endurance 4 = 10,000 cycles Read Access Speed 45 = 45 ns 70 = 70 ns Version A = Special Feature Version Device Density 040 = 4 Mbit 020 = 2 Mbit 010 = 1 Mbit Voltage S = 4.5-5.5V Product Series 39 = Multi-Purpose Flash ©2003 Silicon Storage Technology, Inc. S71147-06-000 20 8/04 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet Valid combinations for SST39SF010A SST39SF010A-45-4C-NH SST39SF010A-45-4C-WH SST39SF010A-45-4C-NHE SST39SF010A-45-4C-WHE SST39SF010A-70-4C-NH SST39SF010A-70-4C-WH SST39SF010A-70-4C-PH SST39SF010A-70-4C-NHE SST39SF010A-70-4C-WHE SST39SF010A-70-4C-PHE SST39SF010A-45-4I-NH SST39SF010A-45-4I-WH SST39SF010A-45-4I-NHE SST39SF010A-45-4I-WHE SST39SF010A-70-4I-NH SST39SF010A-70-4I-WH SST39SF010A-70-4I-NHE SST39SF010A-70-4I-WHE Valid combinations for SST39SF020A SST39SF020A-45-4C-NH SST39SF020A-45-4C-WH SST39SF020A-45-4C-NHE SST39SF020A-45-4C-WHE SST39SF020A-70-4C-NH SST39SF020A-70-4C-WH SST39SF020A-70-4C-PH SST39SF020A-70-4C-NHE SST39SF020A-70-4C-WHE SST39SF020A-70-4C-PHE SST39SF020A-45-4I-NH SST39SF020A-45-4I-WH SST39SF020A-45-4I-NHE SST39SF020A-45-4I-WHE SST39SF020A-70-4I-NH SST39SF020A-70-4I-WH SST39SF020A-70-4I-NHE SST39SF020A-70-4I-WHE Valid combinations for SST39SF040 SST39SF040-45-4C-NH SST39SF040-45-4C-WH SST39SF040-45-4C-NHE SST39SF040-45-4C-WHE SST39SF040-70-4C-NH SST39SF040-70-4C-WH SST39SF040-70-4C-PH SST39SF040-70-4C-NHE SST39SF040-70-4C-WHE SST39SF040-70-4C-PHE SST39SF040-45-4I-NH SST39SF040-45-4I-WH SST39SF040-45-4I-NHE SST39SF040-45-4I-WHE SST39SF040-70-4I-NH SST39SF040-70-4I-WH SST39SF040-70-4I-NHE SST39SF040-70-4I-WHE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2003 Silicon Storage Technology, Inc. S71147-06-000 21 8/04 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet PACKAGING DIAGRAMS TOP VIEW Optional Pin #1 Identifier .048 .042 SIDE VIEW .495 .485 .453 .447 2 1 32 .112 .106 .020 R. MAX. .029 x 30˚ .023 .040 R. .030 .042 .048 .595 .553 .585 .547 BOTTOM VIEW .021 .013 .400 .530 BSC .490 .032 .026 .050 BSC .015 Min. .095 .075 .050 BSC .140 .125 .032 .026 Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (max/min). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 4. Coplanarity: 4 mils. 32-plcc-NH-3 32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC) SST PACKAGE CODE: NH ©2003 Silicon Storage Technology, Inc. S71147-06-000 22 8/04 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet 1.05 0.95 Pin # 1 Identifier 0.50 BSC 8.10 7.90 0.27 0.17 0.15 0.05 12.50 12.30 DETAIL 1.20 max. 0.70 0.50 14.20 13.80 0˚- 5˚ 0.70 0.50 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 1mm 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 32-tsop-WH-7 32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM SST PACKAGE CODE: WH ©2003 Silicon Storage Technology, Inc. S71147-06-000 23 8/04 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet 32 CL Pin #1 Identifier 1 1.655 1.645 .075 .065 7˚ 4 PLCS. Base Plane Seating Plane .625 .600 .550 .530 .200 .170 .050 .015 .080 .070 .065 .045 .022 .016 .100 BSC .150 .120 0˚ 15˚ .012 .008 .600 BSC Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (max/min). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches. 32-pdip-PH-3 32-PIN PLASTIC DUAL IN-LINE PINS (PDIP) SST PACKAGE CODE: PH TABLE 11: REVISION HISTORY Number Description 2002 Data Book Date 02 • 03 • 04 • • Document status changed from “Preliminary Specification” to “Data Sheet” Changed IDD Program and Erase max values from 25 to 35 in Table 5 on page 8 Oct 2003 05 • • 2004 Data Book Added non-Pb MPNs and removed footnote (See page 21) Nov 2003 06 • Corrected Revision History for Version 04: IDD max value was incorrectly stated as 30 mA instead of 35 mA Aug 2004 May 2002 Changes to Table 5 on page 8 – Added footnote for MPF power usage and Typical conditions – Clarified the Test Conditions for Power Supply Current and Read parameters – Clarified IDD Write to be Program and Erase Mar 2003 Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 www.SuperFlash.com or www.sst.com ©2003 Silicon Storage Technology, Inc. S71147-06-000 24 8/04