CYPRESS CY7C1021CV26

CY7C1021CV26
1-Mbit (64 K × 16) Static RAM
1-Mbit (64 K × 16) Static RAM
Features
automatic power-down feature that significantly reduces power
consumption when deselected.
■
Temperature Range
❐ Automotive: –40 °C to 125 °C
■
High speed
❐ tAA = 15 ns
■
Optimized voltage range: 2.5 V to 2.7 V
■
Low active power: 220 mW (Max)
■
Automatic power-down when deselected
■
Independent control of upper and lower bits
■
CMOS for optimum speed/power
■
Available in Pb-free and non Pb-free 44-pin TSOP II, 44-pin
(400-Mil) Molded SOJ and Pb-free 48-ball FBGA packages
Writing to the device is accomplished by taking Chip Enable (CE)
and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is
LOW, then data from I/O pins (I/O0 through I/O7), is written into
the location specified on the address pins (A0 through A15). If
Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8
through I/O15) is written into the location specified on the address
pins (A0 through A15).
Reading from the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins will
appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then
data from memory will appear on I/O8 to I/O15. See the truth table
at the end of this data sheet for a complete description of Read
and Write modes.
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), the BHE and BLE are
disabled (BHE, BLE HIGH), or during a Write operation (CE
LOW, and WE LOW).
Functional Description
The CY7C1021CV26 is a high-performance CMOS static RAM
organized as 65,536 words by 16 bits. This device has an
Logic Block Diagram
64 K × 16
RAM Array
SENSE AMPS
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
A8
A9
A10
A11
A12
A13
A14
A15
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation
Document Number: 38-05589 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 20, 2011
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CY7C1021CV26
Contents
Selection Guide ................................................................ 3
Pin Configuration ............................................................. 3
Pin Definitions .................................................................. 4
Maximum Ratings ............................................................. 5
Operating Range ............................................................... 5
Electrical Characteristics ................................................. 5
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 6
Switching Characteristics ................................................ 6
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 10
Document Number: 38-05589 Rev. *F
Ordering Information ...................................................... 11
Ordering Code Definitions ......................................... 11
Package Diagrams .......................................................... 12
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 16
Worldwide Sales and Design Support ....................... 16
Products .................................................................... 16
PSoC Solutions ......................................................... 16
Page 2 of 16
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CY7C1021CV26
Selection Guide
Description [1]
-15
Unit
Maximum Access Time
15
ns
Maximum Operating Current
80
mA
Maximum CMOS Standby Current
10
mA
Pin Configuration
Figure 1. 44-pin SOJ/TSOP II [2]
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
Figure 2. 48-ball FBGA Pinout [2]
1
2
3
4
5
6
BLE
OE
A0
A1
A2
NC
A
I/O8
BHE
A3
A4
CE
I/O0
B
I/O9
I/O10
A5
A6
I/O2
I/O1
C
VSS I/O11
NC
A7
VCC
D
VCC
NC
NC
I/O4
VSS
E
I/O14 I/O13 A14
A15
I/O5
I/O6
F
I/O12
I/O3
I/O15
NC
A12
A13
WE
I/O7
G
NC
A8
A9
A10
A11
NC
H
Notes
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C.
2. NC pins are not connected on the die.
Document Number: 38-05589 Rev. *F
Page 3 of 16
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CY7C1021CV26
Pin Definitions
Pin Name
Pin Number
I/O Type
Description
A0–A15
1–5, 18–21,
24–27, 42–44
Input
Address Inputs used to select one of the address locations.
I/O0–I/O15
7–10, 13–16,
29–32, 35–38
Input/Output
Bidirectional Data I/O lines. Used as input or output lines depending on operation.
NC
22, 23, 28
No Connect
No Connects. This pin is not connected to the die.
WE
17
Input/Control
Write Enable Input, active LOW. When selected LOW, a Write is conducted. When
selected HIGH, a Read is conducted.
CE
6
Input/Control
Chip Enable Input, active LOW. When LOW, selects the chip. When HIGH, deselects
the chip.
BHE, BLE
40, 39
Input/Control
Byte Write Select Inputs, active LOW. BHE controls I/O15–I/O8, BLE controls
I/O7–I/O0.
OE
41
Input/Control
Output Enable, active LOW. Controls the direction of the I/O pins. When LOW, the
I/O pins are allowed to behave as outputs. When de-asserted HIGH, I/O pins are
tri-stated, and act as input data pins.
VSS
12, 34
Ground
Ground for the device. Should be connected to ground of the system.
VCC
11, 33
Power Supply
Power Supply inputs to the device.
Document Number: 38-05589 Rev. *F
Page 4 of 16
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CY7C1021CV26
DC input voltage[3] .............................. –0.5 V to VCC + 0.5 V
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65 C to +150 C
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage .......................................... > 2001 V
(per MIL-STD-883, method 3015)
Latch-up current .................................................... > 200 mA
Ambient temperature with
power applied .......................................... –55 C to +125 C
Operating Range
Supply voltage on
VCC to relative GND[3] .................................–0.5 V to +4.6 V
Range
Automotive
DC voltage applied to outputs
in high Z state[3] .................................. –0.5 V to VCC + 0.5 V
Ambient Temperature
VCC
–40 C to +125 C
2.5 V–2.7 V
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
VOH
Output HIGH voltage
VCC = Min, IOH = –1.0 mA
VOL
Output LOW voltage
VCC = Min, IOL = 1.0 mA
-15
Unit
Min
Max
2.3
–
V
–
0.4
V
VIH
Input HIGH voltage
2.0
VCC + 0.3
V
VIL
Input LOW voltage[3]
–0.3
0.8
V
IIX
Input leakage current
GND < VI < VCC
–3
+3
A
IOZ
Output leakage current
GND < VI < VCC, output disabled
–3
+3
A
ICC
VCC operating supply current
VCC = Max, IOUT = 0 mA, f = fMAX = 1/tRC
–
80
mA
ISB1
Automatic CE power-down
Current —TTL inputs
Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX
–
15
mA
ISB2
Automatic CE power-down
Current —CMOS inputs
Max VCC, CE > VCC – 0.3 V, VIN > VCC – 0.3 V,
or VIN < 0.3 V, f = 0
–
10
mA
Capacitance
Parameter [4]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25 C, f = 1 MHz, VCC = 2.6 V
Max
Unit
8
pF
8
pF
Thermal Resistance
Parameter [4]
Description
JA
Thermal Resistance (Junction to Ambient)
JC
Thermal Resistance (Junction to Case)
Test Conditions
Still Air, soldered on a 3 × 4.5 inch, four-layer
printed circuit board
44-pin TSOP II Unit
76.92
C/W
15.86
C/W
Notes
3. VIL (min.) = –2.0V and VIH(max) = VCC + 0.5 V for pulse durations of less than 20 ns.
4. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05589 Rev. *F
Page 5 of 16
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CY7C1021CV26
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms [5]
2.6 V
R1
1830 
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
GND
R2
High Z characteristics:
ALL INPUT PULSES
2.6 V
90%
90%
10%
10%
Rise Time: 1 V/ns
R 317 
OUTPUT
R2
351
5 pF
1976 
(a)
2.6 V
(b)
Fall Time: 1 V/ns
(c)
Switching Characteristics
Over the Operating Range
Parameter [6]
Description
-15
Min
Max
Unit
Read Cycle
tRC
Read cycle time
15
–
ns
tAA
Address to data valid
–
15
ns
tOHA
Data hold from address change
3
–
ns
tACE
CE LOW to data valid
–
15
ns
tDOE
OE LOW to data valid
–
7
ns
tLZOE
OE LOW to low Z[7]
0
–
ns
–
7
ns
tHZOE
OE HIGH to high
Z[7, 8]
Z[7]
tLZCE
CE LOW to low
3
–
ns
tHZCE
CE HIGH to high Z[7, 8]
–
7
ns
tPU[9]
tPD[9]
CE LOW to power-up
0
–
ns
CE HIGH to power-down
–
15
ns
tDBE
Byte enable to data valid
–
7
ns
tLZBE
Byte enable to low Z
0
–
ns
tHZBE
Byte disable to high Z
–
7
ns
Notes
5. AC characteristics (except high Z) are tested using the Thevenin load shown in Figure 3 (a). High Z characteristics are tested for all speeds using the test load
shown inFigure 3 (c).
6. Test conditions assume signal transition time of 2.6 ns or less, timing reference levels of 1.3 V, input pulse levels of 0 to 2.6 V.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of Figure 3. Transition is measured 500 mV from steady-state voltage.
9. This parameter is guaranteed by design and is not tested.
Document Number: 38-05589 Rev. *F
Page 6 of 16
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CY7C1021CV26
Switching Characteristics (continued)
Over the Operating Range
Parameter [6]
Description
-15
Min
Max
Unit
Write Cycle[10]
tWC
Write cycle time
15
–
ns
tSCE
CE LOW to write end
10
–
ns
tAW
Address set-up to write end
10
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address set-up to write start
0
–
ns
tPWE
WE pulse width
10
–
ns
tSD
Data set-up to write end
8
–
ns
tHD
Data hold from write end
0
–
ns
Z[11]
tLZWE
WE HIGH to low
3
–
ns
tHZWE
WE LOW to high Z[11, 12]
–
7
ns
tBW
Byte enable to end of write
9
–
ns
Notes
10. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Write, and
the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
11. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
12. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of Figure 3 on page 6. Transition is measured 500 mV from steady-state voltage.
Document Number: 38-05589 Rev. *F
Page 7 of 16
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CY7C1021CV26
Switching Waveforms
Figure 4. Read Cycle No. 1 [13, 14]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 5. Read Cycle No. 2 (OE Controlled) [14, 15]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
BHE, BLE
tLZOE
tHZCE
tDBE
tLZBE
DATA OUT
HIGH IMPEDANCE
tLZCE
VCC
SUPPLY
CURRENT
tHZBE
DATA VALID
HIGH
IMPEDANCE
tPD
tPU
50%
50%
IICC
CC
IISB
SB
Notes
13. Device is continuously selected. OE, CE, BHE and/or BLE = VIL.
14. WE is HIGH for Read cycle.
15. Address valid prior to or coincident with CE transition LOW.
Document Number: 38-05589 Rev. *F
Page 8 of 16
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CY7C1021CV26
Switching Waveforms (continued)
Figure 6. Write Cycle No. 1 (CE Controlled) [16, 17]
tWC
ADDRESS
CE
tSA
tSCE
tAW
tHA
tPWE
WE
tBW
BHE, BLE
tSD
tHD
DATA I/O
Figure 7. Write Cycle No. 2 (BLE or BHE Controlled)
tWC
ADDRESS
BHE, BLE
tSA
tBW
tAW
tHA
tPWE
WE
tSCE
CE
tSD
tHD
DATA I/O
Notes
16. Data I/O is high-impedance if OE or BHE and/or BLE= VIH.
17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document Number: 38-05589 Rev. *F
Page 9 of 16
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CY7C1021CV26
Switching Waveforms (continued)
Figure 8. Write Cycle No. 3 (WE Controlled, LOW)
OE
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE, BLE
tHZWE
tSD
tHD
DATA I/O
tLZWE
Truth Table
CE
OE
WE
H
X
X
X
X
High Z
High Z
Power-down
Standby (ISB)
L
L
H
L
L
Data Out
Data Out
Read – All bits
Active (ICC)
L
H
Data Out
High Z
Read – Lower bits only
Active (ICC)
H
L
High Z
Data Out
Read – Upper bits only
Active (ICC)
L
L
Data In
Data In
Write – All bits
Active (ICC)
L
X
L
BLE
BHE
I/O0–I/O7
I/O8–I/O15
Mode
Power
L
H
Data In
High Z
Write – Lower bits only
Active (ICC)
H
L
High Z
Data In
Write – Upper bits only
Active (ICC)
L
H
H
X
X
High Z
High Z
Selected, Outputs Disabled
Active (ICC)
L
X
X
H
H
High Z
High Z
Selected, Outputs Disabled
Active (ICC)
Document Number: 38-05589 Rev. *F
Page 10 of 16
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CY7C1021CV26
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The following table contains only
the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at http://www.cypress.com
and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative.
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(ns)
15
Ordering Code
Package
Name
Package Type
CY7C1021CV26-15ZSXE
51-85087 44-pin TSOP Type II (Pb-free)
CY7C1021CV26-15VXE
51-85082 44-pin (400-Mil) Molded SOJ (Pb-free)
CY7C1021CV26-15BAE
51-85150 48-ball FBGA (6 × 8 × 1 mm) (Pb-free)
CY7C1021CV26-15BAET
51-85150 48-ball FBGA (6 × 8 × 1 mm) (Pb-free)
CY7C1021CV26-15VXET
51-85082 44-pin (400-Mil) Molded SOJ (Pb-free)
CY7C1021CV26-15ZSXET
51-85087 44-pin TSOP Type II (Pb-free)
Operating
Range
Automotive
Ordering Code Definitions
CY 7
C 1021 C V26 - 15 XX X E X
X = T or Blank
T = Tape and Reel; Blank = Tube
Temperature Range: E = Automotive
Pb-free
Package Type: XX = ZS or V or BA
ZS = 44-pin TSOP Type II
V = 44-pin (400-Mil) Molded SOJ
BA = 48-ball FBGA
Speed Grade: 15 ns
V26 = 2.6 V
Process Technology  0.16 µm
Part Identifier
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 38-05589 Rev. *F
Page 11 of 16
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CY7C1021CV26
Package Diagrams
Figure 9. 44-pin TSOP Z44-II, 51-85087
51-85087 *C51-85087-*A
Figure 10. 44-pin Molded SOJ (400-Mil) V44.4, 51-85082
51-85082 *C
Document Number: 38-05589 Rev. *F
Page 12 of 16
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CY7C1021CV26
Package Diagrams (continued)
Figure 11. 48-ball FBGA (6 × 8 × 1 mm), 51-85150
51-85150 *F
Document Number: 38-05589 Rev. *F
Page 13 of 16
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CY7C1021CV26
Acronyms
Acronym
Document Conventions
Description
CMOS
complementary metal oxide semiconductor
CE
chip enable
I/O
input/output
OE
output enable
SOJ
small outline J-lead
SRAM
static random access memory
TSOP
thin small-outline package
TTL
Units of Measure
Symbol
Unit of Measure
°C
degree Celsius
µA
micro Amperes
mA
milli Amperes
mm
milli meter
mW
milli Watts
transistor-transistor logic
MHz
Mega Hertz
FBGA
fine-pitch ball grid array
ns
nano seconds
WE
write enable
pF
pico Farad
V
Volts
W
Watts
%
percent
Document Number: 38-05589 Rev. *F
Page 14 of 16
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CY7C1021CV26
Document History Page
Document Title: CY7C1021CV26, 1-Mbit (64 K × 16) Static RAM
Document Number: 38-05589
REV.
ECN NO.
Issue Date
Orig. of
Change
**
238454
See ECN
RKF
New data sheet for Automotive
*A
335861
See ECN
SYT
Added Lead-Free Product Information
Included the 44-Lead (400-Mil) Molded SOJ V34 Package
*B
493543
See ECN
NXR
Changed the description of IIX from Input Load Current to
Input Leakage Current in DC Electrical Characteristics table
Removed IOS parameter from DC Electrical Characteristics table
Updated Ordering Information Table
*C
2897087
03/22/10
AJU
Removed obsolete parts from ordering information table
Updated package diagrams
*D
3057593
10/13/2010
PRAS
Updated Ordering Information and added Ordering Code Definitions.
Updated Package Diagrams.
*E
3098812
12/01/2010
PRAS
Added Acronyms and Units of Measure.
Minor edits and updated in new template.
*F
3277371
06/08/2011
AJU
Document Number: 38-05589 Rev. *F
Description of Change
Updated Pin Configuration (Included pin configurations for 44-pin SOJ and
48-ball FBGA packages).
Page 15 of 16
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Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
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psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
cypress.com/go/memory
cypress.com/go/image
PSoC
cypress.com/go/psoc
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cypress.com/go/touch
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Wireless/RF
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05589 Rev. *F
Revised June 20, 2011
Page 16 of 16
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