CY2DM1502 1:2 CML / LVPECL Input to CML Output Fanout Buffer Features Functional Description ■ One current mode logic (CML) or low-voltage positive emitter-coupled logic (LVPECL) input pair distributed to two CML output pairs ■ 20-ps maximum output-to-output skew ■ 480-ps maximum propagation delay The CY2DM1502 is an ultra-low noise, low-skew, low-propagation delay 1:2 CML or LVPECL to CML fanout buffer targeted to meet the requirements of high-speed clock distribution applications. The device has a fully differential internal architecture that is optimized to achieve low additive jitter and low skew at operating frequencies of up to 1.5 GHz. ■ 0.15-ps maximum additive RMS phase jitter at 156.25 MHz (12-kHz to 20-MHz offset) ■ Up to 1.5 GHz operation ■ 8-Pin thin shrunk small outline package (TSSOP) package ■ 2.5-V or 3.3-V operating voltage[1] ■ Commercial and industrial operating temperature range Logic Block Diagram VDD VDD VSS Q0 Q0# IN IN# Q1 Q1# Note 1. Input AC-coupling capacitors are required for voltage-translation applications. Cypress Semiconductor Corporation Document Number: 001-56315 Rev. *F • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised February 25, 2011 [+] Feedback CY2DM1502 Contents Pinouts .............................................................................. Absolute Maximum Ratings ............................................ Operating Conditions....................................................... DC Electrical Specifications ............................................ AC Electrical Specifications ............................................ Ordering Information........................................................ Ordering Code Definition............................................. Package Dimension.......................................................... Document Number: 001-56315 Rev. *F 3 3 3 4 5 8 8 9 Acronyms ........................................................................ Document Conventions ................................................. Document History Page ................................................. Sales, Solutions, and Legal Information ...................... Worldwide Sales and Design Support....................... Products .................................................................... PSoC Solutions ......................................................... 10 10 11 12 12 12 12 Page 2 of 12 [+] Feedback CY2DM1502 Pinouts Q0 1 Q0# 2 Q1 3 Q1# 4 CY2DM1502 Figure 1. Pin Diagram – 8-Pin TSSOP Package 8 VDD 7 IN 6 IN# 5 VSS Table 1. Pin Definitions Pin No. Pin Name Pin Type Description 1,3 Q(0:1) Output CML output clocks 2,4 Q(0:1)# Output CML complementary output clocks 5 VSS Power Ground 6 IN# Input CML/LVPECL complementary input clock 7 IN Input CML/LVPECL input clock 8 VDD Power Power supply Absolute Maximum Ratings Parameter Description Condition Min Max Unit VDD Supply voltage Nonfunctional –0.5 4.6 V VIN[2] Input voltage, relative to VSS Nonfunctional –0.5 lesser of 4.0 or VDD + 0.4 V VOUT[2] DC output or I/O voltage, relative to VSS Nonfunctional –0.5 lesser of 4.0 or VDD + 0.4 V TS Storage temperature Nonfunctional –55 150 °C ESDHBM Electrostatic discharge (ESD) protection (Human body model) JEDEC STD 22-A114-B 2000 – V LU Latch up UL–94 Flammability rating MSL Moisture sensitivity level Meets or exceeds JEDEC Spec JESD78B IC Latchup Test At 1/8 in V-0 3 Operating Conditions Parameter Description VDD Supply voltage TA Ambient operating temperature tPU Power ramp time Min Max Unit 2.5-V supply Condition 2.375 2.625 V 3.3-V supply 3.135 3.465 V Commercial 0 70 °C Industrial –40 85 °C Power-up time for VDD to reach minimum specified voltage (power ramp must be monotonic). 0.05 500 ms Note 2. The voltage on any I/O pin cannot exceed the power pin during power up. Power supply sequencing is NOT required. Document Number: 001-56315 Rev. *F Page 3 of 12 [+] Feedback CY2DM1502 DC Electrical Specifications (VDD = 3.3 V ± 5% or 2.5 V ± 5%; TA = 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial)) Parameter Description Min Max Unit – 50 mA Input high voltage, CML / LVPECL inputs IN and IN# – VDD + 0.3 V VIL Input low voltage, CML / LVPECL inputs IN and IN# –0.3 – V VID[3] Input differential amplitude See Figure 2 on page 6 0.4 1.0 V VICM Input common mode voltage See Figure 2 on page 6 0.5 VDD – 0.2 V IIH Input high current, CML / LVPECL inputs Input = VDD[4] IN and IN# – 150 μA IIL Input low current, CML / LVPECL inputs Input = VSS[4] IN and IN# –150 – μA VOH CML output high voltage Terminated with 50 Ω to VDD[5] VDD – 0.1 – VOL CML output low voltage Terminated with 50 Ω to VDD[5] VDD – 0.7 VDD – 0.3 CIN Input capacitance Measured at 10 MHz; per pin IDD Operating supply current VIH Condition All CML outputs floating (internal IDD) – 3 V V pF Notes 3. VID minimum of 400 mV is required to meet all output AC Electrical Specifications. The device is functional with VID minimum of greater than 200 mV. 4. Positive current flows into the input pin, negative current flows out of the input pin. 5. Refer to Figure 3 on page 6. Document Number: 001-56315 Rev. *F Page 4 of 12 [+] Feedback CY2DM1502 AC Electrical Specifications (VDD = 3.3 V ± 5% or 2.5 V ± 5%; TA = 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial)) Parameter Description Condition Min Typ Max Unit DC – 1.5 GHz FOUT = FIN DC – 1.5 GHz Fout = DC to 150 MHz 250 – 700 mV 250 – 600 mV Input rise/fall time < 1.5 ns (20% to 80%) – – 480 ps Output duty cycle 50% duty cycle at input Frequency range up to 1 GHz 48 – 52 % tSK1[8] Output-to-output skew Any output to any output, with same load conditions at DUT – – 20 ps tSK1 D[8] Device-to-device output skew Any output to any output between two or more devices. Devices must have the same input and have the same output load. – – 150 ps PNADD Additive RMS phase noise 156.25-MHz Input Rise/fall time < 150 ps (20% to 80%) VID > 400 mV Offset = 1 kHz – – –120 dBc/Hz Offset = 10 kHz – – –130 dBc/Hz Offset = 100 kHz – – –135 dBc/Hz FIN Input frequency FOUT Output frequency VPP CML differential output voltage peak-to-peak, single-ended. Terminated with 50 Ω to VDD[5] Fout = >150 MHz to 1.5 GHz tPD[6] Propagation delay input pair to output pair tODC[7] Offset = 1 MHz – – –145 dBc/Hz Offset = 10 MHz – – –153 dBc/Hz Offset = 20 MHz – – –155 dBc/Hz tJIT[9] Additive RMS phase jitter (Random) 156.25 MHz, 12 kHz to 20 MHz offset; input rise/fall time < 150 ps (20% to 80%), VID > 400 mV – – 0.15 ps tR, tF[10] Output rise/fall time 50% duty cycle at input, 20% to 80% of full swing (VOL to VOH) Input rise/fall time < 1.5 ns (20% to 80%) Measured at 1 GHz – – 250 ps Notes 6. Refer to Figure 4 on page 6. 7. Refer to Figure 5 on page 6. 8. Refer to Figure 6 on page 7. 9. Refer to Figure 7 on page 7. 10. Refer to Figure 8 on page 7. Document Number: 001-56315 Rev. *F Page 5 of 12 [+] Feedback CY2DM1502 Figure 2. Input Differential and Common Mode Voltages VA IN VICM = (VA + VB)/2 VID IN# VB Figure 3. Output Differential Voltage VOH Q VPP Q# VOL Figure 4. Input to Any Output Pair Propagation Delay IN IN # QX Q X# tP D Figure 5. Output Duty Cycle QX Q X# tPW tPERIOD tODC = Document Number: 001-56315 Rev. *F tPW tPERIOD Page 6 of 12 [+] Feedback CY2DM1502 Figure 6. Output-to-Output and Device-to-Device Skew QX Q X# Device 1 QY Q Y# tSK1 QZ Device 2 Q Z# tSK1 D Figure 7. RMS Phase Jitter Phase noise Noise Power Phase noise mark Offset Frequency f2 f1 RMS Jitter ∝ Area Under the Masked Phase Noise Plot Figure 8. Output Rise/Fall Time QX 80% 80% VPP 20% QX# 20% tR Document Number: 001-56315 Rev. *F tF Page 7 of 12 [+] Feedback CY2DM1502 Ordering Information Part Number Type Production Flow Pb-free CY2DM1502ZXC 8-Pin TSSOP Commercial, 0 °C to 70 °C CY2DM1502ZXCT 8-Pin TSSOP tape and reel Commercial, 0 °C to 70 °C CY2DM1502ZXI 8-Pin TSSOP Industrial, –40 °C to 85 °C CY2DM1502ZXIT 8-Pin TSSOP tape and reel Industrial, –40 °C to 85 °C Ordering Code Definition CY 2DM15 02 ZX C/I T Tape and reel Temperature range C = Commercial I = Industrial Pb-free TSSOP package Number of differential output pairs Base part number Company ID: CY = Cypress Document Number: 001-56315 Rev. *F Page 8 of 12 [+] Feedback CY2DM1502 Package Dimension Figure 9. 8-Pin Thin Shrunk Small Outline Package (4.40 MM Body) Z8 51-85093 *C Document Number: 001-56315 Rev. *F Page 9 of 12 [+] Feedback CY2DM1502 Acronyms Document Conventions Table 2. Acronyms Used in this Document Table 3. Units of Measure Acronym Description Symbol Unit of Measure CML current mode logic °C degree Celsius ESD electrostatic discharge dBc decibels relative to the carrier HBM human body model GHz giga hertz JEDEC Joint electron devices engineering council Hz hertz LVDS low-voltage differential signal kΩ kilo ohm LVCMOS low-voltage complementary metal oxide semiconductor µA microamperes µF micro Farad LVPECL low-voltage positive emitter-coupled logic LVTTL low-voltage transistor-transistor logic OE Output enable RMS root mean square TSSOP thin shrunk small outline package Document Number: 001-56315 Rev. *F µs microsecond mA milliamperes ms millisecond mV millivolt MHz megahertz ns nanosecond Ω ohm pF pico Farad ps pico second V volts W watts Page 10 of 12 [+] Feedback CY2DM1502 Document History Page Document Title: CY2DM1502 1:2 CML / LVPECL Input to CML Output Fanout Buffer Document Number: 001-56315 Revision ECN Orig. of Change Submission Date Description of Change ** 2782891 CXQ 10/09/09 *A 2838916 CXQ 01/05/2010 Changed status from “ADVANCE” to “PRELIMINARY”. Changed from 0.34 ps to 0.25 ps maximum additive jitter in “Features” on page 1 and in tJIT in the AC Electrical Specs table on page 4. Added tPU spec to the Operating Conditions table on page 2. Removed VOH spec maximum of VDD in the DC Electrical Specs table on page 3. Changed VOL spec min from VDD - 0.6V to VDD - 0.7V; changed max from VDD - 0.4V to VDD - 0.3V in the DC Electrical Specs table on page 3. Removed VOD spec of minimum 300 mV, maximum 450 mV in the DC Electrical Specs table on page 3. Added RP spec in the DC Electrical Specs table on page 3. Min = 60 kΩ, Max = 140 kΩ. Added a measurement definition for CIN in the DC Electrical Specs table on page 3. Added VPP spec to the AC Electrical Specs table on page 4. VPP max = 700 mV for DC - 150 MHz and max = 600 mV for 150 MHz to 1.5 GHz. VPP min = 250 mV over the entire range. Changed letter case and some names of all the timing parameters in the AC Electrical Specs table on page 4 to be consistent with EROS. Lowered all additive phase noise mask specs by 3 dB in in the AC Electrical Specs table on page 4. Added condition to tR and tF specs in the AC Electrical specs table on page 4 that input rise/fall time must be less than 1.5 ns (20% to 80%). Changed letter case and some names of all the timing parameters in Figures 3, 4, 5, 6 and 8, to be consistent with EROS. *B 3011766 CXQ 08/20/2010 Changed from 0.25 ps to 0.11 ps maximum additive jitter in “Features” on page 1 and in tJIT in the AC Electrical Specs table. Added note 3 to describe IIH and IIL specs. Removed reference to data distribution from “Functional Description”. Changed RP for diff inputs from 100 kΩ to 150 kΩ in the Logic Block Diagram and from 60 kΩ min / 140 kΩ max to 90 kΩ min / 210 kΩ max in the DC Electrical Specs table. Added max VID of 1.0V in DC Electrical Specs table. Updated phase noise specs for 1 k/10 k/100 k/1 M/10 M/20 MHz offset to -120/-130/-135/-150/-150/-150dBc/Hz, respectively, in the AC Electrical Specs table. Added “Frequency range up to 1 GHz” condition to tODC spec. Updated package diagram. Added Acronyms and Ordering Code Definition. *C 3017258 CXQ 08/27/2010 Corrected Output Rise/Fall time diagram. *D 3100234 CXQ 11/18/2010 Updated Phase jitter to 0.15ps max from 0.11ps max. Changed VIN and VOUT specs from 4.0V to “lesser of 4.0 or VDD + 0.4” Removed 200mA min LU spec, replaced with “Meets or exceeds JEDEC Spec JESD78B IC Latchup Test” Removed RP spec for differential input clock pins INX and INX#. Changed CIN condition to “Measured at 10 MHz”. Changed PNADD specs for 1MHz, 10MHz, and 20MHz offsets. Added condition “Measured at 1 GHz” to tR, tF specs. *E 3137726 CXQ 01/13/2011 Removed “Preliminary” status heading. Removed resistors from IN/IN# in Logic Block Diagram. *F 3090938 CXQ 02/25/2011 Post to external web. Document Number: 001-56315 Rev. *F New Datasheet. Page 11 of 12 [+] Feedback CY2DM1502 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive psoc.cypress.com/solutions cypress.com/go/clocks PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing cypress.com/go/memory cypress.com/go/image PSoC Touch Sensing cypress.com/go/psoc cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. 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Document Number: 001-56315 Rev. *F Revised February 25, 2011 Page 12 of 12 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback