M54HC112 RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 79MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 54 SERIES 112 SPACE GRADE-1: ESA SCC QUALIFIED 50 krad QUALIFIED, 100 krad AVAILABLE ON REQUEST NO SEL UNDER HIGH LET HEAVY IONS IRRADIATION DEVICE FULLY COMPLIANT WITH SCC-9203-051 DESCRIPTION The M54HC112 is an high speed CMOS DUAL J-K FLIP-FLOP WITH PRESET AND CLEAR fabricated with silicon gate C2MOS technology. The M54HC112 dual JK flip-flop features DILC-16 FPC-16 ORDER CODES PACKAGE FM EM DILC FPC M54HC112D M54HC112K M54HC112D1 M54HC112K1 individual J, K, clock, and asynchronous set and clear inputs for each flip-flop. When the clock goes high, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is high and the bistable will function as shown in the truth table. Input data is transferred to the input on the negative going edge of the clock pulse. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION March 2004 1/11 M54HC112 IEC LOGIC SYMBOLS INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN N° SYMBOL NAME AND FUNCTION Clock Input (HIGH to LOW edge triggered) Data Inputs: Flip-Flop 1 1K, 2K and 2 Data Inputs: Flip-Flop 1 1J, 2J and 2 1PR, 2PR Set Inputs 1Q, 2Q True Flip-Flop Outputs Complement Flip-Flop 1Q, 2Q Outputs 1CLR, 2CLR Reset Inputs GND Ground (0V) VCC Positive Supply Voltage 1CK, 2CK 1, 13 2, 12 3, 11 4, 10 5, 9 6, 7 15, 14 8 16 TRUTH TABLE INPUTS OUTPUTS FUNCTION CLR PR J K CK Q Q L H L H L L X X X X X X X X X L H H H L H CLEAR PRESET ---- H H L L Qn Qn NO CHANGE H H H L H L ---- H H L H L H ---- H H H H Qn Qn TOGGLE H H X X Qn Qn NO CHANGE X : Don’t Care 2/11 M54HC112 LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Supply Voltage Value Unit -0.5 to +7 V VI DC Input Voltage -0.5 to VCC + 0.5 V VO DC Output Voltage -0.5 to VCC + 0.5 ± 20 V mA IIK DC Input Diode Current IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 25 mA ± 50 mA ICC or IGND DC VCC or Ground Current Power Dissipation PD Tstg Storage Temperature TL Lead Temperature (10 sec) 300 mW -65 to +150 °C 265 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Supply Voltage Value Unit 2 to 6 V V VI Input Voltage 0 to VCC VO Output Voltage 0 to VCC V Top Operating Temperature -55 to 125 °C VCC = 2.0V 0 to 1000 ns VCC = 4.5V 0 to 500 ns VCC = 6.0V 0 to 400 ns Input Rise and Fall Time tr, tf 3/11 M54HC112 DC SPECIFICATIONS Test Condition Symbol VIH VIL VOH VOL II ICC 4/11 Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Quiescent Supply Current Value TA = 25°C VCC (V) Min. 2.0 4.5 6.0 2.0 4.5 6.0 Typ. Max. 1.5 3.15 4.2 -40 to 85°C -55 to 125°C Min. Min. Max. 1.5 3.15 4.2 0.5 1.35 1.8 Max. 1.5 3.15 4.2 0.5 1.35 1.8 V 0.5 1.35 1.8 2.0 IO=-20 µA 1.9 2.0 1.9 1.9 4.5 IO=-20 µA 4.4 4.5 4.4 4.4 Unit V 6.0 IO=-20 µA 5.9 6.0 5.9 5.9 4.5 IO=-4.0 mA 4.18 4.31 4.13 4.10 6.0 IO=-5.2 mA 5.68 2.0 IO=20 µA 0.0 0.1 0.1 0.1 4.5 IO=20 µA 0.0 0.1 0.1 0.1 6.0 IO=20 µA 0.0 0.1 0.1 0.1 4.5 IO=4.0 mA 0.17 0.26 0.33 0.40 6.0 IO=5.2 mA 0.18 0.26 0.33 0.40 6.0 VI = VCC or GND ± 0.1 ±1 ±1 µA 6.0 VI = VCC or GND 2 20 40 µA 5.8 5.63 V 5.60 V M54HC112 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns) Test Condition Symbol Parameter tTLH tTHL Output Transition Time tPLH tPHL Propagation Delay Time (CK - Q, Q) tPLH tPHL Propagation Delay Time (CLR, PR - Q, Q) fMAX Maximum Clock Frequency tW(H) tW(L) Minimum Pulse Width (CLOCK) tW(L) Minimum Pulse Width (CLR, PR) ts th tREM Minimum Set-up Time Minimum Hold Time Minimum Removal Time (CLR, PR) Value TA = 25°C VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Min. Typ. Max. 75 15 13 125 25 21 135 27 23 8 40 47 30 8 7 52 16 14 68 17 14 16 68 79 20 5 4 20 5 4 28 7 6 -40 to 85°C -55 to 125°C Min. Min. Max. 95 19 16 155 31 26 170 34 29 6.4 32 38 75 15 13 75 15 13 75 15 13 0 0 0 50 10 9 24 4 3 Max. 110 22 19 190 38 32 205 41 35 5.4 27 32 95 19 16 95 19 16 95 19 16 0 0 0 60 12 10 Unit ns ns ns MHz 110 22 19 110 22 19 110 22 19 0 0 0 70 14 12 ns ns ns ns ns CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter VCC (V) Value TA = 25°C Min. Typ. Max. 10 CIN Input Capacitance 5.0 5 CPD Power Dissipation Capacitance (note 1) 5.0 33 -40 to 85°C -55 to 125°C Min. Min. Max. 10 Unit Max. 10 pF pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/2 (per FLIP/ FLOP) 5/11 M54HC112 TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance) RT = ZOUT of pulse generator (typically 50Ω) WAVEFORM 1: PROPAGATION DELAY TIMES, MINIMUM PULSE WIDTH (CK), SETUP AND HOLD TIME (J to CK) (f=1MHz; 50% duty cycle) 6/11 M54HC112 WAVEFORM 2: PROPAGATIONS DELAY TIME, MINIMUM PULSE WIDTH (CLR, PR) (f=1MHz; 50% duty cycle) WAVEFORM 3: MINIMUM REMOVAL TIME (CLR to CK) (f=1MHz; 50% duty cycle) 7/11 M54HC112 WAVEFORM 4: MINIMUM REMOVAL TIME (PR to CK) (f=1MHz; 50% duty cycle) 8/11 M54HC112 DILC-16 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. MIN. TYP. MAX. A 2.1 2.71 0.083 0.107 a1 3.00 3.70 0.118 0.146 a2 0.63 1.14 0.025 B 1.82 2.39 0.072 b 0.40 0.45 0.50 0.016 0.018 0.020 b1 0.20 0.254 0.30 0.008 0.010 0.012 D 20.06 20.32 20.58 0.790 0.800 0.810 e 7.36 7.62 7.87 0.290 0.300 0.310 e1 0.88 2.54 0.035 0.045 0.094 0.100 e2 17.65 17.78 17.90 0.695 0.700 0.705 e3 7.62 7.87 8.12 0.300 0.310 0.320 F 7.29 7.49 7.70 0.287 0.295 0.303 I 3.83 0.151 K 10.90 12.1 0.429 0.476 L 1.14 1.5 0.045 0.059 0056437F 9/11 M54HC112 FPC-16 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. MIN. TYP. MAX. A 6.75 6.91 7.06 0.266 0.272 0.278 B 9.76 9.94 10.14 0.384 0.392 0.399 C 1.49 1.95 0.059 D 0.102 0.127 0.152 0.004 0.005 0.006 E 8.76 8.89 9.01 0.345 0.350 0.355 F 0.077 1.27 G 0.38 H 6.0 L 18.75 M 0.33 0.050 0.43 0.48 0.015 0.017 0.019 0.237 0.38 N 22.0 0.738 0.43 0.013 0.867 0.015 4.31 0.017 0.170 G F D H 9 16 A N L 8 1 H E B 10/11 M C 0016030E M54HC112 Information furnished is believed to be accurate and reliable. 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