CYPRESS CY25818SXCT

CY25818/19
Spread Spectrum Clock Generator
Features
Applications
• 8- to 32-MHz input frequency range
• Printers and MFPs
• CY25818: 8–16 MHz
• LCD panels and notebook PCs
• CY25819: 16–32 MHz
• Digital copiers
• Separate modulated and unmodulated clocks
• PDAs
• Accepts clock, crystal, and resonator inputs
• Automotive
• Down spread modulation
• CD-ROM, VCD, and DVD
• Power-down function
• Networking and LAN/WAN
• Low-power dissipation
• Scanners
— CY25818 = 33 mW-typ @ 8 MHz
• Modems
— CY25818 = 56 mW-typ @ 16 MHz
• Embedded digital systems
— CY25819 = 36 mW-typ @ 16 MHz
Benefits
— CY25819 = 63 mW-typ @ 32 MHz
• Peak electromagnetic interference (EMI) reduction by
8–16 dB
• Low cycle-to-cycle jitter
— SSCLK = 250 ps-typ
• Fast time to market
— REFOUT = 275 ps-typ
• Cost reduction
• Available in 8-pin (150-mil) SOIC package
Block Diagram
Pin Configuration
300K
XIN/CLKIN 1
REFERENCE
DIVIDER
PD and
CP
MODULATION
CONTROL
VCO
COUNTER
LF
XIN/CLKIN 1
XOUT 8
VDD
Vss 2
VCO
CY25818
CY25819
S0 3
7
VSS 2
8 XOUT
6 PD#
SSCLK 4
INPUT
DECODER
3
DIVIDER
and
MUX
4
SSCLK
5
REFCLK
7 Vdd
5 REFCLK
8 Pin SOIC
8-pin SOIC
6
S0 PD#
Cypress Semiconductor Corporation
Document #: 38-07362 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 11, 2006
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CY25818/19
.
Pin Description
Pin
Name
Description
1
XIN/CLK
2
Vss
Power Supply Ground.
3
S0
Digital Spread% Control Pin. 3-Level input (H-M-L). Default = M.
4
SSCLK
5
REFCLK
6
PD#
Power-Down Control Pin. Default = H (Vdd).
7
Vdd
Positive Power Supply.
8
XOUT
Clock, Crystal, or Ceramic Resonator Input Pin.
Modulated Spread Spectrum Output Clock. The output frequency is referenced to input frequency. Refer
to Table 2 for the amount of modulation (Spread%).
Unmodulated Reference Clock Output. The unmodulated output frequency is the same as the input
frequency.
Clock, Crystal, or Ceramic Resonator Output Pin. Leave this pin unconnected if an external clock is used
at XIN pin.
Overview
The Cypress CY25818/19 products are Spread Spectrum
Clock Generator (SSCG) ICs used for the purpose of reducing
EMI found in today’s high-speed digital electronic systems.
The devices use a Cypress proprietary phase-locked loop
(PLL) and Spread Spectrum Clock (SSC) technology to
synthesize and modulate the frequency of the input clock. By
frequency modulating the clock, the measured EMI at the
fundamental and harmonic frequencies is greatly reduced.
This reduction in radiated energy can significantly reduce the
cost of complying with regulatory agency requirements and
improve time to market without degrading system performance.
The CY25818/19 products are available in an 8-pin SOIC
(150-mil) package with a commercial operating temperature
range of 0–70°C. Contact Cypress for availability of –40 to
+85°C industrial temperature range operation or TSSOP
package versions. Refer to the CY25568, CY25811,
CY25812, and CY25814 products for other functions such as
clock multiplication of 1×, 2×, or 4× to generate a wide range
of Spread Spectrum output clocks from 4 to 128 MHz.
Input Frequency Range and Selection
CY25818/19 input frequency range is 8–32 MHz. This range
is divided into two segments, as given in Table 1.
Table 1. Input and Output Frequency Selection
The input frequency range is 8–16 MHz for the CY25818 and
16–32 MHz for the CY25819. Both products accept external
clock, crystal, or ceramic resonator inputs.
The CY25818/19 provide separate modulated (SSCLK) and
unmodulated reference (REFCLK) clock outputs which are the
same frequency as the input clock frequency. Down spread
frequency modulation can be selected by the user, based on
three discrete values of Spread%. A separate power down
function is also provided.
Product
CY25818
CY25819
Input/Output Frequency Range
8–16 MHz
16–32 MHz
Spread% Selection
CY25818/19 SSCG products provide Down-Spread frequency
modulation. The amount of Spread% is selected by using
3-Level S0 digital input. Spread% values are given in Table 2.
Table 2. Spread% Selection
XIN (MHz)
Product
8–10
10–12
12–14
14–16
16–20
20–24
24–28
28–32
CY25818
CY25818
CY25818
CY25818
CY25819
CY25819
CY25819
CY25819
Document #: 38-07362 Rev. *B
S0 = 1
Down (%)
–3.0
–2.7
–2.5
–2.3
–3.0
–2.7
–2.5
–2.3
S0 = 0
Down (%)
–2.2
–1.9
–1.8
–1.7
–2.2
–1.9
–1.8
–1.7
S0 = M
Down (%)
–0.7
–0.6
–0.6
–0.5
–0.7
–0.6
–0.6
–0.5
Page 2 of 7
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CY25818/19
3-Level Digital Inputs
Modulation Rate
S0 digital input is designed to sense three logic levels designated as HIGH “1,” LOW “0,” and MIDDLE “M.” With this
3-Level digital input logic, the 3-Level logic is able to detect
three different logic levels.
Spread Spectrum Clock Generators utilize frequency
modulation (FM) to distribute energy over a specific band of
frequencies. The maximum frequency of the clock (fmax) and
minimum frequency of the clock (fmin) determine this band of
frequencies. The time required to transition from fmin to fmax
and back to fmin is the period of the Modulation Rate, Tmod.
The Modulation Rates of SSCG clocks are generally referred
to in terms of frequency, and fmod = 1/Tmod.
The S0 pin includes an on-chip 20K (10K/10K) resistor divider.
No external application resistors are needed to implement
3-Level logic, as follows.
Logic Level “0”: 3-Level logic pin connected to GND.
Logic Level “M”: 3-Level logic pin left floating (no connection.)
Logic Level “1”: 3-Level logic pin connected to Vdd.
In the case of CY25818/19 devices, the (Spread Spectrum)
Modulation Rate, fmod, is given by the following formula:
Figure 1 illustrates how to implement 3-Level Logic.
L O G IC
L O W (0 )
L O G IC
H IG H (H )
L O G IC
M ID D L E (M )
VDD
S0
S0
S0
to V S S
UNCO NNECTED
to V D D
The input clock frequency, fin, and the internal divider
determine the Modulation Rate.
fmod = fIN/DR
where fmod is the Modulation Rate, fIN is the Input Frequency,
and DR is the Divider Ratio, as given in Table 3.
VSS
Figure 1. 3-Level Logic
Table 3. Modulation Rate Divider Ratios
Product
Input Frequency Range
Divider Ratio (DR)
CY25818
8–16 MHz
256
CY25819
16–32 MHz
512
Maximum Ratings[1, 2]
Input Voltage Relative to Vss:............................... Vss + 0.3V
Supply Voltage (Vdd): ..................................................+ 5.5V
Input Voltage Relative to Vdd:.............................. Vdd + 0.3V
Operating Temperature:................................... 0°C to + 70°C
Storage Temperature: ................................ –65°C to + 150°C
Table 4. DC Electrical Characteristics Vdd = 3.3V ±10%, TA = 0°C to +70°C and CL = 15 pF (unless otherwise noted)
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
Vdd
Power Supply Range
2.97
3.3
3.63
V
VINH
Input HIGH Voltage
S0 Input
0.85 Vdd
Vdd
Vdd
V
VINM
Input MIDDLE Voltage
S0 Input
0.40 Vdd
0.50 Vdd
0.60 Vdd
V
VINL
Input LOW Voltage
S0 Input
0.0
0.0
0.15 Vdd
V
VOH1
Output HIGH Voltage
IOH = 4 ma, SSCLK and REFCLK
2.4
–
–
V
VOH2
Output HIGH Voltage
IOH = 6 ma, SSCLK and REFCLK
2.0
–
–
V
VOL1
Output LOW Voltage
IOL = 4 ma, SSCLK Output
–
–
0.4
V
VOL2
Output LOW Voltage
IOL = 10 ma, SSCLK Output
–
–
1.2
V
CIN1
Input Capacitance
XIN (Pin 1) and XOUT (Pin 8)
6.0
7.5
9.0
pF
CIN2
Input Capacitance
All Digital Inputs
3.5
4.5
6.0
pF
IDD1
Power Supply Current
FIN=8 MHz, no load
–
10.0
12.5
mA
IDD3
Power Supply Current
FIN=32 MHz, no load
–
19.0
23.0
mA
IDD4
Power Supply Current
PD# = Vss
–
150
250
mA
Document #: 38-07362 Rev. *B
Page 3 of 7
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CY25818/19
Table 5. Timing Electrical Characteristics Vdd = 3.3V ±10%, TA = 0°C to +70°C and CL = 15 pF (unless otherwise noted)
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
ICLKFR1
Input Frequency Range
CY25818
8
–
16
MHz
ICLKFR2
Input Frequency Range
CY25819
16
–
32
MHz
trise1
Clock Rise Time
SSCLK and REFCLK, 0.4V to 2.4V
2.0
3.0
4.0
ns
tfall1
Clock Fall Time
SSCLK and REFCLK, 0.4V to 2.4V
2.0
3.0
4.0
ns
CDCin
Input Clock Duty Cycle
XIN
20
50
80
%
CDCout
Output Clock Duty Cycle
SSCLK and REFCLK @ 1.5V
45
50
55
%
CCJss
Cycle-to-Cycle Jitter
SSCLK; FIN = FOUT = 8–32 MHz
250
350
ps
CCJref
Cycle-to-Cycle Jitter
REFCLK; FIN = FOUT = 8–32 MHz
275
375
ps
Characteristics Curves
20
300
290
19
16
15
14
R EFC L K C Y2 5 8 19
13
270
CCJ (ps)
C Y 2 5 8 19
16 - 3 2 M H z
17
R EFC L K C Y2 5 8 18
280
C Y 2 5 8 18
8 - 16 M H z
18
IDD(mA)
The following curves demonstrate the characteristic behavior
of the CY25818/19 when tested over a number of environmental and application specific parameters. These are typical
performance curves and are not meant to replace any
parameter specified in Table 4 and Table 5.
12
260
11
250
10
8
S S C LK C Y2 5 8 19
240
12
16
20
24
28
32
F r e q ue nc y ( M H z )
230
S S C LK C Y2 5 8 18
220
Figure 4. IDD (mA) vs. Frequency (MHz)
210
200
8
12
16
20
24
28
32
F r e q ue nc y ( M H z )
BW (%)
Figure 2. CCJ (ps) vs. Frequency (MHz)
2.75
2.5
BW %
12 MHz
3.1
3
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2
1.9
1.8
[email protected] MHz
[email protected] MHz
2.8
2.25
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
VDD (volts)
32.0 MHz
2
Figure 5. Bandwidth% vs. Vdd
1.75
-40
-25
-10
5
20
35
50
65
80
95
110
125
Temp (C)
Figure 3. Bandwidth% vs. Temperature
Notes:
1. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power-up.
2. Operation at any Absolute Maximum Rating is not implied.
Document #: 38-07362 Rev. *B
Page 4 of 7
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CY25818/19
SSCG Profiles
CY25818/19 SSCG products use a non-linear “optimized”
frequency profile as shown in Figure 6 and Figure 7. The use
of Cypress proprietary “optimized” frequency profile maintains
flat energy distribution over the fundamental and higher order
harmonics. This results in additional EMI reduction in
electronic systems.
Figure 7. CY25819 Spread Spectrum Profile
(Frequency vs. Time)[4]
Figure 6. CY25818 Spread Spectrum Profile
(Frequency vs. Time)[3]
Application Schematic
Vdd
C3
0.1 uF
7
C2
27 pF
C3
1
XIN
Vdd
14.3 MHz
or
27.0 MHz
8
SSCLK
REFCLK
XOUT
27 pF
4
5
14.3 MHz (CY25818)
27.0 MHz (CY25819)
CY25818
CY25819
6
PD#
S0
3
Vss
2
Figure 8. Typical Application Schematic
Notes:
3. XIN = 16.0 MHz; S0 = 1; SSCLK = 16.0 MHz; BW = –2.14%.
4. Xin = 32.0MHz; S0 = 1; SSCLK = 32.0 MHz; BW = -2.15%
Document #: 38-07362 Rev. *B
Page 5 of 7
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CY25818/19
Ordering Information
Part Number
Package Type
Product Flow
CY25818SC
8-pin SOIC
Commercial, 0° to 70°C
CY25818SCT
8-pin SOIC–Tape and Reel
Commercial, 0° to 70°C
CY25819SC
8-pin SOIC
Commercial, 0° to 70°C
CY25819SCT
8-pin SOIC–Tape and Reel
Commercial, 0° to 70°C
CY25818SXC
8-pin SOIC
Commercial, 0° to 70°C
CY25818SXCT
8-pin SOIC–Tape and Reel
Commercial, 0° to 70°C
Lead-free
CY25819SXC
8-pin SOIC
Commercial, 0° to 70°C
CY25819SXCT
8-pin SOIC–Tape and Reel
Commercial, 0° to 70°C
Package Drawing and Dimensions
8-lead (150-Mil) SOIC S8
8 Lead (150 Mil) SOIC - S08
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
RECTANGULAR ON MATRIX LEADFRAME
0.150[3.810]
0.157[3.987]
3. REFERENCE JEDEC MS-012
0.230[5.842]
0.244[6.197]
4. PACKAGE WEIGHT 0.07gms
PART #
S08.15 STANDARD PKG.
5
SZ08.15 LEAD FREE PKG.
8
0.189[4.800]
0.196[4.978]
0.010[0.254]
0.016[0.406]
SEATING PLANE
X 45°
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.004[0.102]
0.0098[0.249]
0°~8°
0.016[0.406]
0.035[0.889]
0.0075[0.190]
0.0098[0.249]
0.0138[0.350]
0.0192[0.487]
51-85066-*C
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-07362 Rev. *B
Page 6 of 7
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY25818/19
Document History Page
Document Title: CY25818/19 Spread Spectrum Clock Generator
Document Number: 38-07362
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
112462
03/21/02
OXC
New Data Sheet
*A
122701
12/28/02
RBI
Added power up requirements to maximum rating information.
*B
448097
See ECN
RGL
Add Lead-free devices
Document #: 38-07362 Rev. *B
Page 7 of 7
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