September 2006 Advance Information AS7C256B ® 5V 32K X 8 CMOS SRAM (Common I/O) Features • Industrial (-40o to 85oC) temperature • Organization: 32,768 words × 8 bits • High speed • 28-pin JEDEC standard packages - 300 mil SOJ - 8 × 13.4 mm TSOP - 300 mil PDIP - 12 ns address access time - 6 ns output enable access time • ESD protection ≥ 2000 volts • Low power consumption via chip deselect • One chip select plus one Output Enable pin • Bidirectional data inputs and outputs • TTL-compatible Logic block diagram Pin arrangement VCC GND I/O7 32,768 X 8 Array (262,144) Sense amp A0 A1 A2 A3 A4 A5 A6 A7 Address decoder Input buffer I/O0 Address decoder WE Control circuit OE CE A A A A A A A 8 9 10 11 12 13 14 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 AS7C256B 28-pin DIP, SOJ (300 mil) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 28-pin TSOP 1 (8×13.4mm) OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 (21) 28 (22) (20) 27 (23) (19) 26 (24) (18) 25 (25) (17) 24 (26) (16) 23 (27) (28) AS7C256B (15) 22 (14) 21 (1) (13) 20 (2) (12) 19 (3) (11) 18 (4) (10) 17 (5) (9) 16 (6) (8) 15 (7) A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 Note: This part is compatible with both pin numbering conventions used by various manufacturers. 12/5/06; V.1.0 Alliance Memory P. 1 of 8 Copyright © Alliance Memory. All rights reserved. AS7C256B ® Functional description The AS7C256B is a 5V high-performance CMOS 262,144-bit Static Random-Access Memory (SRAM) device organized as 32,768 words × 8 bits. It is designed for memory applications requiring fast data access at low voltage, including PentiumTM, PowerPCTM, and portable computing. Alliance’s advanced circuit design and process techniques permit 5.0V operation without sacrificing performance or operating margins. The device enters standby mode when CE is high. Equal address access and cycle times (tAA, tRC, tWC) of 12 ns with output enable access times (tOE) of 6 ns are ideal for high-performance applications. The chip enable (CE) input permits easy memory expansion with multiple-bank memory organizations. A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting chip enable (CE) and output enable (OE) LOW, with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write enable is low, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible. Operation is from a single 5.0±0.5V supply. The AS7C256B is packaged in high volume industry standard packages. Absolute maximum ratings Parameter Symbol Min Max Unit Voltage on VCC relative to GND Vt1 –0.5 +7.0 V Voltage on any pin relative to GND Vt2 –0.5 VCC + 0.5 V Power dissipation PD – 1.25 W Storage temperature (plastic) Tstg –55 +125 oC Ambient temperature with VCC applied Tbias –55 +125 o DC current into outputs (low) IOUT – 50 C mA Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE WE OE Data Mode H X X High Z Standby (ISB, ISB1) L H H High Z Output disable (ICC) L H L DOUT Read (ICC) L L X DIN Write (ICC) Notes: H = VIH, L = VIL, x = Don’t care. VLC = 0.2V, VHC = VCC - 0.2V. Other inputs ≥ VHC or VLC. 12/5/06; V.1.0 Alliance Memory P. 2 of 8 AS7C256B ® Recommended operating conditions Parameter Symbol Min Typical Max Unit VCC 4.5 5.0 5.5 V Supply voltage Input voltage VIH 2.2 – VCC+0.5 V VIL(1) -0.5(1) – 0.8 V TA –40 – 85 o Ambient operating temperature (Industrial) C Note: 1 VIL min = –1.5V for pulse width less than 10ns, once per cycle. DC operating characteristics (over the operating range)1 AS7C256B-12 Parameter Symbol Test conditions Min Max Unit Input leakage current |ILI| VCC = Max, Vin = GND to VCC – 5 µA Output leakage current |ILO| VCC = Max, CS = VIH, VOUT = GND to VCC – 5 µA Operating power supply current ICC – 160 mA VCC = Max, CE ≤ VIL f = fMax, IOUT = 0mA ISB VCC = Max, CE > VIH f = fMax, IOUT = 0mA – 50 mA ISB1 VCC = Max, CE > VCC–0.2V VIN < GND + 0.2V or VIN > VCC–0.2V, f = 0(2) – 15 mA VOL IOL = 8 mA, VCC = Min – 0.4 V VOH IOH = –4 mA, VCC = Min 2.4 – V Standby power supply current Output voltage Notes: All values are maximum guaranteed values. fMax = 1/tRC, only address inputs cycling at fMax, f = 0 means that no inputs are cycling. Capacitance (f = 1MHz, Ta = room temperature, VCC = NOMINAL)2 Parameter Symbol Signals Test conditions Max Unit Input capacitance CIN A, CE, WE, OE Vin = 3dV 7 pF I/O capacitance CI/O I/O Vout = 3dV 7 pF Note: This parameter is guaranteed by device characterization, but is not production tested. 12/5/06; V.1.0 Alliance Memory P. 3 of 8 AS7C256B ® Read cycle (over the operating range)3,9 AS7C256B-12 Parameter Symbol Min Max Unit Notes Read cycle time tRC 12 – ns Address access time tAA – 12 ns 3 Chip enable (CE) access time tACE – 12 ns 3 Output enable (OE) access time tOE – 6 ns Output hold from address change tOH 3 – ns 5 CE LOW to output in low Z tCLZ 4 – ns 4, 5 CE HIGH to output in high Z tCHZ 0 6 ns 4, 5 OE LOW to output in low Z tOLZ 0 – ns 4, 5 OE HIGH to output in high Z tOHZ 0 6 ns 4, 5 Power up time tPU 0 – ns 4, 5 Power down time tPD – 12 ns 4, 5 Key to switching waveforms Rising input Falling input Undefined output/don’t care Read waveform 1 (address controlled)3,6,7,9 tRC Address tOH tAA Dout Data valid Read waveform 2 (CE controlled)3,6,8,9 tRC CE tOE OE tOLZ tOHZ tCHZ tACE Dout Data valid tCLZ Supply current 12/5/06; V.1.0 tPU tPD 50% ICC ISB 50% Alliance Memory P. 4 of 8 AS7C256B ® Write cycle (over the operating range)11 AS7C256B-12 Parameter Symbol Min Max Unit Notes Write cycle time tWC 12 – ns Chip enable to write end tCW 9 – ns Address setup to write end tAW 9 – ns Address setup time tAS 0 – ns Write pulse width tWP 8 – ns Write recovery time tWR 0 – ns Address hold from end of write tAH 0 – ns Data valid to write end tDW 6 – ns Data hold time tDH 0 – ns 4, 5 Write enable to output in high Z tWZ 0 6 ns 4, 5 Output active from write end tOW 4 – ns 4, 5 Shaded areas contain advance information. Write waveform 1 (WE controlled)10,11 tWC tAW tAH tWR Address tWP WE tAS tDW tDH Data valid Din tWZ tOW Dout Write waveform 2 (CE controlled)10,11 tWC tAW tAH tWR Address tAS tCW CE tWP WE tWZ Din tDW tDH Data valid Dout 12/5/06; V.1.0 Alliance Memory P. 5 of 8 AS7C256B ® AC test conditions - Output load: see Figure B. Input pulse level: GND to VCC. See Figure A. Input rise and fall times: 3 ns. See Figure A. Input and output timing reference levels: 1.5V. Thevenin equivalent 168Ω Dout +1.72V (5V) VCC 480Ω VCC GND 90% 10% Dout 255Ω 90% 3 ns 10% C(13) GND Figure B: Output load Figure A: Input pulse Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. This parameter is sampled, but not 100% tested. For test conditions, see AC Test Conditions, Figures A and B. These parameters are specified with CL = 5pF, as in Figures B. Transition is measured ±200mV from steady-state voltage. This parameter is guaranteed, but not tested. WE is High for read cycle. CE and OE are Low for read cycle. Address valid prior to or coincident with CE transition Low. All read cycle timings are referenced from the last valid address to the first transitioning address. CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle. All write cycle timings are referenced from the last valid address to the first transitioning address. CE1 and CE2 have identical timing. C=30pF, except on High Z and Low Z parameters, where C=5pF. 12/5/06; V.1.0 Alliance Memory P. 6 of 8 AS7C256B ® Package diagrams 28-pin SOJ Min Max in mils D e A A1 A2 B b c D E E1 E2 e B A A1 E1 E2 Seating Plane b Pin 1 c A2 E2 c A2 L pin 1(22) D Hd 0.140 - 0.095 0.105 0.028 TYP 0.018 TYP 0.010 TYP - 0.730 0.245 0.285 0.295 0.305 0.327 0.347 0.050 BSC 28-pin TSOP 8×13.4 mm Min Max e b 0.025 A A1 pin 8(21) α pin 1(7) pin 5(8) 28-pin A A1 – 1.20 0.10 0.20 A2 0.95 1.05 b c D e E Hd L 0.15 0.25 α 0.10 0.20 11.60 11.80 0.55 nominal 8.0 nominal 13.30 13.50 0.50 0.70 0° 5° E 28-pin PDIP Min Max in mils A D B S E1 E α L e Pin 1 A1 b Seating Plane Note: This part is compatible with both pin numbering conventions used by various manufacturers. 12/5/06; V.1.0 Alliance Memory eA c A A1 B b c D E E1 e eA L a S - 0.180 0.010 - 0.040 0.065 0.014 0.022 0.008 0.014 - 1.400 0.295 0.320 0.278 0.298 0.100 BSC 0.330 0.380 0.120 0.140 0° 15° - 0.055 P. 7 of 8 AS7C256B ® Ordering information Volt/Temp 12 ns Plastic DIP, 300 mil Package 5V industrial AS7C256B-12PIN Plastic SOJ, 300 mil 5V industrial AS7C256B-12JIN TSOP 8x13.4 mm 5V industrial AS7C256B-12TIN Part numbering system AS7C SRAM prefix 256B –XX Device number Access time X I X Package: P=DIP 300 mil Temperature range: J=SOJ 300 mil I = -40C to 85C T=TSOP 8x13.4 mm N=Lead Free Part ® Alliance Memory, Inc. 1116 South Amphlett San Mateo, CA 94402 Tel: 650-525-3737 Fax: 650-525-0449 Copyright © Alliance Memory All Rights Reserved Part Number: AS7C256B Document Version: v.1.0 www.alliancememory.com © Copyright 2003 Alliance Memory, Inc. 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