TI SN74CBT16211

SN74CBT16211
24-BIT BUS SWITCH
SCDS028E – JULY 1995 – REVISED APRIL 1997
D
D
D
5-Ω Switch Connection Between Two Ports
TTL-Compatible Input and Output Levels
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
NC
1A1
1A2
1A3
1A4
1A5
1A6
GND
1A7
1A8
1A9
1A10
1A11
1A12
2A1
2A2
VCC
2A3
GND
2A4
2A5
2A6
2A7
2A8
2A9
2A10
2A11
2A12
description
The SN74CBT16211 provides 24 bits of
high-speed TTL-compatible bus switching. The
low on-state resistance of the switch allows
connections to be made with minimal propagation
delay.
The device operates as a 12-bit or 24-bit bus
switch. When 1OE is low, 1A is connected to 1B.
When 2OE is low, 2A is connected to 2B.
The SN74CBT16211 is characterized
operation from –40°C to 85°C.
for
FUNCTION TABLE
INPUTS
INPUTS/OUTPUTS
1OE
2OE
1A, 1B
2A, 2B
L
L
1A = 1B
2A = 2B
L
H
1A = 1B
Z
H
L
Z
2A = 2B
H
H
Z
Z
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1OE
2OE
1B1
1B2
1B3
1B4
1B5
GND
1B6
1B7
1B8
1B9
1B10
1B11
1B12
2B1
2B2
2B3
GND
2B4
2B5
2B6
2B7
2B8
2B9
2B10
2B11
2B12
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
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1
SN74CBT16211
24-BIT BUS SWITCH
SCDS028E – JULY 1995 – REVISED APRIL 1997
logic diagram (positive logic)
2
54
1A1
1B1
14
42
1A12
1OE
1B12
56
15
41
2A1
2B1
28
2A12
29
2B12
55
2OE
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
recommended operating conditions
2
MIN
MAX
5.5
VCC
VIH
Supply voltage
4
High-level control input voltage
2
VIL
TA
Low-level control input voltage
Operating free-air temperature
–40
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• DALLAS, TEXAS 75265
UNIT
V
V
0.8
V
85
°C
SN74CBT16211
24-BIT BUS SWITCH
SCDS028E – JULY 1995 – REVISED APRIL 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
II
ICC
∆ICC‡
Control pins
Ci
Control pins
Cio(OFF)
ron§
TEST CONDITIONS
VCC = 4.5 V,
VCC = 0 V,
II = –18 mA
VI = 5.5 V
VCC = 5.5 V,
VCC = 5.5 V,
VI = 5.5 V or GND
IO = 0,
VCC = 5.5 V,
VI = 3 V or 0
One input at 3.4 V,
VO = 3 V or 0,
VCC = 4 V,
OE = VCC
VCC = 4.5 V
MIN
TYP†
MAX
UNIT
–1.2
V
10
±1
VI = VCC or GND
Other inputs at VCC or GND
µA
3
µA
2.5
mA
4.5
pF
5.5
pF
VI = 2.4 V,
II = 15 mA
14
20
VI = 0
II = 64 mA
II = 30 mA
5
7
5
7
Ω
VI = 2.4 V,
II = 15 mA
8
12
† All typical values are at VCC = 5 V, TA = 25°C.
‡ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
§ Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lowest voltage of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
tpd¶
A or B
B or A
ten
OE
A or B
PARAMETER
VCC = 5 V
± 0.5 V
VCC = 4 V
MIN
MIN
3.9
MAX
UNIT
MAX
0.25
0.25
ns
9.3
10.1
ns
tdis
OE
A or B
3.3
8.5
7.1
ns
¶ This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical on-state resistance
of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance).
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN74CBT16211
24-BIT BUS SWITCH
SCDS028E – JULY 1995 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
7V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
500 Ω
3V
Output Control
(low-level
enabling)
LOAD CIRCUIT
1.5 V
1.5 V
0V
tPZL
3V
Input
1.5 V
1.5 V
0V
tPLH
1.5 V
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
3.5 V
VOL + 0.3 V
VOL
tPHZ
tPZH
tPHL
VOH
Output
tPLZ
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
1.5 V
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 Ω, tr 2.5 ns, tf 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
v
Figure 1. Load Circuit and Voltage Waveforms
4
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• DALLAS, TEXAS 75265
v
v
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Copyright  1999, Texas Instruments Incorporated