CY23S09, CY23S05 Low Cost 3.3V Spread Aware Zero Delay Buffer Features ■ 10 MHz to 100 and 133 MHz operating range, compatible with CPU and PCI bus frequencies ■ Zero input-output propagation delay ■ Multiple low skew outputs ❐ Output-output skew less than 250 ps ❐ Device-device skew less than 700 ps ❐ One input drives five outputs (CY23S05) ❐ One input drives nine outputs, grouped as 4 + 4 + 1 (CY23S09) ■ Less than 200 ps cycle-to-cycle jitter is compatible with Pentium® based systems ■ Test mode to bypass PLL (CY23S09 only, see Select Input Decoding for CY23S09 on page 2) ■ Available in space saving 16-pin, 150-mil SOIC, 4.4 mm TSSOP, and 150-mil SSOP ( CY23S09) or 8-pin, 150-mil SOIC package (CY23S05) ■ 3.3V operation, advanced 0.65μ CMOS technology ■ Spread Aware Functional Description The CY23S09 is a low cost 3.3V zero delay buffer designed to distribute high speed clocks and is available in a 16-pin SOIC package. The CY23S05 is an 8-pin version of the CY23S09. It accepts one reference input, and drives out five low skew clocks. The -1H versions of each device operate at up to 100 and 133 MHz frequencies and have higher drive than the -1 devices. All parts have on-chip PLLs that lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The CY23S09 has two banks of four outputs each, which can be controlled by the select inputs as shown in the Select Input Decoding table on Select Input Decoding for CY23S09 on page 2. If all output clocks are not required, Bank B can be three-stated. The select inputs also allow the input clock to be directly applied to the outputs for chip and system testing purposes. The CY23S09 and CY23S05 PLLs enter a power down mode when there are no rising edges on the REF input. In this state, the outputs are three-stated and the PLL is turned off, resulting in less than 12.0 μA of current draw (for commercial temperature devices) and 25.0 μA (for industrial temperature devices). The CY23S09 PLL shuts down in one additional case, as shown in the Select Input Decoding for CY23S09 on page 2. Multiple CY23S09 and CY23S05 devices can accept the same input clock and distribute it. In this case, the skew between the outputs of two devices is guaranteed to be less than 700 ps. All outputs have less than 200 ps of cycle-to-cycle jitter. The input to output propagation delay on both devices is guaranteed to be less than 350 ps; the output to output skew is guaranteed to be less than 250 ps. The CY23S05 and CY23S09 is available in two different configurations, as shown in the Ordering Information on page 6. The CY23S05-1 and CY23S09-1 is the base part. The CY23S05-1H and CY23S09-1H is the high drive version of the -1, and its rise and fall times are much faster than -1. Logic Block Diagram Cypress Semiconductor Corporation Document Number: 38-07296 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised October 22, 2008 [+] Feedback CY23S09, CY23S05 Select Input Decoding for CY23S09 S2 S1 CLOCK A1–A4 CLOCK B1–B4 CLKOUT[1] Output Source PLL Shut-down 0 0 Three-state Three-state Driven PLL N 0 1 Driven Three-state Driven PLL N 1 0 Driven Driven Driven Reference Y 1 1 Driven Driven Driven PLL N Zero Delay and Skew Control Spread Aware All outputs must be uniformly loaded to achieve Zero Delay between the input and output. Because the CLKOUT pin is the internal feedback to the PLL, its relative loading can adjust the input-output delay. This is shown in the above graph. Many systems being designed now use a technology called Spread Spectrum Frequency Timing Generation. Cypress is one of the pioneers of SSFTG development and designed this product so as not to filter off the Spread Spectrum feature of the Reference input, assuming it exists. When a zero delay buffer is not designed to pass the SS feature through, the result is a significant amount of tracking skew, which may cause problems in systems requiring synchronization. For applications requiring zero input-output delay, all outputs, including CLKOUT, must be equally loaded. Even if CLKOUT is not used, it must have a capacitive load equal to that on other outputs, to obtain zero input-output delay. If input to output delay adjustments are required, use the above graph to calculate loading differences between the CLKOUT pin and other outputs. For zero output-output skew, be sure to load all outputs equally. For further information, refer to the application note “CY23S05 and CY23S09 as PCI and SDRAM Buffers.” For more details on Spread Spectrum timing technology, please see the Cypress application note AN1278, EMI Suppression Techniques with Spread Spectrum Frequency Timing Generator (SSFTG) ICs. Pin Configurations Figure 1. Pin Diagram - CY23S09 Figure 2. Pin Diagram - CY23S05 Note 1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output. Document Number: 38-07296 Rev. *D Page 2 of 9 [+] Feedback CY23S09, CY23S05 Pin Description for CY23S09 Pin Signal Description 1 REF[2] Input reference frequency, 5V tolerant input 2 CLKA1[3] Buffered clock output, bank A 3 CLKA2[3] Buffered clock output, bank A 4 VDD 3.3V supply 5 GND Ground 6 CLKB1[3] Buffered clock output, bank B 7 CLKB2[3] Buffered clock output, bank B 8 S2[4] Select input, bit 2 9 S1[4] Select input, bit 1 10 CLKB3[3] Buffered clock output, bank B 11 CLKB4[3] Buffered clock output, bank B 12 GND Ground 13 VDD 3.3V supply 14 CLKA3[3] Buffered clock output, bank A 15 CLKA4[3] Buffered clock output, bank A 16 CLKOUT[3] Buffered output, internal feedback on this pin Pin Description for CY23S05 Pin Signal Description 1 REF[2] Input reference frequency, 5V tolerant input 2 CLK2[3] Buffered clock output 3 CLK1[3] Buffered clock output 4 GND Ground 5 CLK3[3] Buffered clock output 6 VDD 3.3V supply 7 CLK4[3] Buffered clock output 8 CLKOUT[3] Buffered clock output, internal feedback on this pin Notes 2. Weak pull-down. 3. Weak pull-down on all outputs. 4. Weak pull-up on these inputs. Document Number: 38-07296 Rev. *D Page 3 of 9 [+] Feedback CY23S09, CY23S05 Storage Temperature ................................. –65°C to +150°C Maximum Ratings Supply Voltage to Ground Potential................–0.5V to +7.0V DC Input Voltage (Except REF) ............ –0.5V to VDD + 0.5V DC Input Voltage REF ............................................. −0.5V to 7V Maximum Soldering Temperature (10 seconds)......... 260°C Junction Temperature ................................................. 150°C Static Discharge Voltage (per MIL-STD-883, Method 3015) ........................... > 2,000V Operating Conditions for CY23S05SC-XX and CY23S09SC-XX Commercial Temperature Devices[5] Parameter Description Min Max Unit 3.0 3.6 V 0 70 °C 30 pF Load Capacitance, from 100 MHz to 133 MHz 10 pF Input Capacitance 7 pF VDD Supply Voltage TA Operating Temperature (Ambient Temperature) CL Load Capacitance, below 100 MHz CL CIN Electrical Characteristics for CY23S05SC-XX and CY23S09SC-XX Commercial Temperature Devices Parameter Description VIL Input LOW Voltage[6] Voltage[6] Test Conditions Min Max Unit 0.8 V VIN = 0V 50.0 μA 100.0 μA 0.4 V VIH Input HIGH IIL Input LOW Current 2.0 IIH Input HIGH Current VIN = VDD VOL Output LOW Voltage[7] IOL = 8 mA (–1) IOH = 12 mA (–1H) VOH Output HIGH Voltage[7] IDD (PD mode) Power Down Supply Current REF = 0 MHz 12.0 μA IDD Supply Current Unloaded outputs at 66.67 MHz, SEL inputs at VDD 32.0 mA IOH = –8 mA (–1) IOL = –12 mA (–1H) V 2.4 V Switching Characteristics for CY23S05SC-1 and CY23S09SC-1 Commercial Temperature Devices [8] Parameter t1 Description Test Conditions Max Unit 100 133.33 MHz MHz 60.0 % Measured between 0.8V and 2.0V 2.50 ns Measured between 0.8V and 2.0V 2.50 ns Output Frequency 30 pF load 10 pF load Duty Cycle[7] = t2 ÷ t1 Measured at 1.4V, Fout = 66.67 MHz Time[7] t3 Rise t4 Fall Time[7] Skew[7] Min Typ 10 10 40.0 50.0 t5 Output-to-Output 250 ps t6 Delay, REF Rising Edge to Measured at VDD/2 CLKOUT Rising Edge[7] 0 ±350 ps t7 Device-to-Device Skew[7] Measured at VDD/2 on the CLKOUT pins of devices 0 700 ps tJ Cycle-to-Cycle Jitter[7] Measured at 66.67 MHz, loaded outputs 200 ps Stable power supply, valid clock presented on REF pin 1.0 ms tLOCK [7] PLL Lock Time All outputs equally loaded Notes 5. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power up. Power supply sequencing is NOT required. 6. REF input has a threshold voltage of VDD/2. 7. Parameter is guaranteed by design and characterization. Not 100% tested in production. 8. All parameters specified with loaded outputs. Document Number: 38-07296 Rev. *D Page 4 of 9 [+] Feedback CY23S09, CY23S05 Switching Characteristics for CY23S05SI-1H and CY23S09SI-1H Industrial Temperature Devices[8] Parameter t1 Description Test Conditions Min Typ Output Frequency 30 pF load 10 pF load Duty Cycle[7] = t2 ÷ t1 Measured at 1.4V, Fout = 66.67 MHz 40.0 50.0 Measured at 1.4V, Fout <50.0 MHz 45.0 50.0 [7] Duty Cycle = t2 ÷ t1 10 10 Max Unit 100 133.33 MHz MHz 60.0 % 55.0 % t3 Rise Time[7] Measured between 0.8V and 2.0V 1.50 ns t4 Fall Time[7] Measured between 0.8V and 2.0V 1.50 ns t5 Output-to-Output Skew[7] All outputs equally loaded 250 ps t6 Delay, REF Rising Edge to Measured at VDD/2 CLKOUT Rising Edge[7] 0 ±350 ps t7 Device-to-Device Skew[7] Measured at VDD/2 on the CLKOUT pins of devices 0 700 ps t8 Output Slew Rate[7] Measured between 0.8V and 2.0V using Test Circuit #2 tJ Cycle-to-Cycle Jitter[7] Measured at 66.67 MHz, loaded outputs 200 ps tLOCK PLL Lock Time[7] Stable power supply, valid clock presented on REF pin 1.0 ms 1 V/ns Switching Waveforms Duty Cycle Timing t1 t2 1.4V 1.4V 1.4V All Outputs Rise/Fall Time OUTPUT 2.0V 0.8V 2.0V 0.8V 3.3V 0V t4 t3 Output-Output Skew OUTPUT 1.4V 1.4V OUTPUT t5 Input-Output Propagation Delay INPUT VDD/2 VDD/2 OUTPUT t6 Document Number: 38-07296 Rev. *D Page 5 of 9 [+] Feedback CY23S09, CY23S05 Switching Waveforms continued Device-Device Skew VDD/2 CLKOUT, Device 1 VDD/2 CLKOUT, Device 2 2309–8 t7 Test Circuits Test Circuit # 2 Test Circuit # 1 V DD V DD 0.1 μF 0.1 μF CLK out OUTPUTS GND 1 kW V DD V DD GND OUTPUTS 10 pF C LOAD 0.1 μF 1 kW 0.1 μF GND GND For parameter t8 (output slew rate) on –1H devices Ordering Information Ordering Code CY23S05SC-1 Package Name S8 Package Type Operating Range 8-pin 150-mil SOIC Commercial Status Active CY23S05SC-1H S8 8-pin 150-mil SOIC Commercial Obsolete CY23S09SC-1 S16 16-pin 150-mil SOIC Commercial Obsolete CY23S09SC-1H S16 16-pin 150-mil SOIC Commercial Obsolete CY23S09ZC-1 Z16 16-pin 4.4 mm TSSOP Commercial Obsolete CY23S09ZC-1H Z16 16-pin 4.4 mm TSSOP Commercial Obsolete CY23S09OC-1 O16 16-pin 150-mil SSOP Commercial Obsolete CY23S09OC-1H O16 16-pin 150-mil SSOP Commercial Obsolete Pb-Free CY23S05SXC-1 S8 8-pin 150-mil SOIC Commercial Active CY23S05SXC-1H S8 8-pin 150-mil SOIC Commercial Active CY23S09SXC-1 S16 16-pin 150-mil SOIC Commercial Active CY23S09SXC-1H S16 16-pin 150-mil SOIC Commercial Active CY23S09ZXC-1 Z16 16-pin 4.4 mm TSSOP Commercial Obsolete CY23S09ZXC-1H Z16 16-pin 4.4 mm TSSOP Commercial Active CY23S09OXC-1 O16 16-pin 150-mil SSOP Commercial Obsolete CY23S09OXC-1H O16 16-pin 150-mil SSOP Commercial Obsolete Document Number: 38-07296 Rev. *D Page 6 of 9 [+] Feedback CY23S09, CY23S05 Package Diagrams Figure 3. 8-Pin (150-Mil) SOIC S8 8 Lead (150 Mil) SOIC - S08 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 0.150[3.810] 0.157[3.987] 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. 5 SZ08.15 LEAD FREE PKG. 8 0.189[4.800] 0.196[4.978] 0.010[0.254] 0.016[0.406] SEATING PLANE X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0°~8° 0.0075[0.190] 0.0098[0.249] 0.016[0.406] 0.035[0.889] 0.0138[0.350] 0.0192[0.487] 16 Lead (150 Mil) SOIC 51-85066-*C Figure 4. 16-Pin (150-Mil) SOIC S16.15 PIN 1 ID 8 1 DIMENSIONS IN INCHES[MM] MIN. MAX. REFERENCE JEDEC MS-012 PACKAGE WEIGHT 0.15gms 0.150[3.810] 0.157[3.987] 0.230[5.842] 0.244[6.197] PART # S16.15 STANDARD PKG. SZ16.15 LEAD FREE PKG. 9 16 0.386[9.804] 0.393[9.982] 0.010[0.254] 0.016[0.406] SEATING PLANE X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0°~8° 0.0138[0.350] 0.0192[0.487] Document Number: 38-07296 Rev. *D 0.004[0.102] 0.0098[0.249] 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 51-85068-*B Page 7 of 9 [+] Feedback CY23S09, CY23S05 Package Diagrams continued Figure 5. 16-Pin TSSOP 4.40 mm Body Z16.173 PIN 1 ID DIMENSIONS IN MM[INCHES] MIN. MAX. 1 REFERENCE JEDEC MO-153 6.25[0.246] 6.50[0.256] PACKAGE WEIGHT 0.05 gms PART # 4.30[0.169] 4.50[0.177] Z16.173 STANDARD PKG. ZZ16.173 LEAD FREE PKG. 16 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0°-8° 0.076[0.003] 0.85[0.033] 0.95[0.037] 4.90[0.193] 5.10[0.200] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 51-85091-*A Figure 6. 16-Pin (150-Mil) QSOP Q1 51-85053-*B Document Number: 38-07296 Rev. *D Page 8 of 9 [+] Feedback CY23S09, CY23S05 Document History Page Document Title: CY23S09/CY23S05 Low Cost 3.3V Spread Aware Zero Delay Buffer Document Number: 38-07296 Rev. ECN No. Submission Date Orig. of Change ** 111147 11/14/01 DSG *A 111773 02/20/02 CTK Added 150-mil SSOP option *B 122885 12/22/02 RBI Added power-up requirements to Operating Conditions *C 267849 See ECN RGL Added Lead-Free devices *D 2595524 10/23/08 Description of Change Changed from spec number 38-01094 to 38-07296 CXQ/PYRS Added device “Status” to Ordering Information Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. 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Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-07296 Rev. *D Revised October 22, 2008 Page 9 of 9 Pentium is a registered trademark of Intel Corporation. Spread Aware is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback