PRELIMINARY W48S87-04 Spread Spectrum 3 DIMM Desktop Clock Features Key Specifications • Outputs — 4 CPU Clock (2.5V or 3.3V, 50 to 83.3 MHz) — 7 PCI (3.3V) — 1 48-MHz for USB (3.3V) — 1 24-MHz for Super I/O (3.3V) — 2 REF (3.3V) — 1 IOAPIC (2.5V or 3.3V) — 12 SDRAM • Serial data interface provides additional frequency selection, individual clock output disable, and other functions • Smooth transition supports dynamic frequency assignment • Frequency selection not affected during power down/up cycle • Supports a variety of power-saving options • 3.3V operation • Available in 48-pin SSOP (300 mils) ±0.5% Spread Spectrum Modulation: ......................... ±0.5% Jitter (Cycle-to-Cycle): .................................................250 ps Duty Cycle: ................................................................ 45-55% CPU-PCI Skew: ........................................................ 1 to 4 ns PCI-PCI or CPU-CPU Skew: .......................................250 ps Table 1. Pin Selectable Frequency[1] Input Address FS2 FS1 FS0 CPU, SDRAM Clocks (MHz) PCI Clocks (MHz) 0 0 0 50.0 25.0 0 0 1 75.0 32.0 0 1 0 83.3 41.65 0 1 1 68.5 34.25 1 0 0 55.0 27.5 1 0 1 75.0 37.5 1 1 0 60.0 30.0 1 1 1 66.8 33.4 Pin Configuration [2] Block Diagram SDATA SCLOCK Serial Port Device Control PLL Ref Freq X1 X2 XTAL OSC VDD1 CPU Clock Mode Control FS0 FS1 FS2 Freq Select I/O REF0/CPU3.3#_2.5 REF1(CPU_STOP#) MODE VDDL1 IOAPIC PLL1 VDDL2 Stop Clock Cntrl 4 CPU0:3 VDD3 CPU_STOP# 12 ÷2 VDD2 I/O I/O 4 PWR_DWN# SDRAM0:11 Power Down Control MODE ÷2 PLL2 ÷4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 W48S87-04 CPU3.3#_2.5 VDD1 REF0/CPU3.3#_2.5 GND X1 X2 VDD2 PCI_F/FS1 PCI0/FS2 GND PCI1 PCI2 PCI3 PCI4 VDD2 PCI5(PWR_DWN#) GND SDRAM11 SDRAM10 VDD3 SDRAM9 SDRAM8 GND SDATA SCLOCK 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDL1 IOAPIC REF1(CPU_STOP#) GND CPU0 CPU1 VDDL2 CPU2 CPU3 GND SDRAM0 SDRAM1 VDD3 SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDD3 SDRAM6 SDRAM7 GND 48MHZ/FS0 24MHZ/MODE PCI_F/FS1 PCI0/FS2 PCI1:4 PCI5(PWR_DWN#) VDD1 I/O I/O 48MHZ/FS0 24MHZ/MODE Notes: 1. Additional frequency selections provided by serial data interface; refer to Table 5 on page 10. 2. Signal names in parenthesis denotes function is selectable through mode pin register strapping. Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 October 19, 1999, rev. ** PRELIMINARY W48S87-04 Pin Definitions Pin Name CPU0:3 PCI_F/FS1 Pin No. Pin Type 44, 43, 41, 40 O CPU Clock Outputs 0 through 3: These four CPU clock outputs are controlled by the CPU_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDL2 and output characteristics are adjusted by input CPU3.3#_2.5. 7 I/O Fixed PCI Clock Output and Frequency Selection Bit 1: As an output, this pin works in conjunction with PCI0:5. Output voltage swing is controlled by voltage applied to VDD2. Pin Description When an input, this pin functions as part of the frequency selection address. The value of FS0:2 determines the power-up default frequency of device output clocks as per the Table 1, “Pin Selectable Frequency” on page 1. PCI0/FS2 8 I/O PCI Bus Clock Output 0 and Frequency Selection Bit 2: As an output, this pin works in conjunction with PCI1:5 and PCI_F. Output voltage swing is controlled by voltage applied to VDD2. When an input, this pin functions as part of the frequency selection address. The value of FS0:2 determines the power-up default frequency of device output clocks as per the Table 1, “Pin Selectable Frequency” on page 1. PCI1:4 PCI5(PWR_DWN#) 10, 11, 12, 13 O PCI Bus Clock Outputs 1 through 4: Output voltage swing is controlled by voltage applied to VDD2. 15 I/O PCI Bus Clock Output 5 or Power-Down Control: As an output, this pin works in conjunction with PCI0:4 and PCI_F. Output voltage swing is controlled by voltage applied to VDD2. If programmed as an input (refer to MODE pin description), this pin is used for power-down control. When LOW, the device goes into a low-power standby condition. All outputs are actively held LOW while in power-down. CPU, SDRAM, and PCI clock outputs are stopped LOW after completing a full clock cycle (2–4 CPU clock cycle latency). When brought HIGH, CPU, SDRAM, and PCI outputs start with a full clock cycle at full operating frequency (3 ms maximum latency). 38, 37, 35, 34, 32, 31, 29, 28, 21, 20, 18, 17 O SDRAM Clock Outputs 0 through 11: These twelve SDRAM clock outputs run synchronous to the CPU clock outputs. Output voltage swing is controlled by voltage applied to VDD3. IOAPIC 47 O I/O APIC Clock Output: Provides 14.318-MHz fixed frequency. The output voltage swing is controlled by VDDL1. 48MHZ/FS0 26 I/O 48-MHz Output and Frequency Selection Bit 0: Fixed clock output that defaults to 48 MHz following device power-up. Output voltage swing is controlled by voltage applied to VDD1. SDRAM0:11 When an input, this pin functions as part of the frequency selection address. The value of FS0:2 determines the power-up default frequency of device output clocks as per the Table 1, “Pin Selectable Frequency” on page 1. 24MHZ/MODE 25 I/O 24-MHz Output and Mode Control Input: Fixed clock output that defaults to 24 MHz following device power-up. Output voltage swing is controlled by voltage applied to VDD1. When an input, this pin is used for pin programming selection. It determines the functions for pins 15 and 46: MODE Pin 15 0 1 PWR_DWN# (input) PCI5 (output) 2 Pin 46 CPU_STOP# (input) REF1 (output) PRELIMINARY W48S87-04 Pin Definitions (continued) Pin Name REF0/CPU3.3#_2.5 Pin No. Pin Type 2 I/O Pin Description Fixed 14.318-MHz Output 0 and CPU Output Voltage Swing Selection Input: As an output, this pin is used for various system applications. Output voltage swing is controlled by voltage applied to VDD1. REF0 is stronger than REF1 and should be used for driving ISA slots. When an input, this pin selects the CPU clock output buffer characteristics that are optimized for either 3.3V or 2.5V operation. CPU3.3#_2.5 0 1 VDDQ2 Voltage (CPU0:3 Swing) 3.3V 2.5V This input adjusts CPU clock output impedance so that a nominal 20Ω output impedance is maintained. This eliminates or reduces the need to adjust external clock tuning components when changing VDDL2 voltage. CPU clock phase is also adjusted so that both CPU and SDRAM and CPU-to-PCI clock skew is maintained over the two VDDL2 voltage options. This input does not adjust IOAPIC clock output characteristics. REF1(CPU_Stop#) 46 I/O Fixed 14.318-MHz Output 0 or CPU Clock Output Stop Control: Used for various system applications. Output voltage swing is controlled by voltage applied to VDD1. REF0 is stronger than REF1 and should be used for driving ISA slots. If programmed as an input (refer to MODE pin description), this pin is used for stopping the CPU clock outputs. When brought LOW, clock outputs CPU0:3 are stopped LOW after completing a full clock cycle (2–3 CPU clock latency). When brought HIGH, clock outputs CPU0:3 are starting beginning with a full clock cycle (2–3 CPU clock latency). X1 4 I Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. X2 5 I Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. SDATA 23 I Serial Data Input: Data input for Serial Data Interface. Refer to Serial Data Interface section that follows. SCLOCK 24 I Serial Clock Input: Clock input for Serial Data Interface. Refer to Serial Data Interface section that follows. VDD1 1 P Power Connection: Power supply for crystal oscillator and REF0:1 output buffers. Connected to 3.3V supply. VDD2 6,14 P Power Connection: Power supply for PCI clock output buffers. Connected to 3.3V supply. VDDL1 48 P Power Connection: Power supply for IOAPIC output buffer. Connected to 2.5V or 3.3V supply. VDDL2 42 P Power Connection: Power supply for CPU clock output buffers. Connected to 2.5V or 3.3V supply. VDD3 19, 30, 36 P Power Connection: Power supply for SDRAM clock output buffers. Connected to 3.3V supply. GND 3, 9, 16, 22, 27, 33, 39, 45 G Ground Connection: Connect all ground pins to the common system ground plane. 3 PRELIMINARY W48S87-04 I/O pins are three-stated, allowing the output strapping resistor on each l/O pin to pull the pin and its associated capacitive clock load to either a logic HIGH or LOW state. At the end of the 2-ms period, the established logic 0 or 1 condition of each l/O is pin is then latched. Next the output buffers are enabled, which converts the l/O pins into operating clock outputs. The 2-ms timer is started when VDD reaches 2.0V. The input bits can only be reset by turning VDD off and then back on again. Overview The W48S87-04, a motherboard clock synthesizer, can provide either a 2.5V or 3.3V CPU clock swing, making it suitable for a variety of CPU options. Twelve SDRAM clocks are provided in phase with the CPU clock outputs. This provides clock support for up to three SDRAM DlMMs. Fixed output frequency clocks are provided for other system functions. It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive impedance of both clock outputs is <40Ω (nominal) which is minimally affected by the 10-kΩ strap to ground or VDD. As with the series termination resistor, the output strapping resistor should be placed as close to the l/O pin as possible in order to keep the interconnecting trace short. The trace from the resistor to ground or VDD should be kept less than two inches in length to prevent system noise coupling during input logic sampling. Functional Description I/O Pin Operation Pins 2, 7, 8, 25, and 26 are dual-purpose l/O pins. Upon powerup these pins act as logic inputs, allowing the determination of assigned device functions. A short time after power-up, the logic state of these pins is latched and the pins then become clock outputs. This feature reduces device pin count by combining clock outputs with input select pins. When the clock outputs are enabled following the 2-ms input period, target (normal) output frequency is delivered assuming that VDD has stabilized. If VDD has not yet reached full value, output frequency initially may be below target but will increase to target once VDD voltage has stabilized. In either case, a short output clock cycle may be produced from the CPU clock outputs when the outputs are enabled. An external 10-kΩ “strapping” resistor is connected between each l/O pin and ground or VDD3. Connection to ground sets a latch to “0”, connection to V DD3 sets a latch to “1”. Figure 1 and Figure 2 show two suggested methods for strapping resistor connection. Upon W48S87-04 power-up, the first 2 ms of operation is used for input logic selection. During this period, these dual-purpose VDD Output Strapping Resistor Series Termination Resistor 10 kΩ (Load Option 1) W48S87-04 Power-on Reset Timer Hold Output Low Output Three-state Q Clock Load 22Ω Output Buffer 10 kΩ (Load Option 0) D Data Latch Figure 1. Input Logic Selection Through Resistor Load Option Jumper Options Output Strapping Resistor VDD Series Termination Resistor 10 kΩ W48S87-04 R Output Buffer Power-on Reset Timer Q Resistor Value R Output 39Ω IOAPIC, SDRAM All other clock outputs 33Ω Hold Output Low Output Three-state D Data Latch Figure 2. Input Logic Selection Through Jumper Option 4 Clock Load PRELIMINARY W48S87-04 the internal crystal oscillator. When using an external clock signal, pin X1 is used as the clock input and pin X2 is left open. The input threshold voltage of pin X1 is VDD/2. CPU/PCI Frequency Selection CPU frequency is selected with I/O pins 26, 7, and 8 (48MHz/FS0, PCI_F/FS1, and PCI0/FS2, respectively). Refer to Table 1 for CPU/PCI frequency programming information. Additional frequency selections are available through the serial data interface. Refer to Table 5 on page 10. The internal crystal oscillator is used in conjunction with a quartz crystal connected to device pins X1 and X2. This forms a parallel resonant crystal oscillator circuit. The W48S87-04 incorporates the necessary feedback resistor and crystal load capacitors. Including typical stray circuit capacitance, the total load presented to the crystal is approximately 20 pF. For optimum frequency accuracy without the addition of external capacitors, a parallel-resonant mode crystal specifying a load of 20 pF should be used. This will typically yield reference frequency accuracies within ±100 ppm. Output Buffer Configuration Clock Outputs All clock outputs are designed to drive serial terminated clock lines. The W48S87-04 outputs are CMOS-type, which provide rail-to-rail output swing. To accommodate the limited voltage swing required by some processors, the output buffers of CPU0:3 use a special VDDL2 power supply pin that can be tied to 2.5V nominal. Dual Supply Voltage Operation The W48S87-04 is designed for dual power supply operation. Supply pins VDD1, VDD2, and VDD3 are connected to a 3.3V supply and supply power to the internal core circuit and to the clock output buffers, except for outputs CPU0:3 and IOAPIC. Supply pins VDDL1 and VDDL2 may be connected to either a 2.5V or 3.3V supply. Crystal Oscillator The W48S87-04 requires one input reference clock to synthesize all output frequencies. The reference clock can be either an externally generated clock signal or the clock generated by 5 PRELIMINARY W48S87-04 The output clock is modulated with a waveform depicted in Figure 4. This waveform, as discussed in “Spread Spectrum Clock Generation for the Reduction of Radiated Emissions” by Bush, Fessler, and Hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. The deviation selected for this chip is ±0.5% of the center frequency. Figure 4 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices. Spread Spectrum Generator The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 3. As depicted in Figure 3, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is Spread Spectrum clocking is activated or deactivated by selecting the appropriate values for bits 1–0 in data byte 0 of the I2C data stream. Refer to Table 4 for more details. dB = 6.5 + 9*log10(P) + 9*log10(F) Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured. 5dB/div Typical Clock Amplitude (dB) SSFTG -SS% Frequency Span (MHz) +1.0 +SS% Figure 3. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation MIN. (–0.5%) Figure 4. Typical Modulation Profile 6 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% FREQUENCY MAX (+.0.5%) PRELIMINARY W48S87-04 of the chipset. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. Table 2 summarizes the control functions of the serial data interface. Serial Data Interface The W48S87-04 features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Upon power-up, the W48S87-04 initializes with default register settings, therefore the use of this serial data interface is optional. The serial interface is writeonly (to the clock chip) and is the dedicated function of device pins SDATA and SCLOCK. In motherboard applications, SDATA and SCLOCK are typically driven by two logic outputs Operation Data is written to the W48S87-04 in ten bytes of eight bits each. Bytes are written in the order shown in Table 3. Table 2. Serial Data Interface Control Functions Summary Control Function Description Common Application Clock Output Disable Any individual clock output(s) can be disabled. Dis- Unused outputs are disabled to reduce EMI abled outputs are actively held LOW. and system power. Examples are clock outputs to unused SDRAM DIMM socket or PCI slot. CPU Clock Frequency Selection Provides CPU/PCI frequency selections beyond the 50- and 66.8-MHz selections that are provided by the FS0:2 power-on default selection. Frequency is changed in a smooth and controlled fashion. For alternate CPU devices, and power management options. Smooth frequency transition allows CPU frequency change under normal system operation. Output Three-state Puts all clock outputs into a high-impedance state. Production PCB testing. Test Mode All clock outputs toggle in relation with X1 input, internal PLL is bypassed. Refer to Table 4. Production PCB testing. (Reserved) Reserved function for future device revision or pro- No user application. Register bit must be writduction device testing. ten as 0. Table 3. Byte Writing Sequence Byte Sequence Byte Name 1 Slave Address 11010010 Bit Sequence Commands the W48S87-04 to accept the bits in Data Bytes 0–6 for internal register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. The slave receiver address for the W48S87-04 is 11010010. Register setting will not be made if the Slave Address is not correct (or is for an alternate slave receiver). Byte Description 2 Command Code Don’t Care Unused by the W48S87-04, therefore bit values are ignored (“don’t care”). This byte must be included in the data write sequence to maintain proper byte allocation. The Command Code Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. 3 Byte Count Don’t Care Unused by the W48S87-04, therefore bit values are ignored (“don’t care”). This byte must be included in the data write sequence to maintain proper byte allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. 4 Data Byte 0 Refer to Table 4 5 Data Byte 1 6 Data Byte 2 The data bits in these bytes set internal W48S87-04 registers that control device operation. The data bits are only accepted when the Address Byte bit sequence is 11010010, as noted above. For description of bit control functions, refer to Table 4, Data Byte Serial Configuration Map. 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 10 Data Byte 6 7 PRELIMINARY Writing Data Bytes W48S87-04 7. Table 4 gives the bit formats for registers located in Data Bytes 0–6. Table 5 details additional frequency selections that are available through the serial data interface. Table 6 details the select functions for Byte 0, bits 1 and 0. Each bit in the data bytes control a particular device function except for the “reserved” bits which must be written as a logic 0. Bits are written MSB (most significant bit) first, which is bit Table 4. Data Bytes 0–6 Serial Configuration Map Affected Pin Bit(s) Pin No. Pin Name Bit Control Control Function 0 1 Default -- -- 0 Data Byte 0 7 -- -- (Reserved) 6 -- -- BYT0_SEL2 Refer to Table 5 0 5 -- -- BYT0_SEL1 Refer to Table 5 0 4 -- -- Refer to Table 5 0 3 BYT0_SEL0 BYT0 _FS# Frequency Controlled by FS (2:0) Frequency Controlled by BYT0_SEL (2:0) (Reserved) 0 2 22 1–0 -- -- 7 26 48MHZ Clock Output Disable Low Active 1 6 25 24MHZ Clock Output Disable Low Active 1 5 -- -- (Reserved) -- -- 0 (Reserved) Bit 1 0 0 1 1 Bit 0 0 1 0 1 0 Function (See Table 6 for function details) Normal Operation Test Mode Spread Spectrum On All Outputs Three-stated 00 Data Byte 1 4 -- -- -- -- 0 3 40 CPU3 Clock Output Disable Low Active 1 2 41 CPU2 Clock Output Disable Low Active 1 1 43 CPU1 Clock Output Disable Low Active 1 0 44 CPU0 Clock Output Disable Low Active 1 7 -- -- -- -- 0 6 7 PCI_F Clock Output Disable Low Active 1 5 15 PCI5 Clock Output Disable Low Active 1 4 13 PCI4 Clock Output Disable Low Active 1 3 12 PCI3 Clock Output Disable Low Active 1 2 11 PCI2 Clock Output Disable Low Active 1 1 10 PCI1 Clock Output Disable Low Active 1 0 8 PCI0 Clock Output Disable Low Active 1 Data Byte 2 (Reserved) 8 PRELIMINARY W48S87-04 Table 4. Data Bytes 0–6 Serial Configuration Map (continued) Affected Pin Bit(s) Pin No. Bit Control Pin Name Control Function 0 1 Default Data Byte 3 7 28 SDRAM7 Clock Output Disable Low Active 1 6 29 SDRAM6 Clock Output Disable Low Active 1 5 31 SDRAM5 Clock Output Disable Low Active 1 4 32 SDRAM4 Clock Output Disable Low Active 1 3 34 SDRAM3 Clock Output Disable Low Active 1 2 35 SDRAM2 Clock Output Disable Low Active 1 1 37 SDRAM1 Clock Output Disable Low Active 1 0 38 SDRAM0 Clock Output Disable Low Active 1 7 -- -- (Reserved) -- -- 0 6 -- -- (Reserved) -- -- 0 5 -- -- (Reserved) -- -- 0 (Reserved) Data Byte 4 4 -- -- -- -- 0 3 17 SDRAM11 Clock Output Disable Low Active 1 2 18 SDRAM10 Clock Output Disable Low Active 1 1 20 SDRAM9 Clock Output Disable Low Active 1 0 21 SDRAM8 Clock Output Disable Low Active 1 7 -- -- (Reserved) -- -- 0 5 -- -- (Reserved) -- -- 0 (Reserved) Data Byte 5 5 -- -- 4 47 IOAPIC -- -- 0 Low Active 1 3 -- -- (Reserved) -- -- 0 2 -- -- (Reserved) -- -- 0 1 46 REF1 Clock Output Disable Low Active 1 0 2 REF0 Clock Output Disable Low Active 1 7 -- -- (Reserved) -- -- 0 6 -- -- (Reserved) -- -- 0 5 -- -- (Reserved) -- -- 0 4 -- -- (Reserved) -- -- 0 3 -- -- (Reserved) -- -- 0 2 -- -- (Reserved) -- -- 0 1 -- -- (Reserved) -- -- 0 0 -- -- (Reserved) -- -- 0 Clock Output Disable Data Byte 6 9 PRELIMINARY W48S87-04 Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes Input Conditions Output Frequency Data Byte 0, Bit 3 = 1 Bit 6 BYT0_SEL2 Bit 5 BYT0_SEL1 Bit 4 BYT0_SEL0 CPU, SDRAM Clocks (MHz) PCI Clocks (MHz) 0 0 0 50 25 0 0 1 75.0 32 0 1 0 83.3 41.65 0 1 1 68.5 34.25 1 0 0 55.0 27.5 1 0 1 75.0 37.5 1 1 0 60.0 30.0 1 1 1 66.8 33.4 Table 6. Select Function for Data Byte 0, Bits 0:1 Input Conditions Data Byte 0 Output Conditions Bit 1 Bit 0 CPU0:3, SRAM0:11 PCI_F, PCI0:5 REF0:1, IOAPIC 48/24MHZ Normal Operation 0 0 Note 3 Note 3 14.318 MHz 48/24 MHz Test Mode 0 1 X1/2 X1/4 X1 Note 4 Spread Spectrum 1 0 Note 3 SS±0.5% Note 3 SS±0.5% 14.318 MHz 48/24 MHz Three-state 1 1 Hi-Z Hi-Z Hi-Z Hi-Z Function Note: 3. CPU, SDRAM, and PCI frequency selections are listed in Table 1 and Table 5. 4. In Test Mode, the 48/24MHz clock outputs are: - X1/2 for 48-MHz output. - X1/4 for 24-MHz output. 10 PRELIMINARY W48S87-04 Although the W48S87-04 is a receive-only device (no data write-back capability), it does transmit an “acknowledge” data pulse after each byte is received. Thus, the SDATA line can both transmit and receive data. How To Use the Serial Data Interface Electrical Requirements Figure 5 illustrates electrical characteristics for the serial interface bus used with the W48S87-04. Devices send data over the bus with an open drain logic output that can (a) pull the bus line LOW, or (b) let the bus default to logic 1. The pull-up resistors on the bus (both clock and data lines) establish a default logic 1. All bus devices generally have logic inputs to receive data. The pull-up resistor should be sized to meet the rise and fall times specified in AC parameters, taking into consideration total bus line capacitance. VDD VDD ~ 2kΩ ~ 2kΩ SERIAL BUS DATA LINE SERIAL BUS CLOCK LINE SDCLK CLOCK IN CLOCK OUT SDATA SCLOCK DATA IN N DATA OUT CLOCK IN N DATA IN DATA OUT CHIP SET (SERIAL BUS MASTER TRANSMITTER) CLOCK DEVICE (SERIAL BUS SLAVE RECEIVER) Figure 5. Serial Interface Bus Electrical Characteristics 11 SDATA N PRELIMINARY W48S87-04 Signaling Requirements Sending Data to the W48S87-04 As shown in Figure 6, valid data bits are defined as stable logic 0 or 1 condition on the data line during a clock HIGH (logic 1) pulse. A transitioning data line during a clock HIGH pulse may be interpreted as a start or stop pulse (it will be interpreted as a start or stop pulse if the start/stop timing parameters are met). The device accepts data once it has detected a valid start bit and address byte sequence. Device functionality is changed upon the receipt of each data bit (registers are not double buffered). Partial transmission is allowed meaning that a transmission can be truncated as soon as the desired data bits are transmitted (remaining registers will be unmodified). Transmission is truncated with either a stop bit or new start bit (restart condition). A write sequence is initiated by a “start bit” as shown in Figure 7. A “stop bit” signifies that a transmission has ended. As stated previously, the W48S87-04 sends an “acknowledge” pulse after receiving eight data bits in each byte as shown in Figure 8. SDATA SCLOCK Valid Data Bit Change of Data Allowed Figure 6. Serial Data Bus Valid Data Bit SDATA SCLOCK Start Bit Stop Bit Figure 7. Serial Data Bus Start and Stop Bit 12 Stop Condition Slave Address (First Byte) SDATA SCLOCK Command Code (Second Byte) MSB 1 1 0 1 0 0 LSB 1 0 1 2 3 4 5 6 7 8 Byte Count (Third Byte) MSB A 1 LSB 2 3 4 5 6 7 8 Last Data Byte (Last Byte) MSB A 1 MSB 2 3 4 1 LSB 2 3 4 5 6 SDATA Acknowledgment Bit from Clock Device Signaling by Clock Device 7 8 A PRELIMINARY Figure 8. Serial Data Bus Write Sequence Signaling from System Core Logic Start Condition 13 tSPF tLOW SCLOCK tSTHD tDSU tHIGH tR tF tDHD tSP tSPSU tSTHD t SPSU W48S87-04 Figure 9. Serial Data Bus Timing Diagram SDATA PRELIMINARY W48S87-04 Absolute Maximum Ratings above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions . Parameter Description Rating Unit V VDD, VIN Voltage on any pin with respect to GND –0.5 to +7.0 –65 to +150 °C 0 to +70 °C –55 to +125 °C 2 (min.) kV TSTG Storage Temperature TA Operating Temperature TB Ambient Temperature under Bias ESDPROT Input ESD Protection Crystal Oscillator Parameter Description Test Condition Min. [5] VTH X1 Input Threshold Voltage CLOAD Load Capacitance, Imposed on External Crystal[6] CIN,X1 X1 Input Capacitance[7] Pin X2 unconnected Typ. Max. Unit 1.65 V 20 pF 40 pF 3.3V DC Electrical Characteristics (CPU3.3#_2.5 Input = 0) TA = 0°C to +70°C, VDD1:3 = VDDL1:2 = 3.3V±5% (3.135–3.465V) Parameter Description Test Condition Min. Typ. Max. Unit 160 mA 0.8 V Supply Current IDD Combined 3.3V Supply Current CPU0:3 =66.8 MHz Outputs Loaded[8] Logic Inputs (All referenced to VDDQ3 = 3.3V) VIL Input Low Voltage VIH Input High Voltage IIL IIH 2.0 V [9] 10 µA [9] 10 µA 50 mV Input Low Current Input High Current Clock Outputs VOL Output Low Voltage VOH Output High Voltage IOL Output Low Current IOL = 1 mA [10] CPU0:3 IOH = –1 mA 3.1 VOL = 1.5V V 55 75 105 SDRAM0:11 80 110 155 PCI_F, PCI0:5 55 75 105 IOAPIC 100 135 190 REF0 60 75 90 REF1 45 60 75 48/24MHZ 55 75 105 mA Notes: 5. X1 input threshold voltage (typical) is VDD/2. 6. The W48S87-04 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 20 pF; this includes typical stray capacitance of short PCB traces to crystal. 7. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected). 8. All clock outputs loaded with maximum lump capacitance test load specified in AC Electrical Characteristics section. 9. W48S87-04 logic inputs have internal pull-up devices. 10. CPU0:3 loaded by 60Ω, 6-inch long transmission lines ending with 20-pF capacitors. 14 PRELIMINARY W48S87-04 3.3V DC Electrical Characteristics (CPU3.3#_2.5 Input = 0) (continued) TA = 0°C to +70°C, VDD1:3 = VDDL1:2 = 3.3V±5% (3.135–3.465V) Parameter IOH Description Output High Current Test Condition [10] CPU0:3 VOH = 1.5V Min. Typ. Max. Unit mA 55 85 125 SDRAM0:11 80 120 175 PCI_F, PCI0:5 55 85 125 IOAPIC 100 150 220 REF0 60 85 110 REF1 45 65 90 48/24MHZ 55 85 125 Pin Capacitance/Inductance CIN Input Pin Capacitance 5 pF COUT Output Pin Capacitance 6 pF LIN Input Pin Inductance 7 nH 0.3VDD V Except X1 and X2 Serial Input Port VIL Input Low Voltage VDD = 3.3V VIH Input High Voltage VDD = 3.3V IIL Input Low Current No internal pull-up/down on SCLOCK 10 µA IIH Input High Current No internal pull-up/down on SCLOCK 10 µA IOL Sink Current into SDATA, Open Drain N-Channel Device On IOL = 0.3VDD CIN Input Capacitance of SDATA and SCLOCK 10 pF CSDATA Total Capacitance of SDATA Bus 400 pF CSCLOCK Total Capacitance of SCLOCK Bus 400 pF Max. Unit 0.7VDD V 6 mA 2.5V DC Electrical Characteristics (CPU3.3#_2.5 Input = 1) TA = 0°C to +70°C, VDD1:3 = 3.3V±5% (3.135–3.456V), VDDL1:2 = 2.5V±5% (2.375–2.625V) Parameter Description Test Condition Min. Typ. Supply Current IDD-3.3V 3.3V Supply Current CPU0:3 = 66.4 MHz Outputs Loaded[8] 300 mA IDD-2.5 2.5V Supply Current CPU0:3= 66.4 MHz Outputs Loaded[8] 50 mA Logic Inputs VIL Input Low Voltage VIH Input High Voltage IIL Input Low Current[9] IIH 0.8 2.0 [9] Input High Current 15 V V 10 µA 10 µA PRELIMINARY W48S87-04 2.5V DC Electrical Characteristics (CPU3.3#_2.5 Input = 1) (continued) TA = 0°C to +70°C, VDD1:3 = 3.3V±5% (3.135–3.456V), VDDL1:2 = 2.5V±5% (2.375–2.625V) Parameter Description Test Condition Min. Typ. Max. Unit 50 mV Clock Outputs VOL Output Low Voltage VOH Output High Voltage IOL = 1 mA IOH = –1 mA 2.2 [10] V VOL = 1.25V 45 70 105 IOL Output Low Current CPU0:3 IOAPIC VOL = 1.25V 55 85 130 IOH Output High Current CPU0:3[10] VOH = 1.25V 40 65 95 IOAPIC VOH = 1.25V 50 80 120 mA mA Pin Capacitance/Inductance CIN Input Pin Capacitance 5 pF COUT Output Pin Capacitance 6 pF LIN Input Pin Inductance 7 nH 0.3VDD V Except X1 and X2 Serial Input Port VIL Input Low Voltage VDD = 2.5V VIH Input High Voltage VDD = 2.5V 0.7VDD V 3.3V AC Electrical Characteristics (CPU3.3#_2.5 Input = 0) TA = 0°C to +70°C, VDD1:3 = VDD1:3 = 3.3V±5% (3.135–3.465V), fXTL = 14.31818 MHz Spread Spectrum function turned off AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output. CPU Clock Outputs, CPU0:3 (Lump Capacitance Test Load = 20 pF) CPU = 66.8 MHz Parameter Description Test Condition/Comments Min. CPU = 60 MHz Typ. Max. Min. tP Period Measured on rising edge at 1.5V f Frequency, Actual Determined by PLL divider ratio tH High Time Duration of clock cycle above 2.4V 5.2 6 ns tL Low Time Duration of clock cycle below 0.4V 5 5.8 ns tR Output Rise Edge Rate Measured from 0.4V to 2.4V tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. tSK Output Skew Measured on rising edge at 1.5V fST Frequency Stabilization Assumes full supply voltage reached within 1 ms from power-up. Short cyfrom Power-up (cold cles exist prior to frequency stabilizastart) tion. Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 16 15 Typ. Max. Unit 16.7 66.8 1 15 59.876 4 20 ns 4 V/ns 1 4 V/ns 45 55 % 250 250 ps 250 250 ps 3 3 ms 30 Ω 30 1 MHz 15 20 PRELIMINARY W48S87-04 3.3V AC Electrical Characteristics (CPU3.3#_2.5 Input = 0) (continued) SDRAM Clock Outputs, SDRAM0:11 (Lump Capacitance Test Load = 30 pF) CPU = 66.8 MHz Parameter Description Test Condition/Comments Min. CPU = 60 MHz Typ. Max. Min. Typ. Max. Unit tP Period Measured on rising edge at 1.5V f Frequency, Actual Determined by PLL divider ratio tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 1 4 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. 250 ps tSK Output Skew Measured on rising edge at 1.5V tSK CPU to SDRAM Clock Skew Covers all CPU/SDRAM outputs. Measured on rising edge at 1.5V. 500 500 ps fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 20 Ω 15 16.7 66.8 ns 59.876 250 100 10 15 MHz 100 20 10 15 ps PCI Clock Outputs, PCI_F and PCI0:5 (Lump Capacitance Test Load = 30 pF) CPU = 66.8 MHz Parameter Description Test Condition/Comments Min. CPU = 60 MHz Typ. Max. Min. Period Measured on rising edge at 1.5V f Frequency, Actual Determined by PLL divider ratio tH High Time Duration of clock cycle above 2.4V 12 tL Low Time Duration of clock cycle below 0.4V 12 tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 1 4 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. 250 250 ps tSK Output Skew Measured on rising edge at 1.5V 250 250 ps tO CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output. 4 ns fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 30 Ω 17 30 Typ. Max. Unit tP 33.3 33.4 ns 29.938 13.3 ns 13.3 1 4 ns 1 3 15 MHz 20 30 15 20 PRELIMINARY W48S87-04 3.3V AC Electrical Characteristics (CPU3.3#_2.5 Input = 0) (continued) IOAPIC Clock Output (Lump Capacitance Test Load = 20 pF) CPU = 60/66.8 MHz Parameter Description f Frequency, Actual Test Condition/Comments Min. Frequency generated by crystal oscillator Typ. Max. 14.31818 Unit MHz tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 1.5 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 15 Ω 8 12 REF0 Clock Output (Lump Capacitance Test Load = 45 pF) CPU = 60/66.8 MHz Parameter Description Test Condition/Comments Min. Typ. Max. Frequency, Actual Frequency generated by crystal oscillator tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 40 fST Frequency Stabilization Assumes full supply voltage reached within from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to frequency stabilization. Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 14.31818 Unit f 17 20 MHz 60 % 1.5 ms 25 Ω REF1 Clock Output (Lump Capacitance Test Load = 20 pF) CPU = 60/66.8 MHz Parameter Description f Frequency, Actual Test Condition/Comments Min. Frequency generated by crystal oscillator Typ. Max. 14.31818 Unit MHz tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 40 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 1.5 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 35 Ω 18 20 25 PRELIMINARY W48S87-04 3.3V AC Electrical Characteristics (CPU3.3#_2.5 Input = 0) (continued) 48-/24-MHZ Clock Outputs (Lump Capacitance Test Load = 20 pF) CPU = 60/66.8 MHz Parameter Description Test Condition/Comments f Frequency, Actual Determined by PLL divider ratio (see n/m below) Min. Typ. Max. Unit 48.008/24.004 MHz ppm fD Deviation from 48 MHz (48.008 – 48)/48 +167 m/n PLL Ratio (14.31818 MHz x 57/17 = 48.008 MHz) 57/17 tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 40 tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. fST Frequency Stabilization Assumes full supply voltage reached within from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to frequency stabilization. Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 55 % 500 ps 3 ms 15 20 30 Ω Min. Typ. Max. Unit 100 kHz Serial Input Port Parameter Description Test Condition fSCLOCK SCLOCK Frequency Normal Mode 0 tSTHD Start Hold Time 4.0 µs tLOW SCLOCK Low Time 4.7 µs tHIGH SCLOCK High Time 4.0 µs tDSU Data Setup Time 250 ns tDHD Data Hold Time (Transmitter should provide a 300-ns hold time to ensure proper timing at the receiver.) 0 ns tR Rise Time, SDATA and SCLOCK From 0.3VDD to 0.7VDD 1000 ns tF Fall Time, SDATA and SCLOCK From 0.7VDD to 0.3VDD 300 ns tSTSU Stop Setup Time 4.0 µs tSPF Bus Free Time between Stop and Start Condition 4.7 µs tSP Allowable Noise Spike Pulse Width 50 19 ns PRELIMINARY W48S87-04 2.5V AC Electrical Characteristics (CPU3.3#_2.5 Input = 1) TA = 0°C to +70°C, VDD1:3 = 3.3V±5% (3.135–3.465V), VDDL1:2 = 2.5V±5% (2.375–2.625V), fXTL = 14.31818 MHz Spread Spectrum function turned off AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output. CPU Clock Outputs, CPU0:3 (Lump Capacitance Test Load = 20 pF) CPU = 66.8 MHz Parameter Description Test Condition/Comments CPU = 60 MHz Min. Typ. Max. Min. Typ. Max. Unit tP Period Measured on rising edge at 1.25V f Frequency, Actual Determined by PLL divider ratio tH High Time Duration of clock cycle above 2.0V tL Low Time Duration of clock cycle below 0.4V tR Output Rise Edge Rate Measured from 0.4V to 2.0V 0.8 3 0.8 3 V/ns tF Output Fall Edge Rate Measured from 2.0V to 0.4V 0.8 3 0.8 3 V/ns tD Duty Cycle Measured on rising and falling edge at 1.25V 45 55 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. 250 250 ps tSK Output Skew Measured on rising edge at 1.25V 250 250 ps fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 30 Ω 15 16.7 66.8 59.876 5.2 MHz 6 5 12 ns ns 5.8 20 30 12 ns 20 IOAPIC Clock Output (Lump Capacitance Test Load = 20 pF) CPU = 60/66.8 MHz Parameter Description Test Condition/Comments Min. Typ. Max. Frequency, Actual Frequency generated by crystal oscillator tR Output Rise Edge Rate Measured from 0.4V to 2.0V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.0V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.25V 45 fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. Ordering Information Ordering Code W48S87 Freq. Mask Code Package Name 04 H Package Type 48-pin SSOP (300 mils) Document #: 38-00859 20 14.31818 Unit f 10 15 MHz 55 % 1.5 ms 25 Ω PRELIMINARY W48S87-04 Package Diagram 48-Pin Small Shrink Outline Package (SSOP, 300 mils) Summary of nominal dimensions in inches: Body Width: 0.296 Lead Pitch: 0.025 Body Length: 0.625 Body Height: 0.102 © Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.