WM8776 w 24-bit, 192kHz Stereo Codec with 5 Channel I/P Multiplexer DESCRIPTION FEATURES The WM8776 is a high performance, stereo audio codec with five channel input selector. The WM8776 is ideal for surround sound processing applications for home hi-fi, DVD-RW and other audio visual equipment. • Audio Performance • − 108dB SNR (‘A’ weighted @ 48kHz) DAC − 102dB SNR (‘A’ weighted @ 48kHz) ADC DAC Sampling Frequency: 32kHz – 192kHz A stereo 24-bit multi-bit sigma delta ADC is used with a five stereo channel input mixer. Each ADC channel has programmable gain control with automatic level control. Digital audio output word lengths from 16-32 bits and sampling rates from 32kHz to 96kHz are supported. • • • • A stereo 24-bit multi-bit sigma delta DAC is used with digital audio input word lengths from 16-32 bits and sampling rates from 32kHz to 192kHz. The DAC has an input mixer allowing an external analogue signal to be mixed with the DAC signal. There are also Headphone and line outputs, with volume controls for the headphones. • • The WM8776 supports fully independent sample rates for the ADC and DAC. The audio data interface supports I2S, left justified, right justified and DSP formats. • • Stereo Headphone and Line Output 3-Wire SPI Compatible or 2-Wire Software Serial Control Interface Master or Slave Clocking Mode Programmable Audio Data Interface Modes • − I2S, Left, Right Justified or DSP − 16/20/24/32 bit Word Lengths Analogue Bypass Path Feature • • The device is controlled in software via a 2 or 3 wire serial interface, selected by the MODE pin, which provides access to all features including channel selection, volume controls, mutes, and de-emphasis facilities. The device is available in a 48-pin TQFP package. VMIDDAC DACREFN DACREFP ADCBCLK DOUT ADCLRC DACMCLK DACBCLK DACLRC DIN ADCMCLK ADCREFGND ADCREFP AVDD Surround Sound AV Processors and Hi-Fi systems DVD-RW ZFLAGL ZFLAGR • • VMIDADC Selectable AUX input to the volume controls 2.7V to 5.5V Analogue, 2.7V to 3.6V Digital supply Operation APPLICATIONS BLOCK DIAGRAM AGND ADC Sampling Frequency: 32kHz – 96kHz Five stereo ADC inputs with analogue gain adjust from +24dB to –21dB in 0.5dB steps Programmable Limiter or Automatic Level Control (ALC) Stereo DAC with independent analogue and digital volume controls AINOPL AINVGL VOUTL VOUTR INPUT MIXER AIN1L AIN1R AIN2L AIN2R AIN3L AIN3R AIN4L AIN4R AIN5L AIN5R HPVDD AUDIO INTERFACE STEREO ADC STEREO DAC AND ALC LOW PASS FILTERS DIGITAL FILTERS z VMID HPOUTL HPOUTR HPGND AINVGR AINOPR W WM8776 WOLFSON MICROELECTRONICS plc w :: www.wolfsonmicro.com AUXL AUXR DI CE CL MODE DVDD DGND CONTROL INTERFACE Product Preview, June 2004, Rev 1.91 Copyright 2004 Wolfson Microelectronics plc WM8776 Product Preview TABLE OF CONTENTS DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................3 ORDERING INFORMATION ..................................................................................3 PIN DESCRIPTION ................................................................................................4 ABSOLUTE MAXIMUM RATINGS.........................................................................5 ELECTRICAL CHARACTERISTICS ......................................................................6 TERMINOLOGY ............................................................................................................ 7 MASTER CLOCK TIMING......................................................................................8 DIGITAL AUDIO INTERFACE – MASTER MODE ......................................................... 9 DIGITAL AUDIO INTERFACE – SLAVE MODE .......................................................... 10 3-WIRE MPU INTERFACE TIMING ............................................................................ 11 CONTROL INTERFACE TIMING – 2-WIRE MODE .................................................... 12 DEVICE DESCRIPTION.......................................................................................13 INTRODUCTION ......................................................................................................... 13 AUDIO DATA SAMPLING RATES............................................................................... 14 ZERO DETECT ........................................................................................................... 15 POWERDOWN MODES ............................................................................................. 15 POWER-ON-RESET ................................................................................................... 16 DIGITAL AUDIO INTERFACE ..................................................................................... 17 CONTROL INTERFACE OPERATION ........................................................................ 21 CONTROL INTERFACE REGISTERS ........................................................................ 23 LIMITER / AUTOMATIC LEVEL CONTROL (ALC) ...................................................... 32 REGISTER MAP ......................................................................................................... 39 DIGITAL FILTER CHARACTERISTICS ...............................................................47 DAC FILTER RESPONSES......................................................................................... 47 ADC FILTER RESPONSES......................................................................................... 48 ADC HIGH PASS FILTER ........................................................................................... 49 DIGITAL DE-EMPHASIS CHARACTERISTICS........................................................... 50 APPLICATIONS INFORMATION .........................................................................51 EXTERNAL CIRCUIT CONFIGURATION ................................................................... 51 RECOMMENDED EXTERNAL COMPONENTS ..................................................52 PACKAGE DIMENSIONS ....................................................................................54 ADDRESS: .................................................................................................................. 55 w PP Rev 1.91 June 2004 2 WM8776 Product Preview PIN CONFIGURATION ORDERING INFORMATION DEVICE TEMPERATURE RANGE WM8776EFT/V -25 to +85 C o o PACKAGE MOISTURE SENSITIVITY LEVEL PEAK SOLDERING TEMPERATURE 48-pin TQFP MSL2 240°C WM8776EFT/RV -25 to +85 C 48-pin TQFP (tape and reel) MSL2 WM8776SEFT/V -25 to +85oC 48-pin TQFP (lead free) MSL2 WM8776SEFT/RV -25 to +85oC 48-pin TQFP (lead free, tape and reel) MSL2 240°C 260°C 260°C Note: Reel quantity = 2,200 w PP Rev 1.91 June 2004 3 WM8776 Product Preview PIN DESCRIPTION PIN NAME TYPE 1 AIN2L Analogue Input Channel 2 left input multiplexor virtual ground DESCRIPTION 2 AIN1R Analogue Input Channel 1 right input multiplexor virtual ground 3 AIN1L Analogue Input Channel 1 left input multiplexor virtual ground 4 DACBCLK Digital input/output 5 DACMCLK Digital input Master DAC clock; 256, 384, 512 or 768fs (fs = word clock frequency) 6 DIN Digital Input DAC data input 7 DACLRC Digital input/output DAC left/right word clock 8 ZFLAGR Open Drain output DAC Right Zero Flag output (external pull-up resistor required) 9 ZFLAGL Open Drain output DAC Left Zero Flag output (external pull-up resistor required) 10 ADCBCLK Digital input/output ADC audio interface bit clock 11 ADCMCLK Digital input 12 DOUT Digital output 13 ADCLRC Digital input/output 14 DGND Supply Digital negative supply 15 DVDD Supply Digital positive supply 16 MODE Digital input Control interface mode select (5V tolerant) 17 CE Digital input Serial interface Latch signal (5V tolerant) 18 DI Digital input Serial interface data (5V tolerant) 19 CL Digital input Serial interface clock (5V tolerant) 20 HPOUTL Analogue Output 21 HPGND Supply Headphone negative supply 22 HPVDD Supply Headphone positive supply 23 HPOUTR Analogue Output 24 NC Not bonded DAC audio interface bit clock ADC audio interface master clock ADC data output ADC left/right word clock Headphone left channel output Headphone right channel output 25 NC Not bonded 26 VOUTL Analogue output DAC channel left output 27 VOUTR Analogue output DAC channel right output 28 VMIDDAC Analogue output DAC midrail decoupling pin ; 10uF external decoupling 29 DACREFN Analogue input DAC negative reference input 30 DACREFP Analogue input DAC positive reference input 31 AUXR Analogue input DAC mixer right channel input 32 AUXL Analogue input DAC mixer left channel input 33 VMIDADC Analogue Output 34 ADCREFGND Supply 35 ADCREFP Analogue Output 36 AVDD Supply Analogue positive supply 37 AGND Supply Analogue negative supply and subVstrate connection 38 AINVGR Analogue Input 39 AINOPR Analogue Output 40 AINVGL Analogue Input 41 AINOPL Analogue Output 42 AIN5R Analogue Input Channel 5 right input multiplexor virtual ground 43 AIN5L Analogue Input Channel 5 left input multiplexor virtual ground 44 AIN4R Analogue Input Channel 4 right input multiplexor virtual ground 45 AIN4L Analogue Input Channel 4 left input multiplexor virtual ground 46 AIN3R Analogue Input Channel 3 right input multiplexor virtual ground 47 AIN3L Analogue Input Channel 3 left input multiplexor virtual ground 48 AIN2R Analogue Input Channel 2 right input multiplexor virtual ground ADC midrail divider decoupling pin; 10uF external decoupling ADC negative supply and substrate connection ADC positive reference decoupling pin; 10uF external decoupling Right channel multiplexor virtual ground Right channel multiplexor output Left channel multiplexor virtual ground Left channel multiplexor output Note : Digital input pins have Schmitt trigger input buffers and pins 16, 17, 18 and 19 are 5V tolerant. w PP Rev 1.91 June 2004 4 WM8776 Product Preview ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag. MIN MAX Digital supply voltage -0.3V +3.63V Analogue supply voltage -0.3V +7V CONDITION Voltage range digital inputs (DI, CL, CE and MODE) DGND -0.3V +7V Voltage range digital inputs (MCLK, DIN, ADCLRC, DACLRC, ADCBCLK and DACBCLK) DGND -0.3V DVDD + 0.3V Voltage range analogue inputs AGND -0.3V AVDD +0.3V Master Clock Frequency 37MHz Operating temperature range, TA -25°C +85°C Storage temperature -65°C +150°C Notes: 1. Analogue and digital grounds must always be within 0.3V of each other. RECOMMENDED OPERATING CONDITIONS PARAMETER Digital supply range SYMBOL TEST CONDITIONS MIN TYP MAX UNIT DVDD 2.7 3.6 V Analogue supply range AVDD, HPVDD, DACREFP 2.7 5.5 V Ground AGND, DGND, DACREFN, ADCREFGND Difference DGND to AGND 0 -0.3 0 V +0.3 V Note: digital supply DVDD must never be more than 0.3V greater than AVDD. w PP Rev 1.91 June 2004 5 WM8776 Product Preview ELECTRICAL CHARACTERISTICS Test Conditions AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT 0.8 V 0.1 x DVDD V Digital Logic Levels (TTL Levels) Input LOW level VIL Input HIGH level VIH Output LOW VOL IOL=1mA Output HIGH VOH IOH=1mA 2.0 V 0.9 x DVDD V Analogue Reference Levels Reference voltage VVMID AVDD/2 V Potential divider resistance RVMID 50k Ω DAC Performance (Load = 10k Ω, 50pF) 0dBFs Full scale output voltage 1.0 x AVDD/5 Vrms SNR (Note 1,2) A-weighted, @ fs = 48kHz 108 dB SNR (Note 1,2) A-weighted @ fs = 96kHz 108 dB A-weighted, -60dB full scale input 108 dB Dynamic Range (Note 2) DNR Total Harmonic Distortion (THD) 1kHz, 0dBFs -97 DAC channel separation -90 100 Power Supply Rejection Ratio PSRR dB dB 1kHz 100mVpp 50 dB 20Hz to 20kHz 100mVpp 45 dB Headphone Buffer Maximum Output voltage Max Output Power (Note 4) Po SNR (Note 1,2) 0.9 Vrms RL = 32 Ω 25 mW RL = 16 Ω 50 mW A-weighted Headphone analogue Volume Gain Step Size 85 92 0.5 1 dB 1.5 dB +6 dB Headphone analogue Volume Gain Range 1kHz Input Headphone analogue Volume Mute Attenuation 1kHz Input, 0dB gain 100 1kHz, RL = 32Ω @ Po = 10mW rms -80 0.01 -60 0.1 dB % 1kHz, RL = 32Ω @ Po = 20mW rms -77 0.014 -40 1.0 dB % 20Hz to 20kHz, without supply decoupling -40 Total Harmonic Distortion +Noise Power Supply Rejection Ratio THD+N PSRR -73 dB dB ADC Performance Input Signal Level (0dB) 1.0 x AVDD/5 Vrms SNR (Note 1,2) A-weighted, 0dB gain @ fs = 48kHz 102 dB SNR (Note 1,2) A-weighted, 0dB gain @ fs = 96kHz 64 x OSR 100 dB Dynamic Range (note 2) Total Harmonic Distortion (THD) w A-weighted, -60dB full scale input 102 1kHz, 0dBFs -90 dB -80 DB PP Rev 1.91 June 2004 6 WM8776 Product Preview Test Conditions AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated. ADC Channel Separation 1kHz, -3dBFs -95 1kHz Input 90 Programmable Gain Step Size 0.25 0.5 -85 dB dB 0.75 dB Programmable Gain Range (Analogue) 1kHz Input -21 +24 dB Programmable Gain Range (Digital) 1kHz Input -103 -21.5 dB Mute Attenuation (Note 6) Power Supply Rejection Ratio PSRR 1kHz Input, 0dB gain 76 dB 1kHz 100mVpp 50 dB 20Hz to 20kHz 100mVpp 45 dB Analogue input (AIN) to Analogue output (VOUT) (Load=10k Ω, 50pF, gain = 0dB) Bypass Mode 0dB Full scale output voltage SNR (Note 1) 90 THD Power Supply Rejection Ratio Mute Attenuation PSRR 1.0 x AVDD/5 Vrms 100 dB 1kHz, 0dB -90 dB 1kHz, -3dB -95 dB 1kHz 100mVpp 50 dB 20Hz to 20kHz 100mVpp 45 dB 1kHz, 0dB 100 dB AVDD = 5V 48 mA DVDD = 3.3V 8 mA Supply Current Analogue supply current Digital supply current Notes: 1. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’ weighted. 2. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. 3. VMID decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance). 4. Harmonic distortion on the headphone output decreases with output power. 5. All performance measurement done using certain timings conditions (Please refer to section ‘Digital Audio Interface’). 6. A better MUTE Attenuation can be achieved if the ADC gain is set to minimum. TERMINOLOGY 1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). 2. Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB). 3. THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal. 4. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band). 5. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other. 6. Pass-Band Ripple - Any variation of the frequency response in the pass-band region. w PP Rev 1.91 June 2004 7 WM8776 Product Preview MASTER CLOCK TIMING tMCLKL MCLK tMCLKH tMCLKY Figure 1 Master Clock Timing Requirements Test Conditions o AVDD = 5V, DVDD = 3.3V, AGND = 0V, AGND, DGND = 0V, TA = +25 C, fs = 48kHz, ADC/DACMCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT System Clock Timing Information ADC/DACMCLK System clock pulse width high tMCLKH 11 ns ADC/DACMCLK System clock pulse width low tMCLKL 11 ns ADC/DACMCLK System clock cycle time tMCLKY 28 ns ADC/DACMCLK Duty cycle 40:60 60:40 Table 1 Master Clock Timing Requirements w PP Rev 1.91 June 2004 8 WM8776 Product Preview DIGITAL AUDIO INTERFACE – MASTER MODE DACBCLK ADCBCLK ADCLRC WM8776 CODEC DACLRC DVD Controller DOUT DIN Figure 2 Audio Interface - Master Mode ADCBCLK/ DACBCLK (Output) tDL ADCLRC/ DACLRC (Outputs) tDDA DOUT DIN tDST tDHT Figure 3 Digital Audio Data Timing – Master Mode Test Conditions AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, ADC/DACMCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information ADC/DACLRC propagation delay from ADC/DACBCLK falling edge tDL 0 10 ns DOUT propagation delay from ADCBCLK falling edge tDDA 0 10 ns DIN setup time to DACBCLK rising edge tDST 10 ns DIN hold time from DACBCLK rising edge tDHT 10 ns Table 2 Digital Audio Data Timing – Master Mode w PP Rev 1.91 June 2004 9 WM8776 Product Preview DIGITAL AUDIO INTERFACE – SLAVE MODE DACBCLK ADCBCLK WM8776 ADCLRC CODEC DACLRC DVD Controller DOUT DIN Figure 4 Audio Interface – Slave Mode tBCH ADCBCLK/ DACBCLK tBCL tBCY DACLRC/ ADCLRC tDS tLRH tLRSU DIN tDD tDH DOUT Figure 5 Digital Audio Data Timing – Slave Mode Test Conditions AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, ADC/DACMCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information ADC/DACBCLK cycle time tBCY 50 ns ADC/DACBCLK pulse width high tBCH 20 ns ADC/DACBCLK pulse width low tBCL 20 ns DACLRC/ADCLRC set-up time to ADC/DACBCLK rising edge tLRSU 10 ns DACLRC/ADCLRC hold time from ADC/DACBCLK rising edge tLRH 10 ns DIN set-up time to DACBCLK rising edge tDS 10 ns DIN hold time from DACBCLK rising edge tDH 10 ns DOUT propagation delay from ADCBCLK falling edge tDD 0 10 ns Table 3 Digital Audio Data Timing – Slave Mode Note: ADCLRC and DACLRC should be synchronous with MCLK, although the WM8776 interface is tolerant of phase variations or jitter on these signals. w PP Rev 1.91 June 2004 10 WM8776 Product Preview 3-WIRE MPU INTERFACE TIMING tCSL tCSH CE tSCY tSCH tCSS tSCS tSCL CL DI LSB tDSU tDHO Figure 6 SPI compatible (3-wire) Control Interface Input Timing (MODE=1) Test Conditions AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated SYMBOL MIN CL rising edge to CE rising edge PARAMETER tSCS 60 TYP MAX UNIT ns CL pulse cycle time tSCY 80 ns CL pulse width low tSCL 30 ns CL pulse width high tSCH 30 ns DI to CL set-up time tDSU 20 ns CL to DI hold time tDHO 20 ns CE pulse width low tCSL 20 ns CE pulse width high tCSH 20 ns CE rising to CL rising tCSS 20 ns Table 4 3-wire SPI compatible Control Interface Input Timing Information w PP Rev 1.91 June 2004 11 WM8776 Product Preview CONTROL INTERFACE TIMING – 2-WIRE MODE t3 t3 t5 DI t6 t4 t2 t8 CL t1 t9 t7 Figure 7 Control Interface Timing – 2-Wire Serial Control Mode (MODE=0) Test Conditions AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated PARAMETER SYMBOL MIN TYP MAX UNIT CL Low Pulse-Width t1 600 400 kHz ns CL High Pulse-Width t2 1.3 us Hold Time (Start Condition) t3 600 ns Setup Time (Start Condition) t4 600 ns Data Setup Time t5 100 DI, CL Rise Time t6 DI, CL Fall Time t7 Setup Time (Stop Condition) t8 Data Hold Time t9 Pulse width of spikes that will be suppressed tps Program Register Input Information CL Frequency 0 ns 300 ns 300 ns 900 ns 5 ns 600 0 ns Table 5 2-wire Control Interface Timing Information. w PP Rev 1.91 June 2004 12 WM8776 Product Preview DEVICE DESCRIPTION INTRODUCTION WM8776 is a complete 2-channel DAC, 2-channel ADC audio codec, with flexible input multiplexor including digital interpolation and decimation filters, multi-bit sigma delta stereo ADC, and switched capacitor multi-bit sigma delta DACs with analogue volume controls on each channel and output smoothing filters. It is available in a single package and controlled by either a 3-wire or 2-wire software interface. The 3-wire interface is compatible with the SPI standard. An analogue bypass path option is available, to allow stereo analogue signals from any of the 5 stereo inputs to be sent to the stereo outputs via the main volume controls. This allows a purely analogue input to analogue output high quality signal path to be implemented if required. The DAC and ADC have separate left/right clocks, bit clocks, master clocks and data I/Os. The Audio Interface may be configured to operate in either master or slave mode. In Slave mode ADCLRC, DACLRC, ADCBCLK and DACBCLK are all inputs. In Master mode ADCLRC, DACLRC, ADCBCLK and DACBCLK are outputs. The input multiplexor to the ADC is configured to allow large signal levels to be input to the ADC, using external resistors to reduce the amplitude of larger signals to within the normal operating range of the ADC. The ADC has an analogue input PGA and a digital gain control, accessed by one register write. The input PGA allows input signals to be gained up to +24dB and attenuated down to -21dB in 0.5dB steps. The digital gain control allows attenuation from -21.5dB to -103dB in 0.5dB steps. This allows the user maximum flexibility in the use of the ADC. The DAC has its own digital volume control, which is adjustable between 0dB and -127.5dB in 0.5dB steps. There is also an analogue volume control on the headphone outputs, which is adjustable between +6dB and -73dB in 1dB steps. The analogue and digital volume controls may be operated independently. In addition a zero cross detect circuit is provided for both analogue and digital volume controls. When analogue volume zero-cross detection is enabled the attenuation values are only updated when the input signal to the gain stage is close to the analogue ground level. The digital volume control detects a transition through the zero point before updating the volume. This minimises audible clicks and ‘zipper’ noise as the gain values change. The DAC output incorporates an input selector and mixer allowing a signal to be either switched into the signal path in place of the DAC signal or mixed with the DAC signal before the volume control. Use of external resistors allows larger input levels to be accepted by the device, giving maximum user flexibility. Internal functionality is controlled by CE, CL, DI and MODE input pins. These are 5V tolerant with TTL input thresholds, allowing the WM8776 to used with DVDD = 3.3V and be controlled by a controller with 5V output. The MODE pin determines which of the two control interface modes is selected. Operation using system clock of 128fs, 192fs, 256fs, 384fs, 512fs or 768fs is provided. In Slave mode selection between clock rates is automatically controlled. In master mode the master clock to sample rate ratio is set by control bits ADCRATE and DACRATE. ADC and DAC may run at different rates and have their own bit clocks and master clocks. The audio data interface supports right, left and I2S interface formats along with a highly flexible DSP serial port interface. w PP Rev 1.91 June 2004 13 WM8776 Product Preview AUDIO DATA SAMPLING RATES In a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio system’s Master Clock. The WM8776 uses separate master clocks for the ADC and DAC. The external master system clocks can be applied directly through the ADCMCLK and DACMCLK input pins with no software configuration necessary. In a system where there are a number of possible sources for the reference clock it is recommended that the clock source with the lowest jitter be used to optimise the performance of the ADC and DAC. The master clock for WM8776 supports DAC and ADC audio sampling rates from 256fs to 768fs, where fs is the audio sampling frequency (DACLRC or ADCLRC) typically 32kHz, 44.1kHz, 48kHz or 96kHz (the DAC also supports operation at 128fs and 192fs and 192kHz sample rate). The master clock is used to operate the digital filters and the noise shaping circuits. In Slave mode the WM8776 has a master detection circuit that automatically determines the relationship between the master clock frequency and the sampling rate (to within +/- 32 system clocks). If there is a greater than 32 clocks error the interface is disabled and maintains the output level at the last sample. The master clock should be synchronised with ADCLRC/DACLRC for optical performance, although the WM8776 is tolerant of phase variations or jitter on this clock. Table 6 shows the typical master clock frequency inputs for the WM8776. The signal processing for the WM8776 typically operates at an oversampling rate of 128fs for both ADC and DAC. The exception to this for the DAC is for operation with a 128/192fs system clock, e.g. for 192kHz operation where the oversampling rate is 64fs. For ADC operation at 96kHz it is recommended that the user set the ADCOSR bit. This changes the ADC signal processing oversample rate to 64fs. SAMPLING RATE (DACLRC/ ADCLRC) 128fs 32kHz 4.096 6.144 8.192 12.288 16.384 24.576 44.1kHz 5.6448 8.467 11.2896 16.9340 22.5792 33.8688 24.576 36.864 System Clock Frequency (MHz) 256fs 192fs 384fs 512fs 768fs DAC ONLY 48kHz 6.144 9.216 12.288 18.432 96kHz 12.288 18.432 24.576 36.864 192kHz 24.576 36.864 Unavailable Unavailable Unavailable Unavailable Unavailable Unavailable Table 6 System Clock Frequencies Versus Sampling Rate In Master mode DACBCLK, ADCBCLK, DACLRC and ADCLRC are generated by the WM8776. The frequencies of ADCLRC and DACLRC are set by setting the required ratio of DACMCLK to DACLRC and ADCMCLK to ADCLRC using the DACRATE and ADCRATE control bits (Table 7). ADCRATE[2:0]/ DACRATE[2:0] ADCMCLK/DACMCLK: ADCLRC/DACLRC RATIO 000 128fs (DAC Only) 001 192fs (DAC Only) 010 256fs 011 384fs 100 512fs 101 768fs Table 7 Master Mode MCLK:ADCLRC/DACLRC Ratio Select w PP Rev 1.91 June 2004 14 WM8776 Product Preview Table 8 shows the settings for ADCRATE and DACRATE for common sample rates and ADCMCLK/DACMCLK frequencies. SAMPLING RATE (DACLRC/ ADCLRC) System Clock Frequency (MHz) 128fs 192fs 256fs 384fs 512fs 768fs DACRATE =000 DACRATE =001 ADCRATE/ DACRATE =010 ADCRATE/ DACRATE =011 ADCRATE/ DACRATE =100 ADCRATE/ DACRATE =101 32kHz 4.096 6.144 8.192 12.288 16.384 24.576 44.1kHz 5.6448 8.467 11.2896 16.9340 22.5792 33.8688 24.576 36.864 48kHz 6.144 9.216 12.288 18.432 96kHz 12.288 18.432 24.576 36.864 192kHz 24.576 36.864 Unavailable Unavailable Unavailable Unavailable Unavailable Unavailable Table 8 Master Mode ADC/DACLRC Frequency Selection ADCBCLK and DACBCLK are also generated by the WM8776. The frequency of ADCBCLK and DACBCLK depends on the mode of operation. In 128/192fs modes (DACRATE=000 or 001) BCLK = MCLK/2. In 256/384/512fs modes (ADCRATE/DACRATE=010 or 011 or 100) BCLK = MCLK/4. However if DSP mode is selected as the audio interface mode then BCLK=MCLK. Note that DSP mode cannot be used in 128fs mode for word lengths greater than 16 bits or in 192fs mode for word lengths greater than 24 bits. ZERO DETECT The WM8776 has a zero detect circuit for each DAC channel, which detects when 1024 consecutive zero samples have been input. The two zero flag outputs (ZFLAGL and ZFLAGR) may be programmed to output the zero detect signals (see Table 9) that may then be used to control external muting circuits. A ‘1’ on ZFLAGL or ZFLAGR indicates a zero detect. The zero detect may also be used to automatically enable the PGA mute by setting IZD. The zero flag output may be disabled by setting DZFM to 00. The zero flag signal for each DAC channel will only be enabled if it is enabled as an input to the output summing stage. DZFM[1:0] 00 ZFLAGL ZFLAGR Zero flag disabled Zero flag disabled 01 Left channel zero Right channel zero 10 Both channel zero Both channel zero 11 Either channels zero Either channel zero Table 9 Zero Flag Output Select POWERDOWN MODES The WM8776 has powerdown control bits allowing specific parts of the WM8776 to be powered off when not being used. The 5-channel input source selector and input buffer may be powered down using control bit AINPD. When AINPD is set all inputs to the source selector (AIN1l/R to AIN5L/R) are switched to a buffered VMIDADC. Control bit ADCPD powers off the ADC and also the ADC input PGAs. The stereo DAC has a separate powerdown control bit, DACPD allowing the DAC and analogue output mixer to be powered off when not in use. This also switches the analogue outputs VOUTL/R to VMIDDAC to maintain a dc level on the output. Setting AINPD, ADCPD and DACPD will powerdown everything except the references VMIDADC, ADCREF and VMIDDAC. These may be powered down by setting PDWN. Setting PDWN will override all other powerdown control bits. It is recommended that AINPD, HPPD, ADCPD and DACPD are set before setting PDWN. The default is for all blocks to be enabled other than HPPD. w PP Rev 1.91 June 2004 15 WM8776 Product Preview POWER-ON-RESET The WM8776 has an internal power-on-reset circuit. The reset phase is entered at power-up of supplies. The DAC and ADC DSP circuitry is also reset when their respective master clocks are stopped. Register values are maintained unless either a power-on-reset occurs or a software reset is written. A software reset will also cause a reset of the DAC and ADC DSP. Figure 8 shows the power-on-reset logic, and Figure 9 shows the reset release characteristics. Figure 8 Circuit Diagram for Power-on-Reset Figure 9 Timing Diagram for Power on Sequence w PP Rev 1.91 June 2004 16 WM8776 Product Preview DIGITAL AUDIO INTERFACE MASTER AND SLAVE MODES The audio interface operates in either Slave or Master mode, selectable using the MS control bit. In both Master and Slave modes DIN is always an input to the WM8776 and DOUT is always an output. The default is Slave mode. In Slave mode (MS=0) ADCLRC, DACLRC, ADCBCLK and DACBCLK are inputs to the WM8776 (Figure 10). DIN and DACLRC are sampled by the WM8776 on the rising edge of DACBCLK, ADCLRC is sampled on the rising edge of ADCBCLK. ADC data is output on DOUT and changes on the falling edge of ADCBCLK. By setting control bit BCLKINV the polarity of ADCBCLK and DACBCLK may be reversed so that DIN and DACLRC are sampled on the falling edge of DACBCLK, ADCLRC is sampled on the falling edge of ADCBCLK and DOUT changes on the rising edge of ADCBCLK. DACBCLK ADCBCLK WM8776 ADCLRC CODEC DACLRC DVD Controller DOUT DIN Figure 10 Slave Mode In Master mode (MS=1) ADCLRC, DACLRC, ADCBCLK and DACBCLK are outputs from the WM8776 (Figure 11). ADCLRC, DACLRC, ADCBCLK and DACBCLK are generated by the WM8776. DIN is sampled by the WM8776 on the rising edge of DACBCLK so the controller must output DAC data that changes on the falling edge of DACBCLK. ADC data is output on DOUT and changes on the falling edge of ADCBCLK. By setting control bit BCLKINV, the polarity of ADCBCLK and DACBCLK may be reversed so that DIN is sampled on the falling edge of DACBCLK and DOUT changes on the rising edge of ADCBCLK. DACBCLK ADCBCLK ADCLRC WM8776 CODEC DACLRC DVD Controller DOUT DIN Figure 11 Master Mode w PP Rev 1.91 June 2004 17 WM8776 Product Preview AUDIO INTERFACE FORMATS Audio data is applied to the internal DAC filters or output from the ADC filters, via the Digital Audio Interface. 5 popular interface formats are supported: • Left Justified mode • Right Justified mode • I2S mode • DSP Early mode • DSP Late mode All 5 formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits, with the exception of 32 bit right justified mode, which is not supported. In left justified, right justified and I2S modes, the digital audio interface receives DAC data on the DIN input and outputs ADC data on DOUT. Audio Data for each stereo channel is time multiplexed with ADCLRC/DACLRC indicating whether the left or right channel is present. ADCLRC/DACLRC is also used as a timing reference to indicate the beginning or end of the data words. In left justified, right justified and I2S modes; the minimum number of BCLKs per DACLRC/ADCLRC period is 2 times the selected word length. ADCLRC/DACLRC must be high for a minimum of word length BCLKs and low for a minimum of word length BCLKs. Any mark to space ratio on ADCLRC/DACLRC is acceptable provided the above requirements are met. In DSP early or DSP late mode, DACLRC is used as a frame sync signal to identify the MSB of the first word. The minimum number of DACBCLKs per DACLRC period is 2 times the selected word length. Any mark to space ratio is acceptable on DACLRC provided the rising edge is correctly positioned. The ADC data may also be output in DSP early or late modes, with ADCLRC used as a frame sync to identify the MSB of the first word. The minimum number of ADCBCLKs per ADCLRC period is 2 times the selected word length. LEFT JUSTIFIED MODE In left justified mode, the MSB of DIN is sampled by the WM8776 on the first rising edge of DACBCLK following a DACLRC transition. The MSB of the ADC data is output on DOUT and changes on the same falling edge of ADCBCLK as ADCLRC and may be sampled on the rising edge of ADCBCLK. ADCLRC and DACLRC are high during the left samples and low during the right samples (Figure 12). 1/fs LEFT CHANNEL RIGHT CHANNEL DACLRC/ ADCLRC DACBCLK/ ADCBCLK DIN/ DOUT 1 MSB 2 3 n-2 n-1 n LSB 1 MSB 2 3 n-2 n-1 n LSB Figure 12 Left Justified Mode Timing Diagram w PP Rev 1.91 June 2004 18 WM8776 Product Preview RIGHT JUSTIFIED MODE In right justified mode, the LSB of DIN is sampled by the WM8776 on the rising edge of DACBCLK preceding a DACLRC transition. The LSB of the ADC data is output on DOUT and changes on the falling edge of ADCBCLK preceding a ADCLRC transition and may be sampled on the rising edge of ADCBCLK. ADCLRC and DACLRC are high during the left samples and low during the right samples (Figure 13). 1/fs LEFT CHANNEL RIGHT CHANNEL DACLRC/ ADCLRC DACBCLK/ ADCBCLK DIN/ DOUT 1 2 3 n-2 n-1 MSB n 1 LSB 2 3 n-2 n-1 MSB n LSB Figure 13 Right Justified Mode Timing Diagram 2 I S MODE In I2S mode, the MSB of DIN is sampled by the WM8776 on the second rising edge of DACBCLK following a DACLRC transition. The MSB of the ADC data is output on DOUT and changes on the first falling edge of ADCBCLK following an ADCLRC transition and may be sampled on the rising edge of ADCBCLK. ADCLRC and DACLRC are low during the left samples and high during the right samples. 1/fs LEFT CHANNEL RIGHT CHANNEL DACLRC/ ADCLRC DACBCLK/ ADCBCLK 1 BCLK 1 BCLK DIN/ DOUT 1 2 3 n-2 n-1 MSB n LSB 1 MSB 2 3 n-2 n-1 n LSB 2 Figure 14 I S Mode Timing Diagram DSP EARLY MODE In DSP early mode, the MSB of DAC left data is sampled by the WM8776 on the second rising edge on DACBCLK following a DACLRC rising edge. DAC right data follows DAC channel left data (Figure 15). w PP Rev 1.91 June 2004 19 WM8776 Product Preview 1 BCLK 1 BCLK 1/fs DACLRC DACBCLK LEFT CHANNEL DIN 1 2 RIGHT CHANNEL n-1 MSB n 1 2 n-1 NO VALID DATA n LSB Word Length (WL) Figure 15 DSP Early Mode Timing Diagram – DAC Data Input The MSB of the left channel ADC data is output on DOUT and changes on the first falling edge of ADCBCLK following a low to high ADCLRC transition and may be sampled on the rising edge of ADCBCLK. The right channel ADC data is contiguous with the left channel data (Figure 16) 1 BCLK 1 BCLK 1/fs ADCLRC ADCBCLK LEFT CHANNEL DOUT 1 2 n-1 MSB RIGHT CHANNEL n 1 2 n-1 NO VALID DATA n LSB Word Length (WL) Figure 16 DSP Early Mode Timing Diagram – ADC Data Output DSP LATE MODE In DSP late mode, the MSB of DAC left data is sampled by the WM8776 on the first DACBCLK rising edge following a DACLRC rising edge. DAC right follow DAC left data (Figure 17). 1/fs DACLRC DACBCLK LEFT CHANNEL DIN 1 2 n-1 MSB RIGHT CHANNEL n 1 2 n-1 NO VALID DATA n 1 LSB Word Length (WL) Figure 17 DSP Late Mode Timing Diagram – DAC Data Input w PP Rev 1.91 June 2004 20 WM8776 Product Preview The MSB of the left channel ADC data is output on DOUT and changes on the same falling edge of ADCBCLK as the low to high ADCLRC transition and may be sampled on the rising edge of ADCBCLK. The right channel ADC data is contiguous with the left channel data (Figure 18). 1/fs ADCLRC ADCBCLK LEFT CHANNEL DOUT 1 2 n-1 MSB RIGHT CHANNEL n 1 2 n-1 NO VALID DATA n 1 LSB Word Length (WL) Figure 18 DSP Late Mode Timing Diagram – ADC Data Output In both early and late DSP modes, the left channel is always sent first, followed immediately by the right channel. No DACBCLK edges are allowed between the data words. CONTROL INTERFACE OPERATION The WM8776 is controlled by writing to registers through a serial control interface. A control word consists of 16 bits. The first 7 bits (B15 to B9) are address bits that select which control register is accessed. The remaining 9 bits (B8 to B0) are data bits, corresponding to the 9 bits in each control register. The control interface can operate as either a 3-wire or 2-wire MPU interface. The MODE pin selects the interface format, as shown in Table 10. . MODE Control Mode 0 2 wire interface 1 3 wire interface Table 10 Control Interface Selection via MODE Pin The control interface is 5V tolerant, meaning that the control interface input signals CE, CL and DI as well as MODE may have an input high level of 5V while DVDD is 3V. Input thresholds are determined by DVDD. 3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE In 3-wire mode, every rising edge of CL clocks in one data bit from the DI pin. A rising edge on CE latches in a complete control word consisting of the last 16 bits. The 3-wire interface protocol is shown in Figure 19. latch CE CL DI B15 B14 B13 B12 B11 B10 B9 control register address B8 B7 B6 B5 B4 B3 B2 B1 B0 control register data bits Figure 19 3-wire SPI Compatible Interface w PP Rev 1.91 June 2004 21 WM8776 Product Preview B[15:9] are Control Address Bits B[8:0] are Control Data Bits CE is edge sensitive – the data is latched on the rising edge of CE. 2-WIRE SERIAL CONTROL MODE The WM8776 supports software control via a 2-wire serial bus. Many devices can be controlled by the same bus, and each device has a unique 7-bit address (this is not the same as the 7-bit address of each register in the WM8776). The WM8776 operates as a slave device only. The controller indicates the start of data transfer with a high to low transition on DI while CL remains high. This indicates that a device address and data will follow. All devices on the 2-wire bus respond to the start condition and shift in the next eight bits on DI (7-bit address + Read/Write bit, MSB first). If the device address received matches the address of the WM8776 and the R/W bit is ‘0’, indicating a write, then the WM8776 responds by pulling DI low on the next clock pulse (ACK). If the address is not recognised or the R/W bit is ‘1’, the WM8776 returns to the idle condition and wait for a new start condition and valid address. Once the WM8776 has acknowledged a correct address, the controller sends the first byte of control data (B15 to B8, i.e. the WM8776 register address plus the first bit of register data). The WM8776 then acknowledges the first data byte by pulling DI low for one clock pulse. The controller then sends the second byte of control data (B7 to B0, i.e. the remaining 8 bits of register data), and the WM8776 acknowledges again by pulling DI low. The transfer of data is complete when there is a low to high transition on DI while CL is high. After receiving a complete address and data sequence the WM8776 returns to the idle state and waits for another start condition. If a start or stop condition is detected out of sequence at any point during data transfer (i.e. DI changes while CL is high), the device jumps to the idle condition. Figure 20 2-wire Serial Interface B[15:9] are Control Address Bits B[8:0] are Control Data Bits The WM8776 has two possible device addresses, which can be selected using the CE pin. CE STATE DEVICE ADDRESS Low 0011010 (0 x 34h) High 0011011 (0 x 36h) Table 11 2-Wire MPU Interface Address Selection w PP Rev 1.91 June 2004 22 WM8776 Product Preview CONTROL INTERFACE REGISTERS DIGITAL AUDIO INTERFACE CONTROL REGISTER Interface format is selected via the FMT[1:0] register bits: REGISTER ADDRESS BIT LABEL DEFAULT R10 (0Ah) 0001010 DAC Interface Control 1:0 DACFMT [1:0] 10 R11 (0Bh) 0001011 ADC Interface Control 1:0 ADCFMT [1:0] 10 DESCRIPTION Interface format Select 00 : right justified mode 01: left justified mode 10: I2S mode 11: DSP (early or late) mode In left justified, right justified or I2S modes, the LRP register bit controls the polarity of ADCLRC/DACLRC. If this bit is set high, the expected polarity of ADCLRC/DACLRC will be the opposite of that shown Figure 12, Figure 13, etc. Note that if this feature is used as a means of swapping the left and right channels, a 1 sample phase difference will be introduced. In DSP modes, the LRP register bit is used to select between early and late modes. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R10 (0Ah) 0001010 DAC Interface Control 2 DACLRP 0 R11 (0Bh) 0001011 ADC Interface Control 2 ADCLRP 0 In left/right/ I2S modes: ADCLRC/DACLRC Polarity (normal) 0 : normal ADCLRC/DACLRC polarity 1: inverted ADCLRC/DACLRC polarity In DSP mode: 0 : Early DSP mode 1: Late DSP mode By default, ADCLRC, DACLRC and DIN are sampled on the rising edge of ADCBCLK and DACBCLK and should ideally change on the falling edge. Data sources that change ADCLRC/DACLRC and DIN on the rising edge of ADCBCLK/DACBCLK can be supported by setting the BCP register bit. Setting BCP to 1 inverts the polarity of BCLK to the inverse of that shown in Figure 12, Figure 13, etc. REGISTER ADDRESS BIT LABEL DEFAULT R10 (0Ah) 0001010 DAC Interface Control 3 DACBCP 0 R11 (0Bh) 0001011 ADC Interface Control 3 ADCBCP 0 DESCRIPTION BCLK Polarity (DSP modes) 0 : normal BCLK polarity 1: inverted BCLK polarity The WL[1:0] bits are used to control the input word length. REGISTER ADDRESS BIT LABEL DEFAULT R10 (0Ah) 0001010 DAC Interface Control 5:4 DACWL [1:0] 10 R11 (0Bh) 0001011 ADC Interface Control 5:4 ADCWL [1:0] 10 DESCRIPTION Word Length 00 : 16 bit data 01: 20 bit data 10: 24 bit data 11: 32 bit data Note: If 32-bit mode is selected in right justified mode, the WM8776 defaults to 24 bits. In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If the DAC is programmed to receive 16 or 20 bit data, the WM8776 pads the unused LSBs with zeros. If the DAC is programmed into 32 bit mode, the 8 LSBs are ignored. w PP Rev 1.91 June 2004 23 WM8776 Product Preview 2 Note: In 24 bit I S mode, any width of 24 bits or less is supported provided that ADCLRC/DACLRC is high for a minimum of 24 BCLKs and low for a minimum of 24 BCLKs. A number of options are available to control how data from the Digital Audio Interface is applied to the DAC. MASTER MODES Control bit ADCMS selects between audio interface Master and Slave Modes for ADC. In ADC Master mode ADCLRC and ADCBCLK are outputs and are generated by the WM8776. In Slave mode ADCLRC and ADCBCLK are inputs to WM8776. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R12 (0Ch) 0001100 Interface Control 9 ADCMS 0 Audio Interface Master/Slave Mode select for ADC: 0 : Slave Mode 1: Master Mode Control bit DACMS selects between audio interface Master and Slave Modes for the DAC. In DAC Master mode DACLRC and DACBCLK are outputs and are generated by the WM8776. In Slave mode DACLRC and DACBCLK are inputs to WM8776. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R12 (0Ch) 0001100 Interface Control 8 DACMS 0 Audio Interface Master/Slave Mode select for DAC: 0 : Slave Mode 1: Master Mode MASTER MODE ADCLRC/DACLRC FREQUENCY SELECT In ADC Master mode the WM8776 generates ADCLRC and ADCBCLK, in DAC master mode the WM8776 generates DACLRC and DACBCLK. These clocks are derived from the master clock (ADCMCLK or DACMCLK). The ratios of ADCMCLK to ADCLRC and DACMCLK to DACLRC are set by ADCRATE and DACRATE respectively. w REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R12 (0Ch) 0001100 ADCLRC and DACLRC frequency select 2:0 ADCRATE[2:0] 010 Master Mode MCLK:ADCLRC ratio select: 010: 256fs 011: 384fs 100: 512fs 101: 768fs 6:4 DACRATE[2:0] 010 Master Mode MCLK:DACLRC ratio select: 000: 128fs 001: 192fs 010: 256fs 011: 384fs 100: 512fs 101: 768fs PP Rev 1.91 June 2004 24 WM8776 Product Preview ADC OVERSAMPLING RATE SELECT For ADC operation at 96kHz it is recommended that the user set the ADCOSR bit. This changes the ADC signal processing oversample rate to 64fs. REGISTER ADDRESS BIT DEFAULT DESCRIPTION LABEL R12 (0Ch) 0001100 ADC Oversampling Rate 3 ADCOSR 0 ADC oversampling rate select 0: 128x oversampling 1: 64x oversampling MUTE MODES Setting MUTE for the DAC will apply a ‘soft’ mute to the input of the digital filters of the channel muted. REGISTER ADDRESS BIT LABEL DEFAULT R8 (08h) 0001000 DAC Mute 0 DMUTE 0 DESCRIPTION DAC Soft Mute select 0 : Normal Operation 1: Soft mute enabled 1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 0 0.001 0.002 0.003 0.004 0.005 0.006 Time(s) Figure 21 Application and Release of Soft Mute Figure 21 shows the application and release of DMUTE whilst a full amplitude sinusoid is being played at 48kHz sampling rate. When DMUTE (lower trace) is asserted, the output (upper trace) begins to decay exponentially from the DC level of the last input sample. The output will decay towards VMID with a time constant of approximately 64 input samples. If DMUTE is applied to both channels for 1024 or more input samples the DAC will be muted if IZD is set. When DMUTE is de-asserted, the output will restart immediately from the current input sample. Note that all other means of muting the DAC: setting the PL[3:0] bits to 0, setting the PDWN bit or setting attenuation to 0 will cause much more abrupt muting of the output. w PP Rev 1.91 June 2004 25 WM8776 Product Preview ADC MUTE Each ADC channel also has an individual mute control bit, which mutes the input to the ADC PGA. By setting the LRBOTH bit (reg22, bit 8) both channels can be muted simultaneously. REGISTER ADDRESS BIT LABEL DEFAULT R21 (15h) 0010101 ADC Mute Left 7 MUTELA 0 ADC Mute select 0 : Normal Operation 1: mute ADC left DESCRIPTION R21 (15h) 0001111 ADC Mute Right 6 MUTERA 0 ADC Mute select 0 : Normal Operation 1: mute ADC right DE-EMPHASIS MODE The De-emphasis filter for the DAC is enabled under the control of DEEMP. REGISTER ADDRESS BIT LABEL DEFAULT R9 (09h) 0001001 DAC De-emphasis Control 0 DEEMPH 0 DESCRIPTION De-emphasis mode select: 0 : Normal Mode 1: De-emphasis Mode Refer to Figure 34, Figure 35, Figure 36, Figure 37, Figure 38 and Figure 39 for details of the De-Emphasis modes at different sample rates. POWERDOWN MODE AND ADC/DAC DISABLE Setting the PDWN register bit immediately powers down the WM8776, including the references, overriding all other powerdown control bits. All trace of the previous input samples is removed, but all control register settings are preserved. When PDWN is cleared, the digital filters will be re-initialised. It is recommended that the 5-channel input mux and buffer, ADC and DAC are powered down before setting PDWN. REGISTER ADDRESS BIT LABEL DEFAULT R13 (0Dh) 0001101 Powerdown Control 0 PDWN 0 DESCRIPTION Power Down Mode Select: 0 : Normal Mode 1: Power Down Mode The ADC, DAC and HEADPHONE PGA’S may also be powered down by setting the ADCD and DACD disable bits. Setting ADCD will disable the ADC and select a low power mode. The ADC digital filters will be reset and will reinitialise when ADCD is reset. The DAC has a separate disable DACD. Setting DACD will disable the DAC, mixer and output PGAs. Resetting DACD will reinitialise the digital filters. REGISTER ADDRESS BIT LABEL DEFAULT R13 (0Dh) 0001101 Powerdown Control 1 ADCPD 0 ADC Powerdown: 0 : Normal Mode 1: Power Down Mode DESCRIPTION 2 DACPD 0 DAC Powerdown: 0 : Normal Mode 1: Power Down Mode 3 HPPD 1 Headphone output/PGA Power down : 0 : HP out enabled 1 : HP out disabled The analogue audio inputs and outputs can also be individually powered down by setting the relevant bits in the powerdown register. w PP Rev 1.91 June 2004 26 WM8776 Product Preview REGISTER ADDRESS BIT LABEL DEFAULT R13 (0Dh) 0001101 Powerdown Control 6 AINPD 0 DESCRIPTION Analogue input PGA disable: 0 : Normal Mode 1: Power Down Mode DIGITAL ATTENUATOR CONTROL MODE Setting the ATC register bit causes the left channel attenuation settings to be applied to both left and right channel DACs from the next audio input sample. No update to the attenuation registers is required for ATC to take effect. REGISTER ADDRESS BIT LABEL DEFAULT R7 (07h) 0000111 DAC Channel Control 1 ATC 0 DESCRIPTION Attenuator Control Mode: 0 : Right channel use Right attenuation 1: Right Channel use Left Attenuation INFINITE ZERO DETECT ENABLE Setting the IZD register bit will enable the internal infinite zero detect function: REGISTER ADDRESS BIT LABEL DEFAULT R7 (07h) 0000111 DAC Channel Control 2 IZD 0 DESCRIPTION Infinite zero Mute Enable 0 : disable infinite zero mute 1: enable infinite zero Mute With IZD enabled, applying 1024 consecutive zero input samples to the DAC will cause both DAC outputs to be muted. Mute will be removed as soon as any channel receives a non-zero input. DAC OUTPUT CONTROL The DAC output control word determines how the left and right inputs to the audio Interface are applied to the left and right DACs: w REGISTER ADDRESS BIT LABEL DEFAULT R7 (07h) 0000111 DAC Control 7:4 PL[3:0] 1001 DESCRIPTION PL[3:0] Left Output Right Output 0000 Mute Mute 0001 Left Mute 0010 Right Mute 0011 (L+R)/2 Mute 0100 Mute Left 0101 Left Left 0110 Right Left 0111 (L+R)/2 Left 1000 Mute Right 1001 Left Right 1010 Right Right 1011 (L+R)/2 Right 1100 Mute (L+R)/2 1101 Left (L+R)/2 1110 Right (L+R)/2 1111 (L+R)/2 (L+R)/2 PP Rev 1.91 June 2004 27 WM8776 Product Preview ANALOGUE OUTPUT VOLUME CONTROLS There are analogue volume controls for the headphone outputs which may be adjusted independently using separate volume control registers. REGISTER ADDRESS BIT LABEL DEFAULT R0 (00h) 0000000 Analogue Attenuation Headphone Output Left 6:0 HPLA[6:0] 1111001 (0dB) 7 HPLZCEN 0 8 UPDATE Not latched Controls simultaneous update of Headphone Attenuation Latches 0: Store HPLA in intermediate latch (no change to output) 1: Store HPLA and update attenuation on both channels. R1 (01h) 0000001 Analogue Attenuation Headphone Output Right 6:0 HPLA[6:0] 1111001 (0dB) Attenuation data for Headphone Right channel in 1dB steps. See Table 13 7 HPRZCEN 0 8 UPDATE Not latched Controls simultaneous update of Headphone Attenuation Latches 0: Store HPRA in intermediate latch (no change to output) 1: Store HPRA and update attenuation on both channels. R2 (02h) 0000010 Headphone Master Analogue Attenuation (both channels) 6:0 HPMASTA [6:0] 1111001 (0dB) Attenuation data for both Headphone channels in 1dB steps. See Table 13 7 MZCEN 0 8 UPDATEA Not latched R13 (0Dh) 0001101 Power Down 3 HPPD 1 DESCRIPTION Attenuation data for Headphone Left channel in 1dB steps. See Table 13 Headphone left zero cross detect enable 0: zero cross disabled 1: zero cross enabled Headphone right zero cross detect enable 0: zero cross disabled 1: zero cross enabled Master zero cross detect enable 0: zero cross disabled 1: zero cross enabled Controls simultaneous update of Attenuation Latches 0: Store gain in intermediate latch (no change to output) 1: Store gain and update attenuation on all channels. Headphone output/PGA Power Down 0 : HP out enabled 1 : HP out disabled Table 12 Headphone Attenuation Register Map Each analogue headphone output channel has a PGA which can be used to attenuate the output from that channel. The PGA’s can be powered up or down using the HPPD bit. Attenuation is 0dB by default but can be set between +6dB and –73dB in 1dB steps using the two Attenuation control words. The attenuation registers are double latched allowing them to be updated in pairs. Setting the UPDATE bit on an attenuation write to one channel, for example HPOUTL, will cause the pre-latched value in HPOUTR to be applied to the PGA. A master attenuation register is also included, allowing both volume levels to be set to the same value in a single write. Note: The UPDATE bit is not latched. If UPDATE=0, the Attenuation value will be written to the pre-latch but not applied to the PGA. If UPDATE=1, pre-latched values will be applied from the next input sample. Writing to HPMASTA[6:0] overwrites any values previously sent to HPLA[6:0] and HPRA[6:0]. HEADPHONE OUTPUT PGA ATTENUATION The analogue output PGAs are controlled by the HPLA and HPRA registers. Register bits MASTA can be used to control attenuation of both channels. Table 13 shows how the attenuation levels are selected from the 7-bit words. w PP Rev 1.91 June 2004 28 WM8776 Product Preview HPLA/ HPRA[6:0] ATTENUATION LEVEL 00(hex) -∞dB (mute) : : 2F(hex) -∞dB (mute) 30(hex) -73dB : : 79 (hex) 0dB (default) : : 7D(hex) +4dB 7E(hex) +5dB 7F(hex) +6dB Table 13 Headphone Volume Control Attenuation Levels In addition a zero cross detect circuit is provided for the output PGA volume under the control of bit 7 (ZCEN) in the each attenuation register. When ZCEN is set the attenuation values are only updated when the input signal to the gain stage is close to the analogue ground level. This minimises audible clicks and ‘zipper’ noise as the gain values change. A timeout clock is also provided which will generate an update after a minimum of 131072 master clocks (= ~10.5ms with a master clock of 12.288MHz). The timeout clock may be disabled by setting TOD. REGISTER ADDRESS BIT R7 (07h) 0000111 Timeout Clock Disable 3 LABEL TOD DEFAULT 0 DESCRIPTION DAC and ADC Analogue Zero cross detect timeout disable 0 : Timeout enabled 1: Timeout disabled DAC DIGITAL VOLUME CONTROL The DAC volume may also be adjusted in the digital domain using independent digital attenuation control registers REGISTER ADDRESS BIT LABEL DEFAULT R3 (03h) 0000011 Digital Attenuation DACL 7:0 LDA[7:0] 11111111 (0dB) 8 UPDATED Not latched R4 (04h) 0000100 Digital Attenuation DACR 7:0 RDA[6:0] 11111111 (0dB) 8 UPDATED Not latched R5 (05h) 0000101 Master Digital Attenuation (both channels) 7:0 MASTDA[7:0] 11111111 (0dB) 8 UPDATED Not latched w DESCRIPTION Digital Attenuation data for Left channel DACL in 0.5dB steps. See Table 14 Controls simultaneous update of Attenuation Latches 0: Store LDA in intermediate latch (no change to output) 1: Store LDA and update attenuation on both channels Digital Attenuation data for Right channel DACR in 0.5dB steps. See Table 14 Controls simultaneous update of Attenuation Latches 0: Store RDA in intermediate latch (no change to output) 1: Store RDA and update attenuation on both channels. Digital Attenuation data for DAC channels in 0.5dB steps. See Table 14 Controls simultaneous update of Attenuation Latches 0: Store gain in intermediate latch (no change to output) 1: Store gain and update attenuation on channels. PP Rev 1.91 June 2004 29 WM8776 Product Preview L/RDA[7:0] ATTENUATION LEVEL 00(hex) -∞ dB (mute) 01(hex) -127dB : : : : : : FE(hex) -0.5dB FF(hex) 0dB Table 14 Digital Volume Control Attenuation Levels The digital volume control also incorporates a zero cross detect circuit which detects a transition through the zero point before updating the digital volume control with the new volume. This is enabled by control bit DZCEN. REGISTER ADDRESS BIT LABEL DEFAULT R7 (07h) 0000111 DAC Control 0 DZCEN 0 DESCRIPTION DAC Digital Volume Zero Cross Enable: 0: Zero cross detect disabled 1: Zero cross detect enabled DAC OUTPUT PHASE The DAC Phase control word determines whether the output of the DAC is non-inverted or inverted REGISTER ADDRESS BIT LABEL DEFAULT R6 (06h) 0000110 DAC Phase 1:0 PH[1:0] 00 DESCRIPTION Bit DAC Phase 0 DACL 1 = invert 1 DACR 1 = invert ADC GAIN CONTROL The ADC has an analogue input PGA and digital gain control for each stereo channel. Both the analogue and digital gains are adjusted by the same register, LAG for the left and RAG for the right. The analogue PGA has a range of +24dB to -21dB in 0.5dB steps. The digital gain control allows further attenuation (after the ADC) from -21.5dB to -103dB in 0.5dB steps. Table 15 shows how the register maps the analogue and digital gains. LAG/RAG[7:0] ATTENUATION LEVEL (AT OUTPUT) ANALOGUE PGA DIGITAL ATTENUATION 00(hex) -∞ dB (mute) -21dB Digital mute 01(hex) -103dB -21dB -82dB : : : : A4(hex) -21.5dB -21dB -0.5dB A5(hex) -21dB -21dB 0dB : : : : CF(hex) 0dB 0dB 0dB : : : : FE(hex) +23.5dB +23.5dB 0dB FF(hex) +24dB +24dB 0dB Table 15 Analogue and Digital Gain Mapping for ADC In addition, a zero cross detect circuit is provided for the input PGA, controlled by bit 8 in each attenuation register. This minimises audible clicks and ‘zipper’ noise by updating the gain when the signal crosses the zero level. w PP Rev 1.91 June 2004 30 WM8776 Product Preview In addition a zero cross detect circuit is provided for the output PGA volume under the control of bit 7 (ZCEN) in the each attenuation register. When ZCEN is set the attenuation values are only updated when the input signal to the gain stage is close to the analogue ground level. This minimises audible clicks and ‘zipper’ noise as the gain values change. A timeout clock is also provided which will generate an update after a minimum of 131072 master clocks (= ~10.5ms with a master clock of 12.288MHz). The timeout clock may be disabled by setting TOD. Left and right inputs may also be independently muted. The LRBOTH control bit allows the user to write the same attenuation value to both left and right volume control registers, saving on software writes. The ADC volume and mute also applies to the bypass signal path. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R14 (0Eh) 0001110 Attenuation ADCL 7:0 LAG[7:0] 11001111 (0dB) 8 ZCLA 0 R15 (0Fh) 0001111 Attenuation ADCR 7:0 RAG[7:0] 11001111 (0dB) 8 ZCRA 0 Right channel ADC zero cross enable: 0: Zero cross disabled 1: Zero cross enabled R21 (15h) 0010101 ADC Input Mux 8 LRBOTH 0 Right channel input PGA controlled by left channel register 0 : Right channel uses RAG. 1 : Right channel uses LAG. R21 (15h) 0010101 ADC Input Mux 7 MUTELA 0 Mute for left channel ADC 0: Mute Off 1: Mute on 6 MUTERA 0 Mute for right channel ADC 0: Mute Off 1: Mute on Attenuation data for Left channel ADC gain in 0.5dB steps. See Table 15. Left channel ADC zero cross enable: 0: Zero cross disabled 1: Zero cross enabled Attenuation data for right channel ADC gain in 0.5dB steps. See Table 15. ADC HIGHPASS FILTER DISABLE The ADC digital filters contain a digital high pass filter. This defaults to enabled and can be disabled using software control bit ADCHPD. w REGISTER ADDRESS BIT LABEL DEFAULT R11 (0Bh) 0001011 ADC Control 8 ADCHPD 0 DESCRIPTION ADC High pass filter disable: 0: High pass filter enabled 1: High pass filter disabled PP Rev 1.91 June 2004 31 WM8776 Product Preview LIMITER / AUTOMATIC LEVEL CONTROL (ALC) The WM8776 has an automatic pga gain control circuit, which can function as a peak limiter or as an automatic level control (ALC). In peak limiter mode, a digital peak detector detects when the input signal goes above a predefined level and will ramp the pga gain down to prevent the signal becoming too large for the input range of the ADC. When the signal returns to a level below the threshold, the pga gain is slowly returned to its starting level. The peak limiter cannot increase the pga gain above its static level. input signal PGA gain signal after PGA Limiter threshold attack time decay time Figure 22 Limiter Operation In ALC mode, the circuit aims to keep a constant recording volume irrespective of the input signal level. This is achieved by continuously adjusting the PGA gain so that the signal level at the ADC input remains constant. A digital peak detector monitors the ADC output and changes the PGA gain if necessary. input signal PGA gain signal after ALC ALC target level hold time decay time attack time Figure 23 ALC Operation w PP Rev 1.91 June 2004 32 WM8776 Product Preview The gain control circuit is enabled by setting the LCEN control bit. The user can select between Limiter mode and three different ALC modes using the LCSEL control bits. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R17 (11h) 0010001 ALC Control 2 8 LCEN 0 Enable the PGA gain control circuit. 0 = Disabled 1 = Enabled R16 (10h) 0010000 ALC Control 1 8:7 LCSEL 00 LC function select 00 = Limiter 01 = ALC Right channel only 10 = ALC Left channel only 11 = ALC Stereo The limiter function only operates in stereo, which means that the peak detector takes the maximum of left and right channel peak values, and any new gain setting is applied to both left and right PGAs, so that the stereo image is preserved. However, the ALC function can also be enabled on one channel only. In this case, only one PGA is controlled by the ALC mechanism, while the other channel runs independently with its PGA gain set through the control register. When enabled, the threshold for the limiter or target level for the ALC is programmed using the LCT control bits. This allows the threshold/target level to be programmed between -1dB and -16dB in 1dB steps. REGISTER ADDRESS BIT LABEL DEFAULT R16 (10h) 0010000 ALC Control 1 3:0 LCT[3:0] 1011 (-5dB) DESCRIPTION Limiter Threshold/ALC target level in 1dB steps. 0000: -16dB FS 0001: -15dB FS … 1101: -3dB FS 1110: -2dB FS 1111: -1dB FS ATTACK AND DECAY TIMES The limiter and ALC have different attack and decay times which determine their operation. However, the attack and decay times are defined slightly differently for the limiter and for the ALC. DCY and ATK control the decay and attack times, respectively. Decay time (Gain Ramp-Up). When in ALC mode, this is defined as the time that it takes for the PGA gain to ramp up across 90% of its range (e.g. from –21dB up to +20 dB). When in limiter mode, it is defined as the time it takes for the gain to ramp up by 6dB. The decay time can be programmed in power-of-two (2n) steps. For the ALC this gives times from 33.6ms, 67.2ms, 134.4ms etc. to 34.41s. For the limiter this gives times from 1.2ms, 2.4ms etc., up to 1.2288s. Attack time (Gain Ramp-Down) When in ALC mode, this is defined as the time that it takes for the PGA gain to ramp down across 90% of its range (e.g. from +20dB down to -21dB gain). When in limiter mode, it is defined as the time it takes for the gain to ramp down by 6dB. The attack time can be programmed in power-of-two (2n) steps, from 8.4ms, 16.8ms, 33.6ms etc. to 8.6s for the ALC and from 250us, 500us, etc. up to 256ms. The time it takes for the recording level to return to its target value or static gain value therefore depends on both the attack/decay time and on the gain adjustment required. If the gain adjustment is small, it will be shorter than the attack/decay time. w PP Rev 1.91 June 2004 33 WM8776 Product Preview REGISTER ADDRESS BIT LABEL DEFAULT R18 (12h) 0010010 ALC Control 3 3:0 ATK[3:0] 0010 DESCRIPTION LC attack (gain ramp-down) time ALC mode 0000: 8.4ms 0001: 16.8ms 0010: 33.6ms… (time doubles with every step) 1010 or higher: 8.6s 7:4 DCY [3:0] Limiter Mode 0000: 250us 0001: 500us… 0010: 1ms (time doubles with every step) 1010 or higher: 256ms LC decay (gain ramp-up) time 0011 ALC mode 0000: 33.5ms 0001: 67.2ms 0010: 134.4ms ….(time doubles for every step) 1010 or higher: 34.3ms Limiter mode 0000: 1.2ms 0001: 2.4ms 0010: 4.8ms ….(time doubles for every step) 1010 or higher: 1.2288s TRANSIENT WINDOW (LIMITER ONLY) To prevent the limiter responding to to short duration high ampitude signals (such as handclaps in a live performance), the limiter has a programmable transient window preventing it responding to signals above the threshold until their duration exceeds the window period. The Transient window is set in register TRANWIN. REGISTER ADDRESS BIT LABEL DEFAULT R20 (14h) 0010100 Limiter Control 6:4 TRANWIN [2:0] 010 DESCRIPTION Length of Transient Window 000: 0us (disabled) 001: 62.5us 010: 125us ….. 111: 4ms ZERO CROSS The PGA has a zero cross detector to prevent gain changes introducing noise to the signal. In ALC mode the register bit ALCZC allows this to be turned off if desired. w REGISTER ADDRESS BIT LABEL DEFAULT R17 (11h) 0010001 ALC Control 2 7 ALCZC 0 (disabled) DESCRIPTION PGA zero cross enable 0 : disabled 1: enabled PP Rev 1.91 June 2004 34 WM8776 Product Preview MAXIMUM GAIN (ALC ONLY) AND MAXIMUM ATTENUATION To prevent low level signals being amplified too much by the ALC, the MAXGAIN register sets the upper limit for the gain. This prevents low level noise being over-amplified. The MAXGAIN register has no effect on the limiter operation. The MAXATTEN register has different operation for the limiter and for the ALC. For the limiter it defines the maximum attenuation below the static (user programmed) gain. For the ALC, it defines the lower limit for the gain. REGISTER ADDRESS BIT LABEL DEFAULT R16 (10h) 0010000 ALC Control 1 6:4 MAXGAIN 111 (+24dB) R20 (14h) 0010100 Limiter Control 3:0 MAXATTEN 0110 DESCRIPTION Set maximum gain for the PGA (ALC only) 111 : +24dB 110 : +20dB …..(-4dB steps) 010 : +4dB 001 : 0dB 000 : 0dB Maximum attenuation of PGA Limiter (attenuation below static) 0011 or lower: -3dB 0100: -4dB …. (-1dB steps) 1100 or higher: -12dB ALC (lower PGA gain limit) 1010 or lower: -1dB 1011 : -5dB ….. (-4dB steps) 1110 : -17dB 1111 : -21dB HOLD TIME (ALC ONLY) The ALC also has a hold time, which is the time delay between the peak level detected being below target and the PGA gain beginning to ramp up. It can be programmed in power-of-two (2n) steps, e.g. 2.67ms, 5.33ms, 10.67ms etc. up to 43.7ms. Alternatively, the hold time can also be set to zero. The hold time only applies to gain ramp-up, there is no delay before ramping the gain down when the signal level is above target. REGISTER ADDRESS BIT LABEL DEFAULT R17 (11h) 0010001 ALC Control 2 3:0 HLD[3:0] 0000 DESCRIPTION ALC hold time before gain is increased. 0000: 0ms 0001: 2.67ms 0010: 5.33ms … (time doubles with every step) 1111: 43.691s OVERLOAD DETECTOR (ALC ONLY) To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes an overload detector. If the ADC input signal exceeds 87.5% of full scale (–1.16dB), the PGA gain is ramped down at the maximum attack rate (as when ATK = 0000), until the signal level falls below 87.5% of full scale. This function is automatically enabled whenever the ALC is enabled. (Note: If ATK = 0000, then the overload detector makes no difference to the operation of the ALC. It is designed to prevent clipping when long attack times are used). w PP Rev 1.91 June 2004 35 WM8776 Product Preview NOISE GATE (ALC ONLY) When the signal is very quiet and consists mainly of noise, the ALC function may cause “noise pumping”, i.e. loud hissing noise during silence periods. The WM8776 has a noise gate function that prevents noise pumping by comparing the signal level at the AINL1/2/3/4/5 and/or AINR1/2/3/4/5 pins against a noise gate threshold, NGTH. The noise gate cuts in when: • Signal level at ADC [dB] < NGTH [dB] + PGA gain [dB] + Mic Boost gain [dB] This is equivalent to: • Signal level at input pin [dB] < NGTH [dB] When the noise gate is triggered, the PGA gain is held constant (preventing it from ramping up as it would normally when the signal is quiet). The table below summarises the noise gate control register. The NGTH control bits set the noise gate threshold with respect to the ADC full-scale range. The threshold is adjusted in 6dB steps. Levels at the extremes of the range may cause inappropriate operation, so care should be taken with set–up of the function. Note that the noise gate only works in conjunction with the ALC function, and always operates on the same channel(s) as the ALC (left, right, both, or none). w REGISTER ADDRESS BIT LABEL DEFAULT R19 (13h) 0010011 Noise Gate Control 0 NGAT 0 4:2 NGTH[2:0] 000 DESCRIPTION Noise gate function enable 1 = enable 0 = disable Noise gate threshold (with respect to ADC output level) 000: -78dBFS 001: -72dBfs … 6 dB steps 110: -42dBFS 111: -36dBFS PP Rev 1.91 June 2004 36 WM8776 Product Preview ADC INPUT MIXER AND POWERDOWN CONTROL REGISTER ADDRESS BIT LABEL DEFAULT R21 (15h) 0010101 ADC Input Mux 4:0 AMX[4:0] 00001 R13 (0Dh) 0001101 Powerdown Control 6 AINPD 0 DESCRIPTION ADC left channel input mixer control bits (see Table 16) Input mux and buffer powerdown 0: Input mux and buffer enabled 1: Input mux and buffer powered down Register bits AMX[4:0] control the left and right channel inputs into the stereo ADC. The default is AIN1. One bit of AMX is allocated to each stereo input pair to allow the signals to be mixed before being digitised by the ADC. For example, if AMX[4:0] is 00101, the input signal to the ADC will be (AIN1L+AIN3L) on the left channel and (AIN1R+AIN3R) on the right channel. However if the analogue input buffer is powered down, by setting AINPD, then all 5-channel mixer inputs are switched to buffered VMIDADC. AMX[4:0] LEFT ADC INPUT RIGHT ADC INPUT 00001 AIN1L AIN1R 00010 AIN2L AIN2R 00100 AIN3L AIN3R 01000 AIN4L AIN4R 10000 AIN5L AIN5R Table 16 ADC Input Mixer AIN1L/R AIN2L/R AIN3L/R AIN4L/R AIN5L/R AMX[0] AMX[1] AMX[2] AMX[3] AMX[4] Figure 24 ADC Input Mixer w PP Rev 1.91 June 2004 37 WM8776 Product Preview OUTPUT SELECT AND ENABLE CONTROL Register bits MX controls the output selection. The output select block consists of a summing stage and an input select switch for each input allowing each signal to be output individually or summed with other signals and output on the analogue output. The default for the output is DAC playback only. VOUT may be selected to output DAC playback, AUX, analogue bypass or a sum of these using the output select controls MX[2:0]. For example, to select sum of DAC and AUX, set MX[2:0] to 011. The output mixer is powered down with DACD. REGISTER ADDRESS BIT LABEL DEFAULT R22 (16h) 0010110 Output Mux 2:0 MX[2:0] 001 (DAC playback) DESCRIPTION VOUT Output select (see Figure 25) Figure 25 MX[2:0] Output Select SOFTWARE REGISTER RESET Writing any value to register 0010111 will cause a register reset, resetting all register bits to their default values. w PP Rev 1.91 June 2004 38 WM8776 Product Preview REGISTER MAP The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The WM8776 can be configured using the Control Interface. All unused bits should be set to ‘0’. REGISTER B B B 15 14 13 12 11 10 B B B B 9 B8 B7 B6 B5 B4 B3 R0 (00h) 0 0 0 0 0 0 0 UPDATE HPLZCEN R1 (01h) 0 0 0 0 0 0 1 UPDATE HPRZCEN R2 (02h) 0 0 0 0 0 1 0 UPDATEA HPMZCEN R3 (03h) 0 0 0 0 0 1 1 UPDATED LDA[7:0] 0FF R4 (04h) 0 0 0 0 1 0 0 UPDATED RDA[7:0] 0FF R5 (05h) 0 0 0 0 1 0 1 UPDATED R6 (06h) 0 0 0 0 1 1 0 0 R7 (07h) 0 0 0 0 1 1 1 0 R8 (08h) 0 0 0 1 0 0 0 0 R9 (09h) 0 0 0 1 0 0 1 R10 (0Ah) 0 0 0 1 0 1 0 R11 (0Bh) B1 B0 DEFAULT (HEX) HPLA[6:0] 079 HPRA[6:0] 079 HPMASTA[6:0] 079 MASTDA 0 0 0 0 PL[3:0] 0 0 0 0 0FF 0 0 PHASE[1:0] TOD IZD ATC DZCEN 000 090 0 0 0 DMUTE 000 0 0 0 0 0 0 0 0 DACWL[1:0] DACBCP DACLRP DACFMT[1:0] 022 ADCMCLK ADCWL[1:0] ADCBCP ADCLRP ADCFMT[1:0] 022 0 0 0 0 1 0 1 1 ADCHPD 0 R12 (0Ch) 0 0 0 1 1 0 0 ADCMS DACMS R13 (ODh) 0 0 0 1 1 0 1 0 0 R14 (0Eh) 0 0 0 1 1 1 0 ZCLA LAG[7:0] R15 (0Fh) 0 0 0 1 1 1 1 ZCRA RAG[7:0] R16 (10h) 0 0 1 0 0 0 0 R17 (11h) 0 0 1 0 0 0 1 LCEN R18 (12h) 0 0 1 0 0 1 0 FDECAY R19 (13h) 0 0 1 0 0 1 1 0 0 R20 (14h) 0 0 1 0 1 0 0 0 0 R21 (15h) 0 0 1 0 1 0 1 LRBOTH MUTELA R22 (16h) 0 0 1 0 1 1 0 0 0 R23 (17h) 0 0 1 0 1 1 1 w B2 DACRATE[2:0] AINPD LCSEL[1:0] ALCZC 0 ADCOSR 0 HPPD MAXGAIN[2:0] 0 0 0 0 ADCRATE[2:0] DACPD ADCPD PDWN 0 SOFTWARE RESET 022 008 0CF 07B HLD[3:0] 000 ATK[3:0] 032 0 MAXATTEN[3:0] AMX[4:0] 0 000 0CF NGTH[2:0] TRANWIN[2:0] MUTERA DEEMPH LCT[3:0] DCY[3:0] 0 DZFM [1:0] NGAT 000 0A6 001 MX[2:0] 001 not reset PP Rev 1.91 June 2004 39 WM8776 Product Preview REGISTER ADDRESS BIT LABEL DEFAULT R0 (00h) 0000000 Headphone Analogue Attenuation Headphone Left 6:0 HPLA[6:0] 1111001 (0dB) 7 HPLZCEN 0 8 UPDATE Not latched 6:0 HPRA[6:0] 1111001 (0dB) 7 HPRZCEN 0 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0: Store HPRA in intermediate latch (no change to output) 1: Store HPRA and update attenuation on all channels. 6:0 HPMASTA[6:0] 1111001 (0dB) Attenuation data for all ANALOGUE gains (L and R channels) in 1dB steps. 7 MZCEN 0 8 UPDATE Not latched R3 (03h) 0000011 Digital Attenuation DACL 7:0 LDA1[7:0] 11111111 (0dB) 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0: Store LDA1 in intermediate latch (no change to output) 1: Store LDA1 and update attenuation on all channels R4 (04h) 0000100 Digital Attenuation DACR 7:0 RDA1[6:0] 11111111 (0dB) Digital Attenuation data for Right channel DACR in 0.5dB steps. 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0: Store RDA1 in intermediate latch (no change to output) 1: Store RDA1 and update attenuation on all channels. R5 (05h) 0000101 Master Digital Attenuation (All Channels 7:0 MASTDA[7:0] 11111111 (0dB) 8 UPDATE Not latched R1 (01h) 0000001 Headphone Analogue Attenuation Headphone Right R2 (02h) 0000010 Headphone Master Analogue Attenuation (All Channels) w DESCRIPTION Attenuation data for HEADPHONE left channel in 1dB steps. Left HEADPHONE zero cross detect enable 0: zero cross disabled 1: zero cross enabled Controls simultaneous update of all Attenuation Latches 0: Store HPLA in intermediate latch (no change to output) 1: Store HPLA and update attenuation on all channels. Attenuation data for Headphone right channel in 1dB steps. Right Headphone zero cross detect enable 0: zero cross disabled 1: zero cross enabled Master zero cross detect enable 0: zero cross disabled 1: zero cross enabled Controls simultaneous update of all Attenuation Latches 0: Store gains in intermediate latch (no change to output) 1: Store gains and update attenuation on all channels. Digital Attenuation data for Left channel DACL in 0.5dB steps. Digital Attenuation data for all DAC channels in 0.5dB steps. Controls simultaneous update of all Attenuation Latches 0: Store gain in intermediate latch (no change to output) 1: Store gain and update attenuation on all channels. PP Rev 1.91 June 2004 40 WM8776 Product Preview REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R6 (06h) 0000110 Phase Swaps 1:0 PHASE 00 Controls phase of DAC outputs (LEFT, RIGHT channel) 0: Sets non inverted output phase 1: inverts phase of DAC output R7 (07h) 0000111 DAC Control 0 DZCEN 0 DAC Digital Volume Zero Cross Enable: 0: Zero Cross detect disabled 1: Zero Cross detect enabled 1 ATC 0 Attenuator Control 0: All DACs use attenuations as programmed. 1: Right DAC uses left DAC attenuations 2 IZD 0 Infinite zero detection circuit control and automute control 0: Infinite zero detect automute disabled 1: Infinite zero detect automute enabled 3 TOD 0 7:4 PL[3:0] 1001 DAC and ADC Analogue Zero cross detect timeout disable 0 : Timeout enabled 1: Timeout disabled DAC Output Control PL[3:0] Left Output Right Output Left Output Right Output 0000 Mute Mute 1000 Mute Right 0001 Left Mute 1001 Left Right 0010 Right Mute 1010 Right Right 0011 (L+R)/2 Mute 1011 (L+R)/2 Right 0100 Mute Left 1100 Mute (L+R)/2 0101 Left Left 1101 Left (L+R)/2 0110 Right Left 1110 Right (L+R)/2 0111 (L+R)/2 Left 1111 (L+R)/2 (L+R)/2 R8 (08h) 0001000 DAC Mute 0 DMUTE 0 DAC channel soft mute enables: 0: mute disabled 1: mute enabled R9 (09h) 0001001 DAC Control 0 DEEMPH 0 De-emphasis mode select: 0 : Normal Mode 1: De-emphasis Mode 2:1 DZFM 00 DZFM 00 01 10 11 w PL[3:0] ZFLAG1 disabled left channels zero both channels zero either channel zero ZFLAG2 disabled right channels zero both channels zero either channel zero PP Rev 1.91 June 2004 41 WM8776 Product Preview REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R10 (0Ah) 0001010 DAC Interface Control 1:0 DACFMT[1:0] 10 DAC Interface format select 00: right justified mode 01: left justified mode 10: I2S mode 11: DSP mode 2 DACLRP 0 DACLRC Polarity or DSP Early/Late mode select Left Justified / Right Justified / I 2S 0: Standard DACLRC Polarity 1: Inverted DACLRC Polarity R11 (0Bh) 0001011 ADC Interface Control DSP Mode 0: Early Mode 1: Late Mode 3 DACBCP 0 DAC BITCLK Polarity 0: Normal – DIN and DACLRC sampled on rising edge of DACBCLK. 1: Inverted - DIN and DACLRC sampled on falling edge of DACBCLK. 5:4 DACWL[1:0] 10 DAC Input Word Length 00: 16-bit Mode 01: 20-bit Mode 10: 24-bit Mode 11: 32-bit Mode (not supported in right justified mode) 1:0 ADCFMT[1:0] 10 ADC Interface format select 00: right justified mode 01: left justified mode 10: I2S mode 11: DSP mode 2 ADCLRP 0 ADCLRC Polarity or DSP Early/Late mode select Left Justified / Right Justified / I 2S 0: Standard ADCLRC Polarity 1: Inverted ADCLRC Polarity DSP Mode 0: Early Mode 1: Late Mode 3 ADCBCP 0 ADC BITCLK Polarity 0: Normal - ADCLRC sampled on rising edge of ADCBCLK; DOUT changes on falling edge of ADCBCLK. 1: Inverted - ADCLRC sampled on falling edge of ADCBCLK; DOUT changes on rising edge of ADCBCLK. 5:4 ADCWL[1:0] 10 ADC Input Word Length 00: 16-bit Mode 01: 20-bit Mode 10: 24-bit Mode 11: 32-bit Mode (not supported in right justified mode) 6 ADCMCLK 0 ADCMCLK Polarity: 0: non-inverted 1: inverted 8 ADCHPD 0 ADC Highpass Filter Disable: 0: Highpass Filter enabled 1: Highpass Filter disabled w PP Rev 1.91 June 2004 42 WM8776 Product Preview REGISTER ADDRESS BIT LABEL DEFAULT R12 (0Ch) 0001100 Master Mode Control 2:0 ADCRATE[2:0] 010 3 ADCOSR 0 6:4 DACRATE[2:0] 010 7 DACMS 0 DAC Maser/Slave interface mode select 0: Slave Mode – DACLRC and DACBCLK are inputs 1: Master Mode –DACLRC and DACBCLK are outputs 8 ADCMS 0 ADC Maser/Slave interface mode select 0: Slave Mode – ADCLRC and ADCBCLK are inputs 1: Master Mode – ADCLRC and ADCBCLK are outputs 0 PDWN 0 Chip Powerdown Control (works in tandem with ADCD and DACD): 0: All circuits running, outputs are active 1: All circuits in power save mode, outputs muted 1 ADCPD 0 ADC powerdown: 0: ADC enabled 1: ADC disabled 2 DACPD 0 DAC powerdown 0: DAC enabled 1: DAC disabled 3 HPPD 1 Headphone Output/PGA’s powerdown 0: Headphone out enabled 1: Headphone out disabled 6 AINPD 0 AINPD powerdown 0: ANALOGUE INPUT enabled 1: ANALOGUE INPUT disabled 7:0 LAG[7:0] 11001111 (0dB) 8 ZCLA 0 R13 (0Dh) 0001101 PWR Down Control R14 (0Eh) 0001110 Attenuation ADCL w DESCRIPTION Master Mode ADCMCLK:ADCLRC ratio select: 010: 256fs 011: 384fs 100: 512fs ADC oversample rate select 0: 128x oversampling 1: 64x oversapmling Master Mode DACMCLK:DACLRC ratio select: 000: 128fs 001: 192fs 010: 256fs 011: 384fs 100: 512fs Attenuation data for Left channel ADC gain in 0.5dB steps. 00000000 : digital mute 00000001 : -103dB ……….. 11001111 : 0dB ………… 11111110 : +23.5dB 11111111 : +24dB Left ADC zero cross enable: 0: Zero cross disabled 1: Zero cross enabled PP Rev 1.91 June 2004 43 WM8776 Product Preview REGISTER ADDRESS BIT R15 (0Fh) 0001111 Attenuation ADCR 7:0 8 R16 (10h) 0010000 ALC Control 1 RAG[7:0] DEFAULT 11001111 (0dB) ZCRA 0 DESCRIPTION Attenuation data for right channel ADC gain in 0.5dB steps. 00000000 : digital mute 00000001 : -103dB ……….. 11001111 : 0dB ………… 11111110 : +23.5dB 11111111 : +24dB Right ADC zero cross enable: 0: Zero cross disabled 1: Zero cross enabled 3:0 LCT[3:0] 1011 (-5dB) Limiter threshold/ALC target level in 1dB steps 0000: -16dB FS 0001: -15dB FS … 1101: -3dB FS 1110: -2dB FS 1111: -1dB FS 6:4 MAXGAIN[2:0] 111 (+24dB) Set Maximum Gain of PGA 111 : +24dB 110 : +20dB ….(-4dB steps) 010 : +4dB 001 : 0dB 000 : 0dB LCSEL[1:0] 00 (Limiter) ALC/Limiter function select 00 = Limiter 01 = ALC Right channel only 10 = ALC Left channel only 11 = ALC Stereo (PGA registers unused) HLD[3:0] 0000 (OFF) ALC hold time before gain is increased. 0000: OFF 0001: 2.67ms 0010: 5.33ms … (time doubles with every step) 1111: 43.691s 7 ALCZC 0 (zero cross off) ALC uses zero cross detection circuit. 8 LCEN 0 Enable Gain control circuit. 0 = Disable 1 = Enable 8:7 R17 (11h) 0010001 ALC Control 2 LABEL 3:0 w PP Rev 1.91 June 2004 44 WM8776 Product Preview REGISTER ADDRESS BIT LABEL DEFAULT R18 (12h) 0011000 ALC Control 3 3:0 ATK[3:0] 0010 (33ms/1ms) 7:4 R19 (13h) 0010011 Noise Gate Control R20 (14h) 0010100 Limiter Control R21 (15h) 0010101 ADC Mux Control DCY[3:0] 0011 (268ms/ 9.6ms) 0 NGAT 0 4:2 NGTH 000 3:0 MAXATTEN [3:0] 0110 6:4 TRANWIN [2:0] 010 4:0 AMX[4:0] 00001 DESCRIPTION ALC/Limiter attack (gain ramp-down) time ALC mode 0000: 8.4ms 0001: 16.8ms 0010: 33.6ms… (time doubles with every step) 1010 or higher: 8.6s ALC/Limiter decay (gain ramp up) time ALC mode 0000: 33.5ms 0001: 67.2ms 0010: 134.4ms ….(time doubles for every step) 1010 or higher: 34.3ms Limiter mode 0000: 1.2ms 0001: 2.4ms 0010: 4.8ms ….(time doubles for every step) 1010 or higher: 1.2288s Noise gate enable (ALC only) 0 : disabled 1 : enabled Noise gate threshold 000: -78dBFS 001: -72dBfs … 6 dB steps 110: -42dBFS 111: -36dBFS Maximum attenuation of PGA Limiter (attenuation below static) 0011 or lower: -3dB 0100: -4dB …. (-1dB steps) 1100 or higher: -12dB ALC (lower PGA gain limit) 1010 or lower: -1dB 1011 : -5dB ….. (-4dB steps) 1110 : -17dB 1111 : -21dB Length of Transient Window 000: 0us (disabled) 001: 62.5us 010: 125us ….. 111: 4ms ADC left channel input mixer control bit AMX[4:0] 00001 00010 00100 01000 10000 ADC LEFT IN AIN1L AIN2L AIN3L AIN4L AIN5L 6 MUTERA 0 Mute for right channel ADC 0: Mute off 1: Mute on 7 MUTELA 0 Mute for left channel ADC 0: Mute off 1: Mute on w Limiter Mode 0000: 250us 0001: 500us… 0010: 1ms (time doubles with every step) 1010 or higher: 256ms ADC RIGHT IN AIN1R AIN2L AIN3R AIN4R AIN5R PP Rev 1.91 June 2004 45 WM8776 REGISTER ADDRESS Product Preview BIT LABEL DEFAULT 8 LRBOTH 0 Right channel input PGA controlled by left channel register 0 : Right channel uses RAG and MUTERA. 1 : Right channel uses LAG and MUTELA. R22 (16h) 0010110 Output Mux 2:0 MX[2:0] 001 VOUT Output select (Analogue ByPass Enable / Disable) 001: DAC 010: AUX 100: BYPASS R23 (17h) 0010111 Software Reset [8:0] RESET Not reset w DESCRIPTION Writing to this register will apply a reset to the device registers. PP Rev 1.91 June 2004 46 WM8776 Product Preview DIGITAL FILTER CHARACTERISTICS PARAMETER TEST CONDITIONS MIN ±0.01 dB 0 TYP MAX UNIT ADC Filter Passband 0.4535fs -6dB 0.5fs ±0.01 Passband ripple Stopband dB 0.5465fs Stopband Attenuation f > 0.5465fs -65 dB Group Delay 22 fs DAC Filter ±0.05 dB Passband 0.454fs -3dB 0.4892 fs ±0.05 Passband ripple Stopband dB 0.546fs Stopband Attenuation f > 0.546fs -60 dB Group Delay 19 fs Table 17 Digital Filter Characteristics DAC FILTER RESPONSES 10 0 0 -10 Response (dB) Response (dB) -20 -40 -60 -80 -20 -30 -40 -50 -60 -100 -70 -80 -120 0 0.5 1 1.5 2 2.5 3 Frequency (Fs) Figure 26 DAC Digital Filter Frequency Response – 44.1, 48 and 96kHz w 0.4 0.45 0.5 0.55 0.6 Frequency (Fs) Figure 27 DAC Digital Filter Transition Band – 44.1, 48 and 96kHz PP Rev 1.91 June 2004 47 WM8776 Product Preview 0.2 0 0.15 -20 Response (dB) Response (dB) 0.1 0.05 0 -0.05 -40 -0.1 -60 -0.15 -0.2 0 0.1 0.2 0.3 0.4 -80 0.5 Frequency (Fs) 0 Figure 28 DAC Digital Filter Ripple – 44.1, 48 and 96kHz 0.2 0.4 0.6 Frequency (Fs) 0.8 1 Figure 29 DAC Digital Filter Frequency Response – 192kHz 0.2 0 Response (dB) -0.2 -0.4 -0.6 -0.8 -1 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5 Figure 30 DAC Digital filter Ripple - 192kHz ADC FILTER RESPONSES 0.02 0 0.015 0.01 Response (dB) Response (dB) -20 -40 0.005 0 -0.005 -60 -0.01 -0.015 -80 -0.02 0 0.5 1 1.5 Frequency (Fs) 2 2.5 Figure 31 ADC Digital Filter Frequency Response w 3 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5 Figure 32 ADC Digital Filter Ripple PP Rev 1.91 June 2004 48 WM8776 Product Preview ADC HIGH PASS FILTER The WM8776 has a selectable digital highpass filter to remove DC offsets. The filter response is characterised by the following polynomial. H(z) = 1 - z-1 1 - 0.9995z-1 Response (dB) 0 -5 -10 -15 0 0.0005 0.001 Frequency (Fs) 0.0015 0.002 Figure 33 ADC Highpass Filter Response w PP Rev 1.91 June 2004 49 WM8776 Product Preview DIGITAL DE-EMPHASIS CHARACTERISTICS 0 1 0.5 -2 Response (dB) Response (dB) 0 -4 -6 -0.5 -1 -1.5 -2 -8 -2.5 -10 -3 0 2 4 6 8 10 Frequency (kHz) 12 14 16 Figure 34 De-Emphasis Frequency Response (32kHz) 0 2 4 6 8 10 Frequency (kHz) 12 14 16 Figure 35 De-Emphasis Error (32KHz) 0 0.4 0.3 -2 Response (dB) Response (dB) 0.2 -4 -6 0.1 0 -0.1 -0.2 -8 -0.3 -10 -0.4 0 5 10 Frequency (kHz) 15 20 Figure 36 De-Emphasis Frequency Response (44.1KHz) 0 5 10 Frequency (kHz) 15 20 Figure 37 De-Emphasis Error (44.1KHz) 0 1 0.8 -2 0.6 Response (dB) Response (dB) 0.4 -4 -6 0.2 0 -0.2 -0.4 -8 -0.6 -0.8 -10 -1 0 5 10 15 Frequency (kHz) 20 Figure 38 De-Emphasis Frequency Response (48kHz) w 0 5 10 15 Frequency (kHz) 20 Figure 39 De-Emphasis Error (48kHz) PP Rev 1.91 June 2004 50 WM8776 Product Preview APPLICATIONS INFORMATION EXTERNAL CIRCUIT CONFIGURATION In order to allow the use of 2V rms and larger inputs to the ADC and AUX inputs, a structure is used that uses external resistors to drop these larger voltages. This also increases the robustness of the circuit to external abuse such as ESD pulses. Figure 40 shows the ADC input multiplexor circuit with external components allowing 2Vrms inputs to be applied. 5K AINOPL 10uF 10K 10uF 10K 10uF 10K 10uF 10K 10uF 10K AINVGL AIN1L AIN2L AIN3L AIN4L AIN5L SOURCE SELECTOR INPUTS 5K AINOPR 10uF 10K 10uF 10K 10uF 10K 10uF 10K 10uF 10K AINVGR AIN1R AIN2R AIN3R AIN4R AIN5R Figure 40 ADC Input Multiplexor Configuration 10K MX[0] 10uF AUX input DACL/R 10K AUXL/R 10K BYPASSL/R 10K MX[1] MX[2] Figure 41 5.1 Channel Input Multiplexor Configuration w PP Rev 1.91 June 2004 51 WM8776 Product Preview RECOMMENDED EXTERNAL COMPONENTS Figure 42 External Component Diagram w PP Rev 1.91 June 2004 52 WM8776 Product Preview It is recommended that a low pass filter be applied to the output from the DAC for hi-fi applications. Typically a second order filter is suitable and provides sufficient attenuation of high frequency components (the unique low order, high bit count multi-bit sigma delta DAC structure used in WM8776 produces much less high frequency output noise). This filter is typically also used to provide the 2x gain needed to provide the standard 2Vrms output level from most consumer equipment. Figure 43 shows a suitable post DAC filter circuit, with 2x gain. Alternative inverting filter architectures might also be used with as good results. 4.7kΩ 4.7kΩ +VS _ 51Ω 10uF + 1.8kΩ 7.5KΩ + 1.0nF 680pF -VS 10kΩ Figure 43 Recommended Post DAC Filter Circuit To ensure that system ‘pop’ noise is kept to a minimum when power is applied or removed, a transistor clamp circuit arrangement may be added to the output connectors of the system. A recommended clamp circuit configuration is shown below. When the +VS power supply is applied, PNP transistor Q10 of the trigger circuit is held on until capacitor C49 is fully charged. With transistor Q10 held ‘on’, NPN transistors Q4 to Q5 of the clamp circuits are also switched on holding the system outputs near to GND. When capacitor C49 is fully charged transistors Q10 and Q4 to Q5 are switched off setting the outputs active. When the +VS power supply is removed, PNP transistor Q11 of the trigger circuit is switched on. In turn, transistors Q4 to Q5 of the clamp circuits are switched on holding the outputs of the evaluation board near to GND until the rest of the circuitry on the board has settled. Note: It is recommended that low Vcesat switching transistors should be used in this circuit to ensure that the clamp is applied before the rest of the circuitry has time to power down. Important: If a trigger circuit such as the one shown is to be used, it is important that the +VS supply drops quicker than any other supply to ensure that the outputs are clamped during the period when ‘pop’ noise may occur. w PP Rev 1.91 June 2004 53 WM8776 Product Preview PACKAGE DIMENSIONS FT: 48 PIN TQFP (7 x 7 x 1.0 mm) b DM004.C e 36 25 37 24 E1 48 E 13 1 12 Θ D1 c D L A A2 A1 -Cccc C Symbols A A1 A2 b c D D1 E E1 e L Θ ccc REF: SEATING PLANE Dimensions (mm) MIN NOM MAX --------1.20 0.05 ----0.15 0.95 1.00 1.05 0.17 0.22 0.27 0.09 ----0.20 9.00 BSC 7.00 BSC 9.00 BSC 7.00 BSC 0.50 BSC 0.45 0.60 0.75 o o o 0 3.5 7 Tolerances of Form and Position 0.08 JEDEC.95, MS-026 NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MS-026, VARIATION = ABC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. w PP Rev 1.91 June 2004 54 Product Preview WM8776 IMPORTANT NOTICE Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM’s standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical components in life support devices or systems without the express written approval of an officer of the company. Life support devices or systems are devices or systems that are intended for surgical implant into the body, or support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be reasonably expected to result in a significant injury to the user. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of WM covering or relating to any combination, machine, or process in which such products or services might be or are used. WM’s publication of information regarding any third party’s products or services does not constitute WM’s approval, license, warranty or endorsement thereof. Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use. Resale of WM’s products or services with statements different from or beyond the parameters stated by WM for that product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use. ADDRESS: Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: [email protected] w PP Rev 1.91 June 2004 55