ETC EUP3410

芯美电子
EUP3410
2A,25V,380KHz Step-Down Converter
DESCRIPTION
FEATURES
The EUP3410 is a current mode, step-down switching
regulator capable of driving 2A continuous load with
excellent line and load regulation. The EUP3410 can
operate with an input voltage range from 4.75V to 25V
and the output can be externally set from 1.2V to 16V
with a resistor divider.
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Fault condition protection includes cycle-by-cycle
current limiting and thermal shutdown. In shutdown
mode the regulator draws 16µA of supply current.
The EUP3410 requires a minimum number of readily
available standard external components.
2A Output Current
0.17Ω Internal DMOS Output Switch
Wide 4.75 to 25V Operating Input Range
Output Adjustable from 1.2V to 16V
Up to 95% Efficiency
16µA Shutdown Current
Fixed 380KHz Frequency
Thermal Shutdown and Overcurrent Protection
Input Under Voltage Lockout
Available in SOP-8 Package
RoHS Compliant and 100% Lead(Pb)-Free
APPLICATIONS
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PC Monitors
Distributed Power Systems
Networking Systems
Portable Electronics
Typical Application Circuit
Figure 1.
DS3410
Ver1.1
Feb. 2008
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EUP3410
Typical Application Circuit (continued)
Figure 2.
Block Diagram
Figure 3.
DS3410
Ver1.1
Feb. 2008
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EUP3410
Pin Configurations
Package Type
Pin
Configurations
SOP-8
Pin Description
PIN
PIN
1
BS
2
IN
3
SW
4
GND
5
FB
6
COMP
7
EN
8
N/C
DS3410
Ver1.1
Feb. 2008
DESCRIPTION
High-Side Gate Drive Boost Input. BS supplies the drive for the high-side n-channel
MOSFET switch. Connect a 10nF or greater capacitor from SW to BS to power the
high-side switch.
Power Input. IN supplies the power to the IC, as well as the step-down converter
switch. Drive IN with a 4.75V to 25V power source. Bypass IN to GND with a
suitably large capacitor to eliminate noise on the input to the IC. See Input
Capacitor.
Power Switching Output. SW is the switching node that supplies power to the output.
Connect the output LC filter from SW to the output load. Note that a capacitor is
required from SW to BS to power the high-side switch.
Ground.
Feedback Input. FB senses the output voltage to regulate that voltage. Drive FB with a
resistive voltage divider from the output voltage. The feedback threshold is 1.2V.
See Setting the Output Voltage.
Compensation Node. COMP is used to compensate the regulation control loop.
Connect a series RC network from COMP to GND to compensate the regulation
control loop. See Compensation.
Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high
to turn on the regulator, drive EN low to turn it off. For automatic startup, leave
EN unconnected.
No Connect
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EUP3410
Ordering Information
Order Number
Package Type
Marking
Operating Temperature range
EUP3410DIR1
SOP-8
xxxxx
P3410
-40°C to 85°C
EUP3410
□ □ □ □
Lead Free Code
1: Lead Free 0: Lead
Packing
R: Tape & Reel
Operating temperature range
I: Industry Standard
Package Type
D: SOP-8
DS3410
Ver1.1
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EUP3410
Absolute Maximum Ratings
„
„
„
„
„
„
„
„
„
Input Voltage (VIN)
----------------------------------------------------------- -0.3V to 26V
Switch Voltage (VSW) ------------------------------------------------------ -1V to VIN +0.3V
Boot Strap Voltage (VBS) ------------------------------------------------ VSW-0.3V to VSW +6V
All Other Pins -------------------------------------------------------------------- -0.3V to 6V
Operating Temperature Range ----------------------------------------------- -40°C to 85°C
Junction Temperature ------------------------------------------------------------------- 150°C
Storage Temperature
------------------------------------------------------- -65°C to 150°C
Lead Temp (Soldering, 10sec) ------------------------------------------------------260°C
Thermal Resistance θJA (SOP-8) ----------------------------------------------------- 90°C/W
Electrical Characteristics
Unless otherwise specified, VEN=5V, VIN=12V ,TA=25°C.
Parameter
Conditions
Feedback Voltage
Upper Switch On Resistance
Lower Switch On Resistance
Upper Switch Leakage
Current Limit
Oscillator Frequency
Short Circuit Frequency
Maximum Duty Cycle
Minimum Duty Cycle
Enable Threshold
Under Voltage Lockout Threshold Rising
Under Voltage Lockout Threshold Hysteresis
Shutdown Supply Current
Operating Supply Current
Thermal Shutdown
DS3410
Ver1.1
Feb. 2008
4.75V ≤ VIN ≤ 25V
EUP3410
Min
Typ
Max
1.162
1.200
0.17
6.8
VEN=0V, VSW=0V
5
2.4
320
VFB=0V
VFB=1V
VFB=1.5V
0.7
2
VEN=0V
VFB=1.4V
1.236
3
380
45
90
0.95
2.5
110
16
0.45
160
440
0
1.4
3
30
0.7
5
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Unit
V
Ω
Ω
µA
A
KHz
KHz
%
%
V
V
mV
µA
mA
°C
芯美电子
EUP3410
Typical Operating Characteristics
C1=390uF, C2=0.22uF, C6=0.22uF, C7=560uF, L=15uH, TA=25℃.
Efficiency versus IOUT and VOUT
95
5.0V
90
Efficiency(%)
3.3V
85
2.5V
80
VIN=10V
75
70
0
500
1000
1500
2000
Output Current(mA)
DS3410
Ver1.1
Feb. 2008
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EUP3410
Typical Operating Characteristics
C1=390uF, C2=0.22uF, C6=0.22uF, C7=560uF, L=15uH, 25℃.
DS3410
Ver1.1
Feb. 2008
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EUP3410
Functional Description
The EUP3410 is a current-mode step-down switch-mode
regulator. It regulates input voltages from 4.75V to 25V
down to an output voltage as low as 1.2V, and is able to
supply up to 2A of load current. The EUP3410 uses
current-mode control to regulate the output voltage. The
output voltage is measured at FB through a resistive
voltage divider and amplified through the internal error
amplifier. The output current of the transconductance
error amplifier is presented at COMP where a network
compensates the regulation control system. The voltage
at COMP is compared to the switch current measured
internally to control the output voltage. Slope
compensation provides stability in constant frequency
architectures by preventing subharmonic oscillations at
high duty cycles. It is accomplished internally by adding
a compensating ramp to the inductor current signal.
Normally, this results in a reduction of maximum
inductor peak current for high duty cycles.
The converter uses an internal n-channel MOSFET
switch to step down the input voltage to the regulated
output voltage. Since the MOSFET requires a gate
voltage greater than the input voltage, a boost capacitor
connected between SW and BS drives the gate. The
capacitor is internally charged while the switch is off. An
internal 6.8Ω switch from SW to GND is used to insure
that SW is pulled to GND when the switch is off to fully
charge the BS capacitor.
Application Information
Setting the Output Voltage
The output voltage is set using a resistive voltage divider
from the output voltage to FB (see Figure 2). The
voltage divider divides the output voltage down by the
ratio:
VFB = VOUT ∗ R 3 / (R 2 + R 3)
Thus the output voltage is :
R3 Can be as high as 100KΩ, but a typical value is 10
KΩ. Using that value, R2 is determined by :
R 2 ~ = 8.33 ∗ (VOUT − 1.2 )(KΩ )
For example, for a 3.3V output voltage, R3 is 10KΩ, and
R2 is 17.5KΩ.
Inductor
The inductor is required to supply constant current to the
output load while being driven by the switched input
voltage. A larger value inductor results in less ripple
current that in turn results in lower output ripple voltage.
However, the larger value inductor has a larger physical
size, higher series resistance, and/or lower saturation
current. Choose an inductor that does not saturate under
Ver1.1
Feb. 2008
L = (VOUT ) ∗ (VIN − VOUT ) / (VIN ∗ f ∗ ∆I )
Where VOUT is the output voltage, VIN is the input
voltage, f is the switching frequency, and ∆I is the
peak-to-peak inductor ripple current.
Input Capacitor
The input current to the step-down converter is
discontinuous, and therefore an input capacitor C1 is
required to supply the AC current to the step-down
converter while maintaining the DC input voltage. A low
ESR capacitor is required to keep the noise at the IC to a
minimum. Ceramic capacitors are preferred, but
tantalum or low-ESR electrolytic capacitors may also
suffice.
The input capacitor value should be greater than 10µF.
The capacitor can be electrolytic, tantalum or ceramic.
However since it absorbs the input switching current it
requires an adequate ripple current rating Its RMS
current rating should be greater than approximately 1/2
of the DC load current.
For insuring stable operation C2 should be placed as
close to the IC as possible. Alternately a smaller high
quality ceramic 0.1µF capacitor may be placed closer to
the IC and a larger capacitor placed further away. If
using this technique, it is recommended that the larger
capacitor be a tantalum or electrolytic type. All ceramic
capacitors should be placed close to the EUP3410.
Output Capacitor
VOUT = 1.2 ∗ (R 2 + R 3) / 3
DS3410
the worst-case load conditions. A good rule for
determining the inductance is to allow the peak-to- peak
ripple current in the inductor to be approximately 30%
of the maximum load current. Also, make sure that the
peak inductor current (the load current plus half the
peak-to-peak inductor ripple current) is below the 2.4A
minimum current limit.
The inductance value can be calculated by the equation:
The output capacitor is required to maintain the DC
output voltage. Low ESR capacitors are preferred to
keep the output voltage ripple low. The characteristics of
the output capacitor also affect the stability of the
regulation control system. Ceramic, tantalum, or low
ESR electrolytic capacitors are recommended. In the
case of ceramic capacitors, the impedance at the
switching frequency is dominated by the capacitance,
and so the output voltage ripple is mostly independent of
the ESR. The output voltage ripple is estimated to be:
VRIPPLE ~ = 1.4 ∗ VIN ∗ (f LC / f )∧ 2
Where VRIPPLE is the output ripple voltage, VIN is the
input voltage, fLC is the resonant frequency of the LC
filter, f is the switching frequency. In the case of
tanatalum or low ESR electrolytic capacitors, the ESR
dominates the impedance at the switching frequency, and
so the output ripple is calculated as:
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VRIPPLE ~ = ∆I ∗ R ESR
Where VRIPPLE is the output voltage ripple, ∆I is the
inductor ripple current, and RESR is the equivalent series
resistance of the output capacitors.
Output Rectifier Diode
The output rectifier diode supplies the current to the
inductor when the high-side switch is off. To reduce
losses due to the diode forward voltage and recovery
times, use a Schottky rectifier.
Compensation
The system stability is controlled through the COMP pin.
COMP is the output of the internal transconductance
error amplifier. A series capacitor-resistor combination
sets a pole-zero combination to control the
characteristics of the control system.
The DC loop gain is:
A VDC = (VFB / VOUT ) ∗ A VEA ∗ G CS ∗ R LOAD
approximately 1/10 of the switching frequency. In this
case, the switching frequency is 380KHz, therefore use a
crossover frequency, fC, of 40KHz. Lower crossover
frequencies result in slower response and worse transient
load recovery. Higher crossover frequencies can result in
instability.
Table 1. Compensation Values for Typical Output
Voltage /Capacitor Combinations
VOUT
C7
R1
C5
C4
2.5V
3.3V
5V
12V
22µF Ceramic
22µF Ceramic
22µF Ceramic
22µF Ceramic
560µF/6.3V
(30mΩ ESR)
560µF/6.3V
(30mΩ ESR)
470µF/10V
(30mΩ ESR)
220µF/25V
(30mΩ ESR)
7.5KΩ
10KΩ
10KΩ
10KΩ
2.2nF
1.5nF
2.2nF
5.6nF
None
None
None
None
10KΩ
30nF
None
10KΩ
39nF
None
10KΩ
47nF
None
10KΩ
56nF
None
2.5V
3.3V
5V
12V
Where:
Choosing the Compensation Components
VFB is the feedback threshold voltage, 1.2V VOUT is the
desired output regulation voltage AVEA is the
transconductance error amplifier voltage gain, 400 V/V.
GCS is the current sense gain, (roughly the output current
divided by the voltage at COMP), 2A/V
RLOAD is the load resistance (VOUT / IOUT where IOUT is
the output load current)
The system has 2 poles of importance, one is due to the
compensation capacitor (C5), and the other is due to the
output capacitor (C7). These are:
The values of the compensation components given in
Table 1 yield a stable control loop for the output voltage
and capacitor given. To optimize the compensation
components for conditions not listed in Table 1, use the
following procedure:
Choose the compensation resistor to set the desired
crossover frequency. Determine the value by the
following equation:
R1 = 2 π ∗ C 7 ∗ VOUT ∗ f c / (G EA ∗ G CS ∗ VFB )
Putting in the known constants and setting the crossover
frequency to the desired 40KHz:
f P1 = G EA / (2 π ∗ A VEA ∗ C5 )
Where P1 is the first pole, and GEA is the error amplifier
transconductance (660µA/V).
and
R1 ≈ 1.36 × 10 8 ∗ C 7 ∗ VOUT
The value of R1 is limited to 10KΩ to prevent output
overshoot at startup, therefore if the value calculated for
R1 is greater than 10KΩ, use 10KΩ.
f P 2 = 1 / (2 π ∗ R LOAD ∗ C 7 )
The system has one zero of importance, due to the
compensation capacitor (C5) and the compensation
resistor (R1). The zero is:
In this case, the actual crossover frequency is less than
the desired 40KHz, and is calculated by:
f C = R1 ∗ G EA ∗ G CS ∗ VFB / (2π ∗ C7 ∗ VOUT )
f Z1 = 1 / (2 π ∗ R1 ∗ C5 )
If a large value capacitor (C7) with relatively high
equivalent-series-resistance (ESR) is used, the zero due
to the capacitance and ESR of the output capacitor can
be compensated by a third pole set by R1 and C4. The
pole is:
f P3 = 1/ (2π ∗ R1 ∗ C4 )
The system crossover frequency (the frequency where
the loop gain drops to 1, or 0dB) is important. A good rule
of thumb is to set the crossover frequency to
DS3410 Ver1.1 Feb. 2008
Or:
(
)
f C ≈ 2.94 × 10 4 ∗ R1 / (C7 ∗ VOUT )
Choose the compensation capacitor to set the zero to ¼
of the crossover frequency.
Determine the value by the following equation:
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(
EUP3410
)
C5 = 0.22 ∗ C 7 ∗ V
/ R1
OUT
Determine if the second compensation capacitor, C4 is
required. It is required if the ESR zero of the output
capacitor happens at less than four times the crossover
frequency.
Or:
8π ∗ C 7 ∗ R ESR ∗ f C ≥ 1
Or:
(7.39 × 10
−5
)
∗ R1 ∗ R ESR / VOUT ≥ 1
Where RESR is the equivalent series resistance of the
output capacitor. If this is the case, add the second
compensation capacitor. Determine the value by the
equation :
C 4 = C 7 ∗ R ESR (max) / R1
Where RESR(max) is the maximum ESR of the output
capacitor.
DS3410
Ver1.1
Feb. 2008
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EUP3410
Packaging Information
SOP-8
SYMBOLS
MILLIMETERS
INCHES
MIN.
MAX.
MIN.
A
1.35
1.75
0.053
0.069
A1
0.10
0.25
0.004
0.010
D
E
4.90
5.80
E1
MAX.
0.193
6.20
0.228
3.90
0.244
0.153
L
0.40
1.27
0.016
0.050
b
0.31
0.51
0.012
0.020
e
DS3410 Ver1.1 Feb. 2008
1.27
0.050
11
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