Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. Freescale Semiconductor Advance Information Document Number: MC13892 Rev. 7.0, 4/2010 Power Management and User Interface IC 13892 The 13892 is a Power Management and User Interface component for Freescale’s i.MX51, i.MX37, i.MX35 and i.MX27 application processors, targeting netbooks, ebooks, mobile internet devices, smart phones, personal media players and personal navigation devices. POWER MANAGEMENT IC Features • Battery charger system for wall charging and USB charging • 10 bit ADC for monitoring battery and other inputs, plus a coulomb counter support module • 4 adjustable output buck converters for direct supply of the processor core and memory • 12 adjustable output LDOs with internal and external pass devices • Boost converter for supplying RGB LEDs • Serial backlight drivers for displays and keypad, plus RGB LED drivers • Power control logic with processor interface and event detection • Real time clock and crystal oscillator circuitry, with coin cell backup and support for external secure real time clock on a companion system processor IC • Touch screen interface • SPI/I2C bus interface for control and register access • Two package offerings in 7 x 7mm and 12 x 12mm VK SUFFIX 98ASA10820D 139-PIN 7X7MM BGA ORDERING INFORMATION Device Temperature Range (TA) See Device Variation Table on Page 2. Camera MMC NVR SSI IRDA TV Out DRAM BT (+FM) Line In/Out Camera Stereo Loudspeakers i.MX51 Apps Processor Audio IC Aud AP Mic Inputs Display Backlight USB Stereo headphones SPI/I2C UI Power Power UI Backlight Adapter MC13892 Power Mgmt & User Interface AP Charger LED Li Ion Battery Aud& Pwr Mgmt RGB Color Indicators Touch Screen Coin Cell Battery Light Sensor CALENDAR Thermistor VL SUFFIX 98ASA10849D 186-PIN 12X12MM BGA RTC Figure 1. 13892 Typical Operating Circuit * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2010. All rights reserved. Package Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. DEVICE VARIATIONS DEVICE VARIATIONS Device Variation Package MC13892VK* MC13892JVK PC13892AJVK** Pin Out Supplemental Functionality MC13892ER Figure 3 Standard Part MC13892AER Figure 3 MC13892ER Figure 4 MC13892AER Figure 4 7x7 PC13892BJVK** MC13892VL* MC13892JVL PC13892AJVL** Errata Doc # 12x12 PC13892BJVL** Global Reset Function Programmable Global Reset Function Standard Part Global Reset Function Programmable Global Reset Function * ITC Effected Product ** PC Contact Local Sales Office for Availability 13892 2 Analog Integrated Circuit Device Data Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. INTERNAL BLOCK DIAGRAM Charger Interface and Control: 4 bit DAC, Clamp, Protection, Trickle Generation Battery Interface & Protection GNDLED LEDR LEDG LEDB GNDBL LEDKP LEDAD LEDMD GNDCHRG CHRGSE1B CHRGLED CHRGRAW CHRGCTRL1 CHRGCTRL2 CHRGISNS BPSNS BP BATTFET BATT BATTISNS INTERNAL BLOCK DIAGRAM Tri-Color LED Drive Backlight LED Drive PWR Gate Drive & Chg Pump PWGTDRV1 PWGTDRV2 LICELL, UID, Die Temp, GPO4 GNDADC ADIN5 Voltage / Current Sensing & Translation SW1 1050 mA Buck ADIN6 ADIN7 TSX1 10 Bit GP ADC MUX SW2 800 mA Buck A/D Result TSX2 TSY1 TSY2 A/D Control Touch Screen Interface Trigger Handling TSREF Die Temp & Thermal Warning Detection ADTRIG SW3 800 mA Buck To Interrupt Section SW4 800 mA Buck BATTISNSCC BATT CFP Coulomb CCOUT Counter SPIVCC MC13892 IC Shift Register CS CLK SPI Interface + Muxed I2C Optional Interface MOSI MISO GNDSPI SPI SW2IN SW2OUT GNDSW2 SW2FB O/P Drive SW3IN SW3OUT GNDSW3 SW3FB O/P Drive SW4IN SW4OUT GNDSW4 SW4FB DVS1 DVS2 SPI Control MC13892 VBUS/ID Detectors VUSB2 Pass FET VAUDIO Pass FET VIOHI Pass FET VPLL Pass FET VDIG Pass FET OTG 5V SPI VUSB Regulator Pass FET To Trimmed Circuits Trim-In-Package Control Logic PLL VDIG VGEN2 VGEN2DRV VGEN2 VGEN3 GNDREG1 GNDREG2 GNDREG3 GPO4 GPO Control GPO3 CLK32K VINGEN3DRV Pass FET Best of Supply VSRTC STANDBYSEC RESETB RESETBMCU INT WDI PWRON3 STANDBY PWRON2 PUMS1 PUMS2 MODE BP 32 KHz Buffers VCAM LICELL Enables & Control VSRTC Interrupt Inputs Core Control Logic, Timers, & Interrupts GNDCTRL XTAL2 XTAL1 GNDRTC GNDSUB8 GNDSUB9 GNDSUB7 GNDSUB6 GNDSUB4 GNDSUB5 VINDIG VGEN1DRV VGEN1 VGEN3 CLK32KMCU SPI Result Registers 32 KHz Crystal Osc GNDSUB3 VINPLL VPLL VGEN1 Switchers RTC + Calibration 32 KHz Internal Osc PWRON1 LCELL Li Cell Charger GNDSUB2 Control Logic Monitor Timer Switch GNDSUB1 VINIOHI VIOHI VSDDRV VSD GPO1 GPO2 Startup Sequencer Decode Trim? PUMS BP VINAUDIO VAUDIO VSD VUSB LICELL VINUSB2 VUSB2 VINCAMDRV VCAM VINUSB VVIDEODRV VVIDEO VVIDEO Connector Interface UID Bi-directional Pin SWBSTIN SWBSTOUT SWBSTFB GNDSWBST Shift Register Reference Generation UVBUS O/P Drive SWBST 300 mA Boost Input Pin To Enables & Control Registers VCORE VBUSEN O/P Drive Package Pin Legend Output Pin REFCORE GNDCORE SW1IN SW1OUT GNDSW1 SW1FB DVS CONTROL To SPI CFM VCOREDIG O/P Drive Figure 2. 13892 Simplified Internal Block Diagram 13892 Analog Integrated Circuit Device Data Freescale Semiconductor 3 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. PIN CONNECTIONS PIN CONNECTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 A VUSB2 VUSB2 VINUSB2 SWBSTIN GNDSWBST GNDBL NC MODE VCORE BATT CHRGRAW CHRGCTRL2 CHRGCTRL2 B VUSB2 GPO1 DVS2 SWBSTOUT LEDB LEDKP LEDR GNDCORE VCOREDIG BP CHRGCTRL1 BATTISNSCC CHRGCTRL2 Regulators C VINPLL VSDDRV CHRGISNS BATTISNS Switchers D VUSB VSD SWBSTFB LEDMD DVS1 REFCORE CHRGSE1B LICELL BATTFET BPSNS PWRON1 E UVBUS VPLL LEDG GNDLED UID PUMS2 GNDCHRG CHRGLED PWRON2 ADTRIG INT GNDSW1 Control Logic F GNDSW3 VBUSEN SW3FB LEDAD GNDSUB GNDSUB GNDSUB GPO3 GPO2 RESETBMCU RESETB SW1OUT Charger G SW3OUT VINUSB SW4FB GNDREG2 GNDSUB GNDSUB GNDSUB PUMS1 WDI GPO4 SW1IN H SW3IN MISO GNDSPI GNDREG3 GNDSUB GNDSUB GNDSUB GNDCTRL SW1FB STANDBYSEC SW2IN J SW4IN MOSI CLK32KMCU STANDBY GNDADC GNDREG1 PWRON3 TSX1 SW2FB TSX2 SW2OUT Backlights RTC Grounds USB ADC K SW4OUT SPIVCC PWGTDRV1 CLK32K VCAM CFP CFM ADIN5 ADIN6 VVIDEODRV GNDSW2 SPI/I2C L GNDSW4 CS TSY2 VVIDEO No Connect M VGEN3 CLK VGEN2 VSRTC GNDRTC VINCAMDRV PWGTDRV2 VDIG VINDIG VGEN1DRV ADIN7 TSY1 TSREF N VGEN3 VGEN3 VINGEN3DRV VGEN2DRV XTAL2 XTAL1 VINAUDIO VAUDIO VIOHI VINIOHI VGEN1 TSREF TSREF Figure 3. 13892VK Pin Connections 13892 4 Analog Integrated Circuit Device Data Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. PIN CONNECTIONS 1 A 2 3 4 5 6 7 8 9 10 11 12 13 VUSB2 VINUSB2 SWBSTOUT SWBSTIN GNDSUB NC MODE VCORE BATT CHRGRAW CHRGCTRL2 CHRGISNS 14 Regulators B VSDDRV GPO1 GNDSUB GNDSUB LEDR UID DVS1 REFCORE GNDCORE CHRGSE1B BP GNDCHRG BATTISNSCC BATTISNS Switchers C VSD DVS2 SWBSTFB LEDB LEDG LEDKP LEDAD PUMS2 VCOREDIG LICELL BATTFET BPSNS GPO3 PUMS1 Backlights D VUSB VPLL GNDSUB GNDSUB GNDSWBST GNDLED LEDMD GNDBL CHRGCTRL1 CHRGLED PWRON1 PWRON3 ADTRIG GPO4 Control Logic E UVBUS GNDREG2 VINPLL GNDSUB GNDSUB GNDSUB GNDSUB GNDSUB GNDSUB GNDSUB PWRON2 GPO2 INT RESETBMCU Charger F SW3OUT VBUSEN VINUSB GNDSUB GNDSUB GNDSUB GNDSUB GNDSUB GNDSUB GNDSUB GNDCTRL WDI RESETB SW1OUT RTC G GNDSW3 GNDSW3 SW3FB GNDSUB GNDSUB GNDSUB GNDSUB GNDSUB GNDSUB GNDSUB GNDSUB SW1FB GNDSW1 GNDSW1 Grounds H SW3IN SW3IN GNDSUB GNDSUB GNDSUB GNDSUB GNDSUB GNDSUB GNDSUB GNDSUB SW1IN SW1IN USB J SW4IN SW4IN SW4FB GNDSUB GNDSUB GNDSUB GNDSUB GNDSUB GNDSUB SW2FB SW2IN SW2IN ADC K GNDSW4 GNDSW4 SPIVCC GNDSUB GNDSUB GNDSUB GNDSUB GNDSUB GNDSUB VVIDEODRV GNDSW2 GNDSW2 SPI/I2C L SW4OUT CS GNDSPI GNDSUB GNDSUB GNDSUB VCAM VINAUDIO VDIG GNDSUB TSY2 STANDBYSEC VVIDEO SW2OUT No Connect M CLK VINGEN3DRV CLK32KMCU CLK32K VSRTC STANDBY VINCAMDRV CFP CFM VGEN1DRV VGEN1 TSX1 TSX2 TSY1 N VGEN3 MOSI VGEN2 GNDREG3 XTAL2 XTAL1 VAUDIO PWGTDRV2 VIOHI VINIOHI GNDADC ADIN5 ADIN7 TSREF MISO PWGTDRV1 VGEN2DRV GNDSUB GNDRTC GNDSUB GNDSUB GNDSUB GNDSUB VINDIG GNDREG1 ADIN6 P Figure 4. 13892VL Pin Connections 13892 Analog Integrated Circuit Device Data Freescale Semiconductor 5 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. PIN CONNECTIONS Table 1. 13892 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 33. Pin Number Pin Number on on the the 13982VL 13982VK 12x12mm 7x7mm Pin Name Rating Pin Function (V) Formal Name Definition A1, A2, B1 A2 VUSB2 3.6 Output USB 2 Supply Output regulator for USB PHY A3 A3 VINUSB2 5.5 Power USB 2 Supply Input A4 A5 SWBSTIN 5.5 Power Switcher Boost Power Input A5 D5 GNDSWBST - Ground Switcher Boost Ground A6 D8 GNDBL - Ground Backlight LED Ground A7 A7 NC - - No Connect A8 A8 MODE 9.0 Input Mode Configuration USB LBP mode, normal mode, test mode selection & anti-fuse bias A9 A9 VCORE 3.6 Output Core Supply Regulated supply output for the IC analog core circuitry A10 A10 BATT 5.5 Input Battery Connection Input regulator VUSB2 Switcher BST input Ground for switcher BST Ground for serial LED drive Do NOT connect 1. Battery positive terminal 2. Battery current sensing point 2 3. Battery supply voltage sense A11 A11 CHRGRAW 20 I/O Charger Input 1. Charger input 2. Output to battery supplied accesories A12, A13, B13 A12 CHRGCTRL2 5.5 Output Charger Control 2 Driver output for charger path FETs M2 B2 B2 GPO1 3.6 Output General Purpose Output 1 General purpose output 1 B3 C2 DVS2 3.6 Input Dynamic Voltage Scaling Control 2 Switcher 2 DVS input pin B4 A4 SWBSTOUT 7.5 Power B5 C4 LEDB 7.5 Output LED Driver General purpose LED driver output Blue B6 C6 LEDKP 28 Output LED Driver Keypad lighting LED driver output B7 B5 LEDR 7.5 Output LED Driver General purpose LED driver output Red B8 B9 GNDCORE - Ground Core Ground B9 C9 VCOREDIG 1.5 Output Digital Core Supply B10 B11 BP 5.5 Power Battery Plus Switcher Boost Output Switcher BST BP supply Ground for the IC core circuitry Regulated supply output for the IC digital core circuitry 1. Application supply point 2. Input supply to the IC core circuitry 3. Application supply voltage sense B11 D9 CHRGCTRL1 20 Output Charger Control 1 Driver output for charger path FETs M1 B12 B13 BATTISNSCC 4.8 Input Battery Current Sense C1 E3 VINPLL 5.5 Power PLL Supply Input Input regulator processor PLL C2 B1 VSDDRV 5.5 Output VSD Driver Drive output regulated SD card C12 A13 CHRGISNS 4.8 Input Charger Current Sense Charge current sensing point 1 C13 B14 BATTISNS 4.8 Input Battery Current Sense Battery current sensing point 1 D1 D1 VUSB 3.6 Output USB Supply Accumulated current counter current sensing point USB transceiver regulator output 13892 6 Analog Integrated Circuit Device Data Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. PIN CONNECTIONS Table 1. 13892 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 33. Pin Number Pin Number on on the the 13982VL 13982VK 12x12mm 7x7mm Pin Name Rating Pin Function (V) Formal Name Definition D2 C1 VSD 3.6 Output SD Card Supply Output regulator SD card D4 C3 SWBSTFB 3.6 Input Switcher Boost Feedback Switcher BST feedback D5 D7 LEDMD 28 Output LED Driver D6 B7 DVS1 3.6 Input Dynamic Voltage Scaling Control 1 Switcher 1DVS input pin D7 B8 REFCORE 3.6 Output Core Reference Main bandgap reference D8 B10 CHRGSE1B 3.6 Input Charger Select Charger forced SE1 detection input D9 C10 LICELL 3.6 I/O Coin Cell Connection Main display backlight LED driver output 1. Coin cell supply input 2. Coin cell charger output D10 C11 BATTFET 4.8 Output Battery FET Connection D12 C12 BPSNS 4.8 Input Battery Plus Sense Driver output for battery path FET M3 1. BP sense point 2. Charge current sensing point 2 D13 D11 PWRON1 3.6 Input Power On 1 Power on/off button connection 1 E1 E1 UVBUS 20 I/O USB Bus 1. USB transceiver cable interface 2. VBUS & OTG supply output E2 D2 VPLL 3.6 Output Voltage Supply for PLL Output regulator processor PLL E4 C5 LEDG 7.5 Output PWM Driver for Green LED E5 D6 GNDLED - Ground LED Ground E6 B6 UID 5.5 Input USB ID E7 C8 PUMS2 3.6 Input Power Up Mode Select 2 Power up mode supply setting 2 E8 B12 GNDCHRG - Ground Charger Ground Ground for charger interface E9 D10 CHRGLED 20 Output Charger LED Trickle LED driver output 1 E10 E11 PWRON2 3.6 Input Power On 2 Power on/off button connection 2 E11 D13 ADTRIG 3.6 Input ADC Trigger ADC trigger input E12 E13 INT 3.6 Output Interrupt Signal Interrupt to processor E13 G13, G14 GNDSW1 - Ground Switcher 1 Ground Ground for switcher 1 F1 G1, G2 GNDSW3 - Ground Switcher 3 Ground Ground for switcher 3 F2 F2 VBUSEN 3.6 Input VBUS Enable F4 G3 SW3FB 3.6 Input Switcher 3 Feedback Switcher 3 feedback F5 C7 LEDAD 28 Output Auxiliary Display LED Auxiliary display backlight LED driver output F6 A6, B3, B4, D3, D4, E4, E5, E6 GNDSUB1 - Ground Ground 1 Non critical signal ground and thermal heat sink F7 E7, E8, E9, E10, F4, F5, F6 GNDSUB2 - Ground Ground 2 Non critical signal ground and thermal heat sink General purpose LED driver output Green Ground for LED drivers USB OTG transceiver cable ID External VBUS enable pin for OTG supply 13892 Analog Integrated Circuit Device Data Freescale Semiconductor 7 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. PIN CONNECTIONS Table 1. 13892 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 33. Pin Number Pin Number on on the the 13982VL 13982VK 12x12mm 7x7mm Pin Name Rating Pin Function (V) Formal Name Definition Non critical signal ground and thermal heat sink F8 F7, F8, F9, F10, G4, G5, G6, G7, G8 GNDSUB3 - Ground Ground 3 F9 C13 GPO3 - Output General Purpose Output 3 General purpose output 3 F10 E12 GPO2 3.6 Output General Purpose Output 2 General purpose output 2 F11 E14 RESETBMCU 3.6 Output MCU Reset Reset output for processor F12 F13 RESETB 3.6 Output Peripheral Reset Reset output for peripherals F13 F14 SW1OUT 5.5 Output Switcher 1 Output Switcher 1 output G1 F1 SW3OUT 5.5 Output Switcher 3 Output Switcher 3 output G2 F3 VINUSB 7.5 Input VUSB Supply Input G4 J3 SW4FB 3.6 Input Switcher 4 Feedback Switcher 4 feedback G5 E2 GNDREG2 - Ground Regulator 2 Ground Ground for regulators 2 G6 G9, G10, G11, H3, H5, H6, H7, H8 GNDSUB4 - Ground Ground 4 Non critical signal ground and thermal heat sink G7 H9, H10, H12, J5, J6, J7 GNDSUB5 - Ground Ground 5 Non critical signal ground and thermal heat sink G8 J8, J9, J10, K4, K5, K6, K7 GNDSUB6 - Ground Ground 6 Non critical signal ground and thermal heat sink G9 C14 PUMS1 3.6 Input Power Up Mode Select 1 Power up mode supply setting 1 G10 F12 WDI 3.6 Input Watchdog Input Watchdog input G12 D14 GPO4 3.6 Output General Purpose Output 4 General purpose output 4 G13 H13, H14 SW1IN 5.5 Input Switcher 1 Input Input voltage for switcher 1 H1 H1, H2 SW3IN 5.5 Power Switcher 3 Input Switcher 3 input H2 P2 MISO 3.6 I/O Master In Slave Out Primary SPI read output H4 L3 GNDSPI - Ground SPI Ground Ground for SPI interface H5 N4 GNDREG3 - Ground Regulator 3 Ground Ground for regulators 3 H6 K8, K10, L4, L5, L6, L10 GNDSUB7 - Ground Ground 7 Non critical signal ground and thermal heat sink H7 P5, P7, P8, P9, P10 GNDSUB8 - Ground Ground 8 Non critical signal ground and thermal heat sink GNDSUB9 - Ground Ground 9 Non critical signal ground and thermal heat sink H8 Input option for UVUSB; tie to SWBST at top level H9 F11 GNDCTRL - Ground Logic Control Ground Ground for control logic H10 G12 SW1FB 3.6 Input Switcher 1 Feedback Switcher 1 feedback 13892 8 Analog Integrated Circuit Device Data Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. PIN CONNECTIONS Table 1. 13892 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 33. Pin Number Pin Number on on the the 13982VL 13982VK 12x12mm 7x7mm Pin Name Rating Pin Function (V) Formal Name Definition H12 L12 STANDBYSEC 3.6 Input Secondary Standby Signal Standby input signal from peripherals H13 J13, J14 SW2IN 5.5 Input Switcher 2 Input Input voltage for Switcher 2 J1 J1, J2 SW4IN 5.5 Power Switcher 4 Input Switcher 4 input J2 N2 MOSI 3.6 Input Master Out Slave In J4 M3 CLK32KMCU 3.6 Output 32 kHz Clock for MCU J5 M6 STANDBY 3.6 Input Standby Signal J6 N11 GNDADC - Ground ADC Ground J7 P12 GNDREG1 - Ground Regulator 1 Ground J8 D12 PWRON3 3.6 Input Power On 3 J9 M12 TSX1 3.6 Input Touch Screen Interface X1 J10 J12 SW2FB 3.6 Input Switcher 2 Feedback J12 M13 TSX2 3.6 Input Touch Screen Interface X2 J13 L14 SW2OUT 5.5 Output Switcher 2 Output Switcher 2 output K1 L1 SW4OUT 5.5 Output Switcher 4 Output Switcher 4 output K2 K3 SPIVCC 3.6 Input K4 P3 PWGTDRV1 4.8 Output Power Gate Driver 1 K5 M4 CLK32K 3.6 Output 32 kHz Clock K6 L7 VCAM 3.6 Output Camera Supply K7 M8 CFP 4.8 Passive Current Filter Positive K8 M9 CFM 4.8 Passive Current Filter Negative Accumulated current filter cap minus terminal K9 N12 ADIN5 4.8 Input ADC Channel 5 Input ADC generic input channel 5 K10 P13 ADIN6 4.8 Input ADC Channel 6 Input ADC generic input channel 6 K12 K12 VVIDEODRV 5.5 Output VVIDEO Driver K13 K13, K14 GNDSW2 - Ground Switcher 2 Ground Ground for switcher 2 L1 K1, K2 GNDSW4 - Ground Switcher 4 Ground Ground for switcher 4 L2 L2 CS 3.6 Input Chip Select L12 L11 TSY2 3.6 Input Touch Screen Interface Y2 Touch screen interface Y2 L13 L13 VVIDEO 3.6 Output Video Supply Output regulator TV DAC M1, N1, N2 N1 VGEN3 3.6 Output General Purpose Regulator 3 Output GEN3 regulator M2 M1 CLK 3.6 Input Clock Primary SPI clock input M3 N3 VGEN2 3.6 Output General Purpose Regulator 2 Output GEN2 regulator Primary SPI write input 32 kHz clock output for processor Standby input signal from processor Ground for A to D circuitry Ground for regulators 1 Power on/off button connection 3 Touch screen interface X1 Switcher 2 feedback Touch screen interface X2 Supply Voltage for SPI Supply for SPI bus and audio bus Power gate driver 1 32 kHz clock output for peripherals Output regulator camera Accumulated current filter cap plus terminal Drive output regulator VVIDEO Primary SPI select input 13892 Analog Integrated Circuit Device Data Freescale Semiconductor 9 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. PIN CONNECTIONS Table 1. 13892 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 33. Pin Number Pin Number on on the the 13982VL 13982VK 12x12mm 7x7mm Pin Name Rating Pin Function (V) Formal Name M4 M5 VSRTC 3.6 Output SRTC Supply M5 P6 GNDRTC - Ground Real Time Clock Ground M6 M7 VINCAMDRV 5.5 I/O Camera Regulator Supply Input and Driver Output Definition Output regulator for SRTC module on processor Ground for the RTC block 1. Input regulator camera using internal PMOS FET. 2. Drive output regulator for camera voltage using external PNP device. M7 N8 PWGTDRV2 4.8 Output Power Gate Driver 2 Power gate driver 2 M8 L9 VDIG 3.6 Output Digital Supply M9 P11 VINDIG 5.5 Input VDIG Supply Input M10 M10 VGEN1DRV 5.5 Output VGEN1 Driver M11 N13 ADIN7 4.8 Input ADC Channel 7 Input M12 M14 TSY1 3.6 Input Touch Screen Interface Y1 Touch screen interface Y1 M13, N12, N13 N14 TSREF 3.6 Output Touch Screen Reference Touch screen reference N3 M2 VINGEN3DRV 5.5 Power/ Output VGEN3 Supply Input and Driver Output Output regulator digital Input regulator digital Drive output GEN1 regulator ADC generic input channel 7, group 1 1. Input VGEN3 regulator 2. Drive VGEN3 output regulator N4 P4 VGEN2DRV 5.5 Output VGEN2 Driver Drive output GEN2 regulator N5 N5 XTAL2 2.5 Input Crystal Connection 2 32.768 kHz oscillator crystal connection 2 N6 N6 XTAL1 2.5 Input Crystal Connection 1 32.768 kHz oscillator crystal connection 1 N7 L8 VINAUDIO 5.5 Power Audio Supply Input N8 N7 VAUDIO 3.6 Output Audio Supply N9 N9 VIOHI 3.6 Output High Voltage IO Supply Output regulator high voltage IO, efuse N10 N10 VINIOHI 5.5 Input High Voltage IO Supply Input Input regulator high voltage IO N11 M11 VGEN1 3.6 Output General Purpose Regulator 1 Input GEN1 regulator Input regulator VAUDIO Output regulator for audio 13892 10 Analog Integrated Circuit Device Data Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings Symbol Value Unit Charger and USB Input Voltage(1) VCHRGR -0.3 to 20 V MODE pin Voltage VMODE -0.3 to 9.0 V VLEDMD, VLEDAD, VLEDKP -0.3 to 28 V VBATT -0.3 to 4.8 V VLICELL -0.3 to 3.6 V ELECTRICAL RATINGS Main/Aux/Keypad Current Sink Voltage Battery Voltage Coin Cell Voltage ESD Voltage(1) Human Body Model - HBM with Mode pin VESD excluded(4) V ±1500 ±250 Charge Device Model - CDM THERMAL RATINGS Ambient Operating Temperature Range TA -30 to +85 °C Operating Junction Temperature Range TJ -30 to +125 °C TSTG -65 to +150 °C TPPRT Note 3 °C Storage Temperature Range THERMAL RESISTANCE Peak Package Reflow Temperature During Reflow(2), (3) Notes 1. USB Input Voltage applies to UVBUS pin only 1. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω) and the Charge Device Model (CDM), Robotic (CZAP = 4.0pF). 2. 3. 4. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. Mode Pin is not ESD protected. Table 3. Dissipation Ratings Rating Parameter Condition Symbol VK Package VL Package Unit Junction to Ambient Natural Convection Single layer board (1s) RθJA 104 65 °C/W Junction to Ambient Natural Convection Four layer board (2s2p) RθJMA 54 42 °C/W Junction to Ambient (@200 ft/min) Single layer board (1s) RθJMA 88 55 °C/W Junction to Ambient (@200 ft/min) Four layer board (2s2p) RθJMA 49 38 °C/W Junction to Board RθJB 32 28 °C/W Junction to Case RθJC 29 22 °C/W θJT 7 5 °C/W Junction to Package Top Natural Convection 13892 Analog Integrated Circuit Device Data Freescale Semiconductor 11 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics Characteristics noted under conditions - 30°C ≤ TA ≤ 85°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted. Current in RTC Mode is from LICELL = 2.5 V, in all other modes from BP = 3.6 V. External loads are not included. Characteristic Symbol Min Typ Max Unit CURRENT CONSUMPTION RTC Mode µA All blocks disabled, no main battery attached, coin cell is attached to LICELL(7) IRTC RTC OFF Mode (All blocks disabled, main battery attached)(7) 3.00 6.00 - 10 30 IOFF 13892 core and RTC module Power Cut Mode (All blocks disabled, no main battery attached, coin cell is attached and valid)(7) - µA IPCUT 13892 core and RTC module µA - 3.0 6.0 ISTBY - 230 295 ION - 459 1500 1.2 - 4.65 1.8 - 2.0 0 - 0.2 VCLKHI SPIVCC-0.2 - SPIVCC VCLKMCUHI VSRTC-0.2 - VSRTC ON Standby mode - Low power mode µA (5) 4 buck switches in low power mode, 3 regulators ON Mode - Typical use case 4 buck switches in PWMPS mode, 5 Regulators(6) µA 32KHZ CRYSTAL OSCILLATOR Operating Voltage VXTAL Oscillator and RTC Block from BP Coincell Disconnect Threshold VLCD At LICELL Output Low CLK32K, CLK32KMCU V V VCLKLO Output sink 100 µA V Output High CLK32K Output source 100 µA CLK32KMCU Output source 100 µA V VSRTC GENERAL Operating Input Voltage Range VINMIN to VINMAX Valid Coin Cell range V VLICELL 1.8 - 3.6 BP UVDET - 4.65 Operating Current Load Range ILMIN to ILMAX ISRTC 0 - 50 µA Bypass Capacitor Value CSRTC - 1.0 - µF Or valid BP Notes 5. VPLL, VIOHI, VGEN2 6. VPLL, VIOHI, VGEN2, VAUDIO, VVIDEO 7. Valid at 25°C only. 13892 12 Analog Integrated Circuit Device Data Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics Characteristics noted under conditions - 30°C ≤ TA ≤ 85°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted. Current in RTC Mode is from LICELL = 2.5 V, in all other modes from BP = 3.6 V. External loads are not included. Characteristic Symbol Min Typ Max Unit VSRTC ACTIVE MODE – DC Output Voltage VOUT VSRTC VINMIN < VIN < VINMAX, ILMIN < IL < ILMAX V 1.15 1.20 1.25 - 0.8 1.0 0 - 0.3*SPIVCC 0.7*SPIVCC - SPIVCC+0.3 0 - 0.2 VOMISOHI VOINTHI SPIVCC-0.2 - SPIVCC SPIVCC 1.75 - 3.1 3.0 2.8 UVDET - 4.65 4.65 4.65 Switcher 1 0.6 - 1.375 Switchers 2, 3, and 4 0.6 - 1.850 Active Mode Quiescent Current IRTCQS VINMIN < VIN < VINMAX, IL = 0 µA CLK AND MISO Input Low CS, MOSI, CLK VINCSLO VINMOSILO VINCLKLO Input High CS, MOSI, CLK VINCSHI VINMOSIHI VINCLKHI Output Low MISO, INT Output sink 100 µA VOMISOLO VOINTLO V V Output High MISO, INT Output source 100 µA SPIVCC Operating Range V V V BUCK CONVERTERS Operating Input Voltage VSWIN PWM operation, 0 < IL < IMAX PFM operation, 0 < IL < IMAX Extended PWM or PFM operation(8) Output Voltage Range V VSW1 V Output Accuracy mV PWM mode including ripple, load regulation, and transients (9) VSWLOPP Nom-50 Nom Nom+50 PFM Mode, including ripple, load regulation, and transients VSWLIPPI Nom-50 Nom Nom+50 ISW1 800 Maximum Continuous Load Current, IMAX, VINMIN<BP<4.65 V SW1 in PWM mode (SWILIMB=0, no max current limit) SW1 in PWM Mode (SWILIMB=1, no max current limit)(10) - mA - 1050 SW2, SW3, SW4 in PWM mode (SWILIMB=0, no max current limit) ISW2,3,4 800 - - SW2, SW3, SW4 in PWM mode (SWILIMB=1, no max current limit) ISW2,3,4 800 - - ISW1, 2, 3, 4 - 50 - SW1, SW2, SW3, SW4 in PFM mode Notes 8. In the extended operating range the performance may be degraded 9. Transient loading for load steps of ILmax/2 10. In this mode, current limit protection is disabled for SW1 - SW4 by setting SWILIMB=1. Therefore, the load on SW1 should not exceed 1.05 A and current on SW2-4 should not exceed 800mA. Application needs to provide current limit protection circuitry either in battery or as pre regulated supply to BP. 13892 Analog Integrated Circuit Device Data Freescale Semiconductor 13 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics Characteristics noted under conditions - 30°C ≤ TA ≤ 85°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted. Current in RTC Mode is from LICELL = 2.5 V, in all other modes from BP = 3.6 V. External loads are not included. Characteristic Symbol Min Typ Max Unit BUCK CONVERTERS (CONTINUED) Effective Quiescent Current Consumption ISWQS PWM Mode, IL=0 mA; device not switching µA - 50 15 100 30 - 50 - PFM, 0.9 V, 1.0 mA - 75 - PFM, 01.8 V, 1.0 mA - 85 - PWM Pulse Skipping, 1.25 V, 50 mA - 78 - PWM Pulse Skipping, 1.8 V, 50 mA - 82 - PWM, 1.25 V, 500 mA - 78 - PWM, 1.8 V, 500 mA - 82 - PFM Mode, IL=0 mA; device not switching Automatic Mode Change Threshold, Switchover between PFM and PWM modes AMCTH mA Efficiency % External Components, Used as a condition for all other parameters LSW234 -20% 2.2 +20% µH (11) LSW1 -30% 1.5 +30% µH Inductor Resistance RWSW - - 0.16 Ω COSW234 -35% 10 +35% µF COSW1 -35% 2x22 +35% µF ESRSW 5.0 - 50 mΩ 1.0 4.7 - µF Nom-5% 5.0 Nom+5% - - 120 - - 0.5 - - 50 Inductor for SW2, SW3, SW4(11) Inductor for SW1 Bypass Capacitor for SW2, SW3, SW4(12) Bypass Capacitor for SW1(13) Bypass Capacitor ESR Input Capacitor(14) SWBST Average Output Voltage(15) 3.0 V < VIN < 4.65 (1), 0 < IL < ILMAX VBST (16) Output Ripple VBSTPP 3.0 V < VIN < 4.65, 0 < IL < ILMAX, Excluding reverse recovery of Schottky diode Average Load Regulation 3.0 V < VIN < 4.65 V, IL = ILMAX mVpp VBSTLOR VIN = 3.6 V, 0 < IL < ILMAX Average Line Regulation V mV/mA VBSTLIR mV Notes 11. Preferred device TDK VLS252012 series at 2.5x2.0 mm footprint and 1.2 mm max height 12. Preferably 0603 style 6.3 V rated X5R/X7R type at 35% total make tolerance, temperature spread and DC bias derating such as TDK C1608X5R0J106M 13. Preferably 0805 style 6.3 V rated X5R/X7R type at 35% total make tolerance, temperature spread and DC bias derating such as TDK C2012X5R0J226M 14. Preferably 0603 style 6.3 V rated X5R/X7R type at 35% total make tolerance, temperature spread and DC bias derating such as TDK C1608X5R0J475 15. Output voltage when configured to supply VBUS in OTG mode can be as high as 5.75 V 16. Vin is the low side of the inductor that is connected to BP. 13892 14 Analog Integrated Circuit Device Data Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics Characteristics noted under conditions - 30°C ≤ TA ≤ 85°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted. Current in RTC Mode is from LICELL = 2.5 V, in all other modes from BP = 3.6 V. External loads are not included. Characteristic Symbol Min Typ Max 300 - - Unit SWBST (CONTINUED) Maximum Continuous Load Current ILMAX IBST 3.0 V < VIN < 4.65, VOUT = 5.0 V Peak Current Limit BSTPK At SWBSTIN; VIN = 3.6 V Start-up Overshoot Bias Current Consumption mA 800 - 1500 - - 500 VBSTOS IL = 0 mA Efficiency, IL = ILMAX mA mV SWBSTEFF - 80 - % IBSTBIAS - 390 1200 µA LBST External Components - Used as a condition for all other parameters Inductor(17) -20% 2.2 +20% µH R_WBST - - 0.2 Ω ILSAT 1.0 - - A Bypass Capacitor(18) COBST -60% 10 +35% µF Bypass Capacitor ESR at resonance ESRBST mΩ Inductor Resistance Inductor saturation current at 30% loss in inductance value 1.0 - 10 CBSTD 1.0 4.7 - µF Diode current capability IBSTDPK 850 - - mAdc Diode current capability IBSTDPK 1500 - - mApk IBSTIK - 1.0 5.0 µA VINVIDEO VNOM+0.25 - 4.65 V IVIDEO 0 -- 350 mA 1.1 2.2 - 20 - 100 VNOM – 3% VNOM VNOM + 3% - - 0.20 Input Capacitor NMOS Off Leakage, SWBSTIN = 4.5 V, SWBSTEN = 0 VVIDEO Operating Input Voltage Range VINMIN to VINMAX Operating Current Load Range ILMIN to ILMAX (Not exceeding PNP max power) Minimum Bypass Capacitor Value COVIDEO Used as a condition for all other parameters Bypass Capacitor ESR µF ESRVIDEO 10 kHz -1.0 MHz mΩ VVIDEO ACTIVE MODE DC Output Voltage VOUT ΔVVIDEO Vinmin < VIN < VINMAX, ILMIN < IL < ILMAX Load Regulation VVIDEOLOPP 1.0 mA < IL < ILMAX, For any VINMIN < VIN < VINMAX Line Regulation VINMIN < VIN < VINMAX, IL = 0 mV - 5.0 8.0 ILMAX+20% - - - 30 45 IVIDEOSHT VINMIN < VIN < VINMAX, Short-circuit VOUT to GND Active Mode Quiescent Current mV/mA VVIDEOLIPP VINMIN < VIN < VINMAX, For any ILMIN < IL < ILMAX Short-circuit Protection Threshold V mA IVIDEOQS µA Notes 17. Preferred device TDK VLS252012 series at 2.5x2.0 mm footprint and 1.2 mm max height 18. Applications of SWBST should take into account impact of tolerance and voltage derating on the bypass capacitor at the output level. 13892 Analog Integrated Circuit Device Data Freescale Semiconductor 15 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics Characteristics noted under conditions - 30°C ≤ TA ≤ 85°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted. Current in RTC Mode is from LICELL = 2.5 V, in all other modes from BP = 3.6 V. External loads are not included. Characteristic Symbol Min Typ Max VNOM -3% VNOM VNOM +3% 0.0 - 3.0 Unit VVIDEO LOW POWER MODE DC - VVIDEOMODE=1 Output Voltage VOUT ΔVVIDEOLO VINMIN < VIN < VINMAX, ILMINLP < IL < ILMAXLP Current Load Range ILminlp to ILMAXLP Low Power Mode Quiescent Current IVIDEOLO V IVIDEOQSLO VINMIN < VIN < VINMAX, IL = 0 mA µA - 8.0 10.5 VAUDIO Operating Input Voltage Range VINMIN to VINMAX VAUDIO VNOM+0.25 - 4.65 V Operating Current Load Range ILMIN to ILMAX IAUDIO 0 - 150 mA COAUDIO 0.65 2.2 - µF 0 - 0.1 Minimum Bypass Capacitor Value Bypass Capacitor ESR ESRAUDIO 10 kHz -1.0 MHz Ω VAUDIO ACTIVE MODE DC Output Voltage VOUT (VINMIN < VIN < VINMAX, ILMIN < IL < ILmax) VAUDIO VNOM – 3% VNOM VNOM + 3% V Load Regulation (1.0 mA < IL < ILMAX, For any VINMIN < VIN < VINMAX) VAUDIOLOR - - 0.25 mV/mA Line Regulation VAUDIOLIR VINMIN < VIN < VINMAX, For any ILMIN < IL < ILMAX Short-circuit Protection Threshold - 5.0 8.0 ILMAX+20% - - - 8.0 10.5 IAUDIOSHT VINMIN < VIN < VINMAX, Short circuit VOUT to GND Active Mode Quiescent Current mV mA IAUDIOQS VINMIN < VIN < VINMAX, IL = 0 µA VPLL AND VDIG Operating Input Voltage Range VINMIN to VINMAX VINPLL, VINDIG VDIG, VPLL all settings, BP biased V UVDET - 4.65 VPLL, VDIG [1:0] = 00,01 1.75 SW4 =1.8 4.65 VPLL, VDIG [1:0] = 10, 11, External Switcher 2.15 2.2 4.65 0 - 50 0.65 2.2 - 0 - 0.1 VNOM – 0.05 VNOM VNOM + 0.05 - - 0.35 Operating Current Load Range ILMIN to ILMAX Minimum Bypass Capacitor Value IPLL, IDIG COPLL, CODIG Used as a condition for all other parameters Bypass Capacitor ESR 10 kHz -1.0 MHz ESRPLL, ESRDIG mA µF Ω VPLL AND VDIG ACTIVE MODE DC Output Voltage VOUT VPLL, VDIG VINMIN < VIN < VINMAX, ILMIN < IL < ILMAX Load Regulation 1.0 mA < IL < ILMAX for any VINMIN < VIN < VINMAX VPLLLOR, VDIGLOR V mV/mA 13892 16 Analog Integrated Circuit Device Data Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics Characteristics noted under conditions - 30°C ≤ TA ≤ 85°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted. Current in RTC Mode is from LICELL = 2.5 V, in all other modes from BP = 3.6 V. External loads are not included. Characteristic Symbol Min Typ Max Unit VPLL AND VDIG ACTIVE MODE DC (CONTINUED) Line Regulation VPLLLIR, VDIGLIR - 5.0 8.0 IPLLLQS, IDIGLQS - 8.0 10.5 VNOM+0.25 - 4.65 IIOHI 0 - 100 mA COIOHI 0.65 2.2 - µF 0 - 100 VNOM -3% VNOM VNOM +3% - - 0.35 - 5.0 8.0 - 8.0 10.5 VNOM +0.25 - 4.65 Internal pass FET 0 - 65 External PNP 0 - 250 VINMIN < VIN < VINMAX for any ILMIN < IL < ILMAX Active Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 mV µA VIOHI Operating Input Voltage Range VINMIN to VINMAX VINIOHI VNOM = 2.775 V Operating Current Load Range ILMIN to ILMAX Minimum Bypass Capacitor Value Bypass Capacitor ESR V ESRIOHI 10 kHz -1.0 MHz mΩ VIOHI ACTIVE MODE DC Output Voltage VOUT - (VNOM = 2.775) VIOH VINMIN < VIN < VINMAX, ILMIN < IL < ILMAX Load Regulation VIOHLOR 1.0 mA < IL < ILMAX, for any VINMIN < VIN < VINMAX Line Regulation mV/mA VIOHLIR VINMIN < VIN < VINMAX, for any ILMIN < IL < ILMAX Active Mode Quiescent Current V mV IIOHQS VINMIN < VIN < VINMAX, IL = 0 µA VCAM Operating Input Voltage Range VINMIN to VINMAX Operating Current Load Range ILMIN to ILMAX Minimum Bypass Capacitor Value VINCAM ICAM mA COCAM µF Internal pass device 0.65 2.2 - External PNP (not exceeding PNP max power) 1.1 2.2 - Bypass Capacitor ESR ESRCAM 10 kHz -1.0 MHz V mΩ 20 - 100 VNOM – 3% VNOM VNOM + 3% - - 0.25 - 5.0 8.0 VCAM ACTIVE MODE DC Output Voltage VOUT (VNOM = 2.775) VCAM VINMIN < VIN < VINMAX, ILMIN < IL < ILMAX Load Regulation VCAMLOR 1.0 mA < IL < ILMAX, for any VINMIN < VIN < VINMAX Line Regulation VINMIN < VIN < VINMAX, for any ILMIN < IL < ILMAX V mV/mA VCAMLIR mV VCAM ACTIVE MODE DC (CONTINUED) 13892 Analog Integrated Circuit Device Data Freescale Semiconductor 17 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics Characteristics noted under conditions - 30°C ≤ TA ≤ 85°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted. Current in RTC Mode is from LICELL = 2.5 V, in all other modes from BP = 3.6 V. External loads are not included. Characteristic Min Typ Max ILMAX+20% - - VINMIN < VIN < VINMAX, IL = 0, Internal PMOS configuration - 25 35 VINMIN < VIN < VINMAX, IL = 0, External PNP configuration - 30 45 Short-circuit Protection Threshold Symbol ICAMSHT VINMIN < VIN < VINMAX, Short-circuit VOUT to GND Active Mode Quiescent Current Unit mA ICAMQS µA VCAM LOW POWER MODE DC Output Voltage VOUT VCAMLO VINMIN < VIN < VINMAX, ILMINLP < IL < ILMAXLP Current Load Range ILMINLP to ILMAXLP Low Power Mode Quiescent Current ICAMLO V VNOM -3% VNOM VNOM +3% 0 - 3.0 ICAMQSLO VINMIN < VIN < VINMAX, IL = 0 mA µA - 8.0 10.5 VNOM+0.25 - 4.65 VSD[2:0]=010 to 111, Extended Operation UVDET - 4.65 VSD[2:0]=000, 001 [000] BP Supplied UVDET - 4.65 2.15 2.20 4.65 VSD Operating Input Voltage Range VINMIN to VINMAX VINSD VSD[2:0]=010 to 111 VSD[2:0]=000 External Switcher Supplied Operating Current Load Range ILMIN to ILMAX ISD Not exceeding PNP max power Minimum Bypass Capacitor Value Bypass Capacitor ESR V COSD mA 0 - 250 1.1 2.2 - 20 - 100 VNOM – 3% VNOM VNOM + 3% - - 0.25 - 5.0 8.0 ILMAX+20% - - - 30 45 VNOM -3% VNOM VNOM +3% 0 - 3.0 - 8.0 10.5 ESRSD 10 kHz -1.0 MHz µF mΩ VSD ACTIVE MODE DC Output Voltage VOUT VSD VINMIN < VIN < VINMAX, ILMIN < IL < ILMAX Load Regulation VSDLOR 1.0 mA < IL < ILMAX, for any VINMIN < VIN < VINMAX Line Regulation mV ISDSHT VINMIN < VIN < VINMAX, Short-circuit VOUT to GND Active Mode Quiescent Current mV/mA VSDLIR VINMIN < VIN < VINMAX, for any ILMIN < IL < ILMAX Short-circuit Protection Threshold V mA ISDQS VINMIN < VIN < VINMAX, IL = 0 µA VSD LOW POWER MODE DC - VSDMODE=1 Output Voltage VOUT VSDLO VINMIN < VIN < VINMAX, ILMINLP < IL < ILMAXLP Current Load Range ILMINLP to ILMAXLP Low Power Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 ISDLO V ISDQSLO mA µA VUSB GENERAL 13892 18 Analog Integrated Circuit Device Data Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics Characteristics noted under conditions - 30°C ≤ TA ≤ 85°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted. Current in RTC Mode is from LICELL = 2.5 V, in all other modes from BP = 3.6 V. External loads are not included. Characteristic Operating Input Voltage Range VINMIN to VINMAX Symbol Supplied by SWBST Bypass Capacitor Value Range Bypass Capacitor ESR Typ Max VINUSB Supplied by VBUS Operating Current Load Range ILMIN to ILMAX Min Unit V 4.4 5.0 5.25 - - 5.75 IUSB 0 - 100 mA COUSB 0.65 2.2 - µF 0 - 0.1 VNOM – 4% 3.3 VNOM + 4% ESRUSB 10 kHz -1.0 MHz Ω VUSB ACTIVE MODE DC Output Voltage VOUT VUSB VINMIN < VIN < VINMAX, ILMIN < IL < ILMAX Load Regulation VUSBLOR 0 < IL < ILMAX from DM/DP for any VINMIN < VIN < VINMAX Line Regulation mV/mA - - 1.0 - - 20 ILMAX+20% - - VNOM +0.25 - 4.65 UVDET - 4.65 0 - 50 0.65 2.2 - 0 - 0.1 VNOM -3% VNOM VNOM + 3% - - 0.35 - 5.0 8.0 VUSBLIR VINMIN < VIN < VINMAX, for any ILMIN < IL < ILMAX Short-circuit Protection Threshold V mV VUSBSHT VINMIN < VIN < VINMAX, Short-circuit VOUT to GND mA VUSB2 Operating Input Voltage Range VINMIN to VINMAX VINUSB2 Extended operation Operating Current Load Range ILMIN to ILMAX Minimum Bypass Capacitor Value IUSB2 COUSB2 Used as a condition for all other parameters Bypass Capacitor ESR mA µF ESRUSB2 10 kHz -1.0 MHz V Ω VUSB2 ACTIVE MODE DC Output Voltage VOUT VUSB2 VINMIN < VIN < VINMAX, ILMIN < IL < ILMAX Load Regulation VUSB2LOR 1.0 mA < IL < ILMAX, for any VINMIN < VIN < VINMAX Line Regulation VINMIN < VIN < VINMAX, IL = 0 mV/mA VUSB2LIR VINMIN < VIN < VINMAX, for any ILMIN < IL < ILMAX Active Mode Quiescent Current V mV IUSB2QS µA - 8.0 13 13892 Analog Integrated Circuit Device Data Freescale Semiconductor 19 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics Characteristics noted under conditions - 30°C ≤ TA ≤ 85°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted. Current in RTC Mode is from LICELL = 2.5 V, in all other modes from BP = 3.6 V. External loads are not included. Characteristic Symbol Min Typ Max 4.75 5.0 5.25 100 Unit UVBUS Operating Input Voltage Range VINMIN to VINMAX VINUVBUS VINUSB supplied by SWBST Operating Current Load Range ILMIN to ILMAX V IUVBUS 0 - Minimum Bypass Capacitor Value COUVBUS (19) (19) Bypass Capacitor ESR VINUVBUS (19) (19) (20) 4.4 5.0 5.25 UVDET < VNOM +0.25 - 4.65 2.15 2.2 4.65 0 - 200 UVDET - 4.65 1.1 2.2 +35% 20 - 100 VGEN1=00, 01, VINMIN < VIN < VINMAX ILMIN < IL < ILMAX VNOM – 0.05 VNOM VNOM + 0.05 VGEN1=10, 11, VINMIN < VIN < VINMAX ILMIN < IL < ILMAX VNOM – 3% VNOM VNOM + 3% 10 kHz -1.0 MHz 6.5 (20) mA µF Ω UVBUS ACTIVE MODE DC Output Voltage Vout VUVBUS VINMIN < VIN < VINMAX, ILMIN < IL < ILMAX V VGEN1 Operating Input Voltage Range VINMIN to VINMAX VINGEN1 All settings, BP biased VGEN1=00,01, External switcher supplied Operating Current Load Range ILMIN to ILMAX (not exceeding PNP max power) IGEN1 Extended input voltage range (BP biased, performance may be out of specification for output levels VGEN1[1:0]=10 to 11) Minimum Bypass Capacitor Value Bypass Capacitor ESR V mA V COGEN1 ESRGEN1 10 kHz -1.0 MHz µF mΩ VGEN1 ACTIVE MODE DC Output Voltage VOUT Load Regulation VGEN1 VGEN1LOR 1.0 mA < IL < ILMAX, for any VINMIN < VIN < VINMAX Line Regulation VINMIN < VIN < VINMAX, IL = 0 - - 0.25 - 5.0 8.0 ILMAX+20% - - mV VGEN1SHT VINMIN < VIN < VINMAX, Short-circuit VOUT to GND Active Mode Quiescent Current mV/mA VGEN1LIR VINMIN < VIN < VINMAX, for any ILMIN < IL < ILMAX Short-circuit Protection Threshold V mA IGEN1QS µA - 20 45 Notes 19. Filtering is shared with CHRGRAW (shorted at board level). 2.2 µF is typically included at the CHRGRAW pin. 20. 6.5 µF is the maximum allowable capacitance on VBUS including all tolerances of filtering capacitance on VBUS and CHRGRAW (which are shorted at the board level). VGEN1 LOW POWER MODE DC - VGEN1MODE=1 13892 20 Analog Integrated Circuit Device Data Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics Characteristics noted under conditions - 30°C ≤ TA ≤ 85°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted. Current in RTC Mode is from LICELL = 2.5 V, in all other modes from BP = 3.6 V. External loads are not included. Characteristic Output Voltage VOUT - VINMIN < VIN < VINMAX, ILMINLP < IL < ILMAXLP Symbol Min Typ Max VGEN1LO V VGEN1=00, 01 VNOM – 0.05 VNOM VNOM + 0.05 VGEN1=10, 11 VNOM -3% VNOM VNOM +3% 0 - 3.0 Current Load Range ILMINLP to ILMAXLP Low Power Mode Quiescent Current IGEN1LO IGEN1QSLO VINMIN < VIN < VINMAX, IL = 0 Unit mA µA - 8.0 10.5 UVDET< VNOM+0.25 - 4.65 2.15 2.2 4.65 IGEN2 0 - 350 COGEN2 1.1 2.2 +35% VGEN2 GENERAL Operating Input Voltage Range VINMIN to VINMAX VINGEN2 All settings, BP biased VGEN2=000,001, External switcher supplied Operating Current Load Range ILMIN to ILMAX (Not exceeding PNP max power) Minimum Bypass Capacitor Value Bypass Capacitor ESR V ESRGEN2 10 kHz -1.0 MHz mA µF mΩ 20 - 100 VGEN2 ACTIVE MODE DC Output Voltage VOUT VGEN2 VGEN2=000, 001, 010, VINMIN < VIN < VINMAX ILMIN < IL < ILMAX VGEN2=011, 100, 101, 110, 111, VINMIN < VIN < VINMAX ILMIN < IL < ILMAX Load Regulation VNOM +0.05 VNOM VNOM +3% - - 0.20 mV/mA mV - 5.0 8.0 ILMAX+20% - - - 35 45 VGEN2SHT VINMIN < VIN < VINMAX, Short-circuit VOUT to GND Active Mode Quiescent Current VNOM VNOM -3% VGEN2LIR VINMIN < VIN < VINMAX, For any ILMIN < IL < ILMAX Short-circuit Protection Threshold VNOM -0.05 VGEN2LOR 1.0 mA < IL < ILMAX, For any VINMIN < VIN < VINMAX Line Regulation V mA IGEN2QS VINMIN < VIN < VINMAX, IL = 0 uA VGEN2 LOW POWER MODE DC - VGEN2MODE=1 Output Voltage VOUT - VINMIN < VIN < VINMAX, ILMINLP < IL < ILMAXLP VGEN2LO V VGEN2=000 to 010 VNOM -0.05 VNOM VNOM +0.05 VGEN2=011 to 111 VNOM -3% VNOM VNOM +3% 0 - 3.0 Current Load Range ILMINLP to ILMAXLP Low Power Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 IGEN2LO IGEN2QSLO mA µA - 8.0 10.5 13892 Analog Integrated Circuit Device Data Freescale Semiconductor 21 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics Characteristics noted under conditions - 30°C ≤ TA ≤ 85°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted. Current in RTC Mode is from LICELL = 2.5 V, in all other modes from BP = 3.6 V. External loads are not included. Characteristic Symbol Min Typ Max VNOM+0.2 - 4.65 UVDET - 4.65 Unit VGEN3 GENERAL Operating Input Voltage Range VINMIN to VINMAX VINGEN3 VGEN3CONFIG, VGEN3=01, 11 VGEN3CONFIG, VGEN3=00, 10 Operating Current Load Range ILMIN to ILMAX V IGEN3 mA Internal Pass FET 0 - 50 External PNP (Not exceeding PNP max power) 0 - 200 Internal pass device 0.65 2.2 - External pass device 1.1 2.2 - 20 - 100 VNOM – 3% VNOM VNOM + 3% Minimum Bypass Capacitor Value Bypass Capacitor ESR COGEN3 µF ESRGEN3 10 kHz -1.0 MHz mΩ VGEN3 ACTIVE MODE DC Output Voltage VOUT VGEN3 VGEN2=000, 001, 010, VINMIN < VIN < VINMAX ILMIN < IL < ILMAX Load Regulation VGEN3LOR 1.0 mA < IL < ILMAX, For any VINMIN < VIN < VINMAX Line Regulation - - 0.40 - 5.0 9.0 ILMAX+20% - - mV VGEN3SHT VINMIN < VIN < VINMAX, Short circuit VOUT to GND Active Mode Quiescent Current mV/mA VGEN3SHT VINMIN < VIN < VINMAX, For any ILMIN < IL < ILMAX Short-circuit Protection Threshold V mA IGEN3QS µA VINMIN < VIN < VINMAX, IL = 0, Internal PMOS configuration - 25 35 VINMIN < VIN < VINMAX, IL=0, external PNP configuration - 30 45 VNOM -3% VNOM VNOM +3% 0 1.0 3.0 - 8.0 10.5 BATTMIN - 17 Charge current 1.0 mA to 100 mA 1.5 - 1.5 Charge current 100 mA and above -3.0 - 1.5 VGEN3 LOW POWER MODE DC Output Voltage VOUT - (Accuracy) VGEN3LO VINMIN < VIN < VINMAX, ILMINLP < IL < ILMAXLP Current Load Range ILMINLP to ILMAXLP Low Power Mode Quiescent Current IGEN3LO V IGEN3QSLO VINMIN < VIN < VINMAX, IL = 0 mA µA CHARGE PATH REGULATOR Input Operating Voltage - CHRGRAW Output Voltage Spread - VCHRG[2:0]=011, 1XX VINCHRG BPSP V % 13892 22 Analog Integrated Circuit Device Data Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics Characteristics noted under conditions - 30°C ≤ TA ≤ 85°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted. Current in RTC Mode is from LICELL = 2.5 V, in all other modes from BP = 3.6 V. External loads are not included. Characteristic Symbol Min Typ Max Unit CHARGE PATH REGULATOR (CONTINUED) Current Limit Tolerance (21) ΔILIM ICHRG[3:0]=0001 68 80 92 mA ICHRG[3:0]=0100 360 400 440 mA ICHRG[3:0]=0110 500 560 620 mA - - 15 % BPOS-START - - 2.0 % CINCHRG CBP LC 10 - 2.2 - 47 3 µF Thermal Warning Lower Threshold TWL - 100 - °C Thermal Warning Higher Threshold TWH - 120 - °C Thermal Warning Hysteresis TWHYS - 3.0 - °C Thermal Protection Threshold TPT - 140 - °C Absolute Accuracy - All current settings - - 15 % Matching - At 400 mV, 21 mA - - 3 % Leakage - LEDxDC[5:0]=000000 - - 1 µA Absolute Accuracy - All current settings - - 15 % Matching - At 400 mV, 21 mA - - 10 % Leakage - LEDxDC[5:0]=000000 - - 1 µA 4.4 5.0 5.25 V All other settings Start-up Overshoot - Unloaded Configuration Input Capacitance - CHRGRAW(22) Load Capacitor - BPSNS(22) Cable length µF m THERMAL BACKLIGHT LED DRIVERS SIGNALING LED DRIVERS ACTIVE MODE DC Output Voltage VOUT - (VNOM = 2.775), VINMIN < VIN < VINMAX, ILMIN < IL < ILMAX ADC Conversion Current 1 mA Converter Core Input Range Single ended voltage readings Differential readings (23) Maximum Input Voltage Channels ADIN5, ADIN6 and ADIN7 V 0 2.4 -1.2 1.2 BP V Integral Nonlinearity 3 LSB Differential Nonlinearity 1 LSB Notes 21. Excludes spread and tolerance due to board and 100 mOhm sense resistor tolerances. 22. An additional derating of 35% is allowed. 23. ADIN5, 6 and 7 inputs must not exceed BP voltage. 13892 Analog Integrated Circuit Device Data Freescale Semiconductor 23 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics Characteristics noted under conditions - 30°C ≤ TA ≤ 85°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted. Current in RTC Mode is from LICELL = 2.5 V, in all other modes from BP = 3.6 V. External loads are not included. Characteristic Symbol Min Typ Max Unit ADC (CONTINUED) Zero Scale Error (Offset) Before auto calibration After auto calibration 10 1 Full Scale Error (Gain) Before auto calibration After auto calibration 25 5 Drift Over-temperature - Including scaling 1 Source Impedance No bypass capacitor at input Bypass capacitor at input 10 nF 5 30 LSB LSB LSB KΩ TOUCH SCREEN Plate Maximum Voltage X, Y(24) VCORE V Ω Plate Resistance X, Y 100 1000 Resistance Between Plates Settling Time - Contact 180 1200 Ω 3 5.5 µs 20 mA +3% V Position measurement TOUCH SCREEN IN STAND ALONE MODE(25) Quiescent Current - Active Mode 20 Max Load Current - Active Mode Output Voltage - 0<IL<20 mA PSRR - IL=15 mA Bypass Capacitor ESR Bypass Capacitance -3% 1.20 µA 50 dB 0 0.65 2.2 0.1 Ω +35% µF Notes 24. TS[xy][1,2] inputs must not exceed BP or VCORE 25. All characteristics in this table are applicable only for non touch screen operation. This applies to Touch Screen in Standalone Mode and below. 13892 24 Analog Integrated Circuit Device Data Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions 3.1 V ≤ BATT ≤ 4.8 V, --30 ≤ TA ≤ 85°C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit 32KHZ CRYSTAL OSCILLATOR RTC oscillator start-up time tRTCST Upon application of power CLK32K Rise and Fall Time - CL=50 pF Sec - - 1.0 tCLK32KET ns CLK32KDRV[1:0]=00 (default) - 22 - CLK32KDRV[1:0]=01 - 11 - CLK32KDRV[1:0]=10 - High Z - CLK32KDRV[1:0]=11 - 44 - - 22 - 45 - 55 SPIDRV [1:0]=00 (default) - 11 - SPIDRV [1:0]=01 - 6.0 - SPIDRV [1:0]=10 - High Z - SPIDRV [1:0]=11 - 22 - - - 500 - - 2.0 Maximum transient Amplitude - - 300 mV Time to settle 80% of transient - - 500 µs Maximum transient Amplitude - - 300 mV Time to settle 80% of transient - - 20 µs CLK32KMCU Rise and Fall Time tCLK32KMCUET CL=12 pF CLK32K and CLK32KMCU Output Duty Cycle Crystal on XTAL1, XTAL2 pins tCLK32KDC, tCLK32KMCUDC ns % CLK AND MISO MISO Rise and Fall Time, CL=50 pF, SPIVCC=1.8 V tMISOET ns BUCK CONVERTERS Turn-on Time, Enable to 90% of end value, IL=0 tONPWM µs SWBST Turn-on Time tONBST Enable to 90% of VOUT, IL=0 Transient Load Response, IL from 1.0 mA to 100 mA in 1.0 µs steps Transient Load Response, IL from 100 mA to 1.0 mA ms ATMAX ATMAX VVIDEO ACTIVE MODE - AC PSRR - IL = 75% of ILMAX, 20 Hz to 20 kHz VVIDEOPSSR dB VIN = VINMIN + 100 mV 35 40 - VIN = VNOM + 1.0 V 50 60 - 100 Hz – 1.0 kHz - -114 - >1.0 kHz – 10 kHz - -124 - >10 kHz – 1.0 MHz - -129 - - - 1.0 Max Output Noise - VIN = VINMIN, IL = 75% of ILMAX Turn-on Time Enable to 90% of end value, VIN = VINMIN, VINMAX, IL = 0 VVIDEOON dBV/√Hz VVIDEOtON ms 13892 Analog Integrated Circuit Device Data Freescale Semiconductor 25 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions 3.1 V ≤ BATT ≤ 4.8 V, --30 ≤ TA ≤ 85°C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit VVIDEO ACTIVE MODE - AC (CONTINUED) Turn-off Time VVIDEOtOFF Disable to 10% of initial value, VIN = VINMIN, VINMAX, IL = 0 Transient Load Response - 10 - 1.0 2.0 - 5.0 8.0 % VVIDEOTLIR IL = 75% of ILMAX Mode Transition Time 0.1 VVIDEOTLOR VIN = VINMIN, VINMAX Transient Line Response ms mV VVIDEOtMOD From low power to active, VIN = VINMIN, VINMAX, IL =ILMAXLP µs - - 100 - 1.0 2.0 VIN = VINMIN + 100 mV, > UVDET 35 40 - VIN = VNOM + 1.0 V, > UVDET 50 60 - 100 Hz – 1.0 kHz - -114 - >1.0 kHz – 10 kHz - -124 - >10 kHz – 1.0 MHz - -129 - - - 1.0 Mode Transition Response VVIDEOMTR From low power to active and from active to low power, VIN = VINMIN, VINMAX, IL = ILMAXLP % VAUDIO PSRR - IL = 75% of ILMAX, 20 Hz to 20 kHz Max Output Noise - VIN = VINMIN, IL = 0.75*ILmax Turn-on Time VAUDIOPSSR VAUDIOON dBV/√Hz VAUDIOtON Enable to 90% of end value, VIN = VINMIN, VINMAX, IL = 0 Turn-off Time dB ms VAUDIOtOFF Disable to 10% of initial value, VIN = VINMIN, VINMAX, IL = 0 ms 0.1 - 10 - 1.0 2.0 - 5.0 8.0 VIN = UVDET 35 40 - VIN = VNOM + 1.0 V, > UVDET 50 60 - Transient Load Response - See Transient Response Waveforms on page 49, VIN = VINMIN, VINMAX VAUDIOTLOR Transient Line Response - See Transient Response Waveforms on page 49 VAUDIOTLIR IL = 75% of ILMAX % mV VPLL AND VDIG ACTIVE MODE - AC PSRR - IL = 75% of ILMAX, 20 Hz to 20 kHz Output Noise - VIN = VINMIN, IL = 0.75*ILMAX VPLLPSSR dB VPLLON 100 Hz – 1.0 kHz - 20 - dB/dec >1 kHz – 1.0 MHz - 2.5 - µV/√Hz - - 100 Turn-on Time VPLLtON Enable to 90% of end value, VIN = VINMIN, VINMAX, IL = 0 Turn-off Time Disable to 10% of initial value, VIN = VINMIN, VINMAX, IL = 0 µs VPLLtOFF ms 0.1 - 10 13892 26 Analog Integrated Circuit Device Data Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions 3.1 V ≤ BATT ≤ 4.8 V, --30 ≤ TA ≤ 85°C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max VPLLTLOR, VDIGTLOR - 50 70 VPLLTLIR, VDIGTLIR - 5.0 8.0 Unit VPLL AND VDIG ACTIVE MODE - AC (CONTINUED) Transient Load Response - See Transient Response Waveforms on page 49 VIN = VINMIN, VINMAX Transient Line Response - See Transient Response Waveforms on page 49 IL = 75% of ILMAX mV mV VIOHI ACTIVE MODE - AC PSRR - IL = 75% of ILMAX, 20 Hz to 20 kHz VIOHIPSSR dB VIN = VINMIN + 100 mV, > UVDET 35 40 - VIN = VNOM + 1.0 V, > UVDET 50 60 - - 20 - dB/dec - 1.0 - µV/√Hz Output Noise - VIN = VINMIN, IL = 0.75*ILMAX VIOHION 100 Hz – 1.0 kHz >1.0 kHz – 1.0 MHz Turn-on Time VIOHItON Enable to 90% of end value, VIN = VINMIN, VINMAX, IL = 0 Turn-off Time - 1.0 0.1 - 10 - 1.0 2.0 ms VIOHITLOR VIN = VINMIN, VINMAX Transient Line Response - See Transient Response Waveforms on page 49 VIOHItOFF Disable to 10% of initial value, VIN = VINMIN, VINMAX, IL = 0 Transient Load Response - See Transient Response Waveforms on page 49 ms % VIOHITLIR IL = 75% of ILMAX mV - 5.0 8.0 - - 10 - 1.0 2.0 VIN = VINMIN + 100 mV 35 40 - VIN = VNOM + 1.0 V 50 60 - Mode Transition Time - See Transient Response Waveforms on page 49 VIOHIMTR From low power to active, VIN = VINMIN, VINMAX, IL = ILMAXLP Mode Transition Response µs VIOHIMTR From low power to active and from active to low power, VIN = VINMIN, VINMAX, IL = ILMAXLP % VCAM ACTIVE MODE - AC PSRR - IL = 75% of ILMAX, 20 Hz to 20 kHz Output Noise - VIN = VINMIN, IL = 0.75*ILMAX VCAMPSSR dB VCAMON 100 Hz – 1.0 kHz - 20 - dB/dec >1.0 kHz – 1.0 MHz - 1.0 - µV/√Hz Turn-on Time (Enable to 90% of end value, VIN = VINMIN, VINMAX, IL = 0) VCAMtON - - 1.0 ms Turn-off Time (Disable to 10% of initial value, VIN = VINMIN, VINMAX, IL = 0) VCAMtOFF 0.1 - 10 ms Transient Load Response - See Transient Response Waveforms on page 49 VCAMLOR VCAM=01, 10, 11 - 1.0 2.0 % VCAM=00 - 50 70 mV - 5.0 8.0 VIN = VINMIN, VINMAX Transient Line Response - See Transient Response Waveforms on page 49 IL = 75% of ILMAX VCAMLIR mV 13892 Analog Integrated Circuit Device Data Freescale Semiconductor 27 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions 3.1 V ≤ BATT ≤ 4.8 V, --30 ≤ TA ≤ 85°C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit VCAM ACTIVE MODE - AC (CONTINUED) Mode Transition Time - See Transient Response Waveforms on page 49 VCAMtMOD From low power to active, VIN = VINMIN, VINMAX, IL = ILMAXLP Mode Transition Response µs - - 100 - 1.0 2.0 VCAMMTR From low power to active and from, active to low power, VIN = VINMIN, VINMAX, IL = ILMAXLP % VSD ACTIVE MODE - AC PSRR - IL = 75% of ILMAX, 20 Hz to 20 kHz VSDPSSR dB VIN = VINMIN + 100 mV 35 40 - VIN = VNOM + 1.0 V 50 60 - 100 Hz – 1.0 kHz - -115 - >1.0 kHz – 10 kHz - -126 - >10 kHz – 1.0 MHz - -132 - Max Output Noise - VIN = VINMIN, IL = 75% of ILMAX VSDON dBV/√Hz Turn-on Time (Enable to 90% of end value, VIN = VINMIN, VINMAX, IL = 0) VSDtON - - 1.0 ms Turn-off Time (Disable to 10% of initial value, VIN = VINMIN, VINMAX, IL = 0) VSDtOFF 0.1 - 10 ms Transient Load Response - See Transient Response Waveforms on page 49 VSDTLOR - VSD[2:0]=010 to 111 - 1.0 2.0 % - VSD[2:0]=000 to 001 - - 70 mV - 5.0 8.0 - - 100 VIN = VINMIN, VINMAX Transient Line Response - See Transient Response Waveforms on page 49 VSDTLIR IL = 75% of ILMAX Mode Transition Time - See Transient Response Waveforms on page 49 VSDtMOD From low power to active, VIN = VINMIN, VINMAX, IL = ILMAXLP Mode Transition Response - See Transient Response Waveforms on page 49 mV µs VSDMTR % - 1.0 2.0 35 40 - 100 Hz – 50 kHz - 1.0 - >50 kHz – 1.0 MHz - 0.2 - VIN = VINMIN + 100 mV 35 40 - VIN = VNOM + 1.0 V 50 60 - 100 Hz – 1.0 kHz - 20 - dB/dec >1.0 kHz – 1.0 MHz - 0.2 - µV/√Hz From low power to active and from active to low power, VIN = VINMIN, VINMAX, IL = ILMAXLP VUSB ACTIVE MODE - AC PSRR - IL = 75% of ILMAX, 20 Hz to 20 kHz VUSBPSSR VIN = VINMIN + 100 mV Max Output Noise - VIN = VINMIN, IL = 75% of ILMAX dB VUSBON µV/√Hz VUSB2 ACTIVE MODE - AC PSRR - IL = 75% of ILMAX, 20 Hz to 20 kHz Output Noise - VIN = VINMIN, IL = 0.75*ILMAX VUSB2PSSR dB VUSB2ON 13892 28 Analog Integrated Circuit Device Data Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions 3.1 V ≤ BATT ≤ 4.8 V, --30 ≤ TA ≤ 85°C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max - - 100 0.1 - 10 Unit VUSB2 ACTIVE MODE - AC (CONTINUED) Turn-on Time VUSB2tON Enable to 90% of end value, VIN = VINMIN, VINMAX, IL = 0 Turn-off Time VUSBtOFF Disable to 10% of initial value, VIN = VINMIN, VINMAX, IL = 0 Start-up Overshoot % - 1.0 2.0 - 1.0 2.0 - 5.0 8.0 VUSB2TLOR VIN = VINMIN, VINMAX Transient Line Response - See Transient Response Waveforms on page 49 ms VUSB2OS VIN = VINMIN, VINMAX, IL = 0 Transient Load Response - See Transient Response Waveforms on page 49 µs % VUSB2TLIR IL = 75% of ILMAX mV UVBUS ACTIVE MODE DC Turn-on Time UVBUStON VBUS Rise Time per USB OTG with max loading of 6.5 µF+10 µF Turn-off Time ms - - 100 UVBUStOFF Disable to 0.8 V, per USB OTG specification parameter VA_SESS_VLD, VIN = VINMIN, VINMAX, IL=0 sec - - 1.3 VIN = UVDET 35 40 - VIN = VNOM + 1.0 V, > UVDET 50 60 - 100 Hz – 1.0 kHz - -115 - >1.0 kHz – 10 kHz - -126 - >10 kHz – 1.0 MHz - -132 - - - 1.0 0.1 - 10 - 1.0 3.0 % - - 70 mV VGEN1 ACTIVE MODE - AC PSRR - IL = 75% of ILMAX, 20 Hz to 20 kHz Max Output Noise - VIN = VINMIN, IL = 0.75*ILMAX Turn-on Time VGEN1PSSR VGEN1ON ms VGEN1tOFF Disable to 10% of initial value VIN = VINMIN, VINMAX, IL = 0 Transient Load Response - See Transient Response Waveforms on page 49 dBV/√Hz VGEN1tON Enable to 90% of end value VIN = VINMIN, VINMAX, IL = 0 Turn-off Time dB ms VGEN1TLOR VIN = VINMIN, VINMAX - VGEN1[1:0]=10 to 11 - VGEN[1:0]=00 to 01 Transient Line Response - See Transient Response Waveforms on page 49 VGEN1TLIR IL = 75% of ILMAX Mode Transition Time - See Transient Response Waveforms on page 49 From low power to active and from active to low power VIN = VINMIN, VINMAX, IL = ILMAXLP - 5.0 8.0 - - 100 - 1.0 2.0 VGEN1tMOD From low power to active VIN = VINMIN, VINMAX, IL = ILMAXLP Mode Transition Response - See Transient Response Waveforms on page 49 mV µs VGEN1MTR % 13892 Analog Integrated Circuit Device Data Freescale Semiconductor 29 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions 3.1 V ≤ BATT ≤ 4.8 V, --30 ≤ TA ≤ 85°C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit VGEN2 ACTIVE MODE - AC PSRR - IL = 75% of ILMAX, 20 Hz to 20 kHz VGEN2PSSR dB VIN = VINMIN + 100 mV 35 40 - VIN = VNOM + 1.0 V 50 60 - 100 Hz – 1.0 kHz - -115 - >1.0 kHz – 10 kHz - -126 - >10 kHz – 1.0 MHz - -132 - - - 1.0 0.1 - 10 ms - 1.0 3.0 % - - 70 mV Max Output Noise - VIN = VINMIN, IL = ILMAX Turn-on Time VGEN2ON dBV/√Hz VGEN2tON Enable to 90% of end value VIN = VINMIN, VINMAX, IL = 0 Turn-off Time (Disable to 10% of initial value VIN = VINMIN, VINMAX, IL = 0) VGEN2tOFF Transient Load Response - See Transient Response Waveforms on page 49 VGEN2TLOR ms VIN = VINMIN, VINMAX - VGEN2[2:0]=100 to 111 - VGEN2[2:0]=000 to 011 Transient Line Response - See Transient Response Waveforms on page 49 VGEN2TLIR IL = 75% of ILMAX Mode Transition Time - See Transient Response Waveforms on page 49 - 5.0 8.0 - - 100 - 1.0 2.0 35 40 - 45 50 - VGEN2tMOD From low power to active VIN = VINMIN, VINMAX, IL = ILMAXLP Mode Transition Response - See Transient Response Waveforms on page 49 mV µs VGEN2MTR % From low power to active and from active to low power VIN = VINMIN, VINMAX, IL = ILMAXLP VGEN3 ACTIVE MODE - AC PSRR VGEN3PSSR IL = 75% of ILMAX, 20 Hz to 20 kHz, VIN = VINMIN +100 mV Vin=Vnom+1V Output Noise - VIN = VINMIN, IL = 75% of ILMAX dB VGEN3ON 100 Hz – 1.0 kHz - 20 - dB/dec >1.0 kHz – 1.0 MHz - 1.0 - µV/√Hz - - 1.0 0.1 - 5.0 - VGEN3=1 - 1.0 2.0 % - VGEN3=0 - - 70 mV - 5.0 8.0 mV Turn-on Time VGEN3tON Enable to 90% of end value VIN = VINMIN, VINMAX, IL = 0 Turn-off Time VGEN3tOFF Disable to 10% of initial value VIN = VINMIN, VINMAX, IL = 0 Transient Load Response ms ms VGEN3TLOR VIN = VINMIN, VINMAX Transient Line Response (IL = 75% of ILMAX) VGEN3TLIR 13892 30 Analog Integrated Circuit Device Data Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions 3.1 V ≤ BATT ≤ 4.8 V, --30 ≤ TA ≤ 85°C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit - - 100 - 1.0 2.0 Turn-On Time - VBUS Rise Time por USB OTG with max loading of 6.5 µF+10 µF - - 100 ms Turn-Off Time - Disable to 0.8 V, per USB OTG specification parameter VA_SESS_VLD VIN = VINMIN, VINMAX, IL=0 - - 1.3 sec 10 µs VGEN3 ACTIVE MODE - AC (CONTINUED) Mode Transition Time VGEN3tMOD From low power to active VIN = VINMIN, VINMAX, IL = ILMAXLP Mode Transition Response From low power to active and from active to low power, VIN = VINMIN, VINMAX, IL = ILMAXLP µs VGEN3MTR % UVBUS - ACTIVE MODE DC ADC Conversion Time per Channel - PLLX[2:0]=100 Turn On Delay µs If Switcher PLL was active - 0 - If Switcher PLL was inactive - 5 10 TOUCH SCREEN Turn-on Time - 90% of output 500 µs 13892 Analog Integrated Circuit Device Data Freescale Semiconductor 31 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS desired supply. This would typically be tied to SW4 programmed for 1.80 V. The strength of the MISO driver is programmable through the SPIDRV[1:0] bits. Figure 5 and Table 6 summarize the SPI electrical and timing requirements. The SPI input and output levels are set independently via the SPIVCC pin by connecting it to the TCLKPER CS TCLKHIGH TCLKLOW TSELLOW TSELHLD TSELSU CLK TWRTSU TWRTHLD MOSI TRDSU TRDEN TRDHLD TRDDIS MISO Figure 5. Timing Requirements Table 6. Timing Parameter Description PARAMETER DESCRIPTION T MIN (NS) tSELSU Time CS has to be high before the first rising edge of CLK 15 tSELHID Time CS has to remain high after the last falling edge of CLK 15 tSELLOW Time CS has to remain low between two transfers 15 tCLKPER Clock period of CLK 38 tCLKHIGH Part of the clock period where CLK has to remain high 15 tCLKLOW Part of the clock period where CLK has to remain low 15 tWRTSU Time MOSI has to be stable before the next rising edge of CLK 4.0 tWRTHLD Time MOSI has to remain stable after the rising edge of CLK 4.0 tRDSU Time MISO will be stable before the next rising edge of CLK 4.0 tRDHLD Time MISO will remain stable after the falling edge of CLK 4.0 tRDEN Time MISO needs to become active after the rising edge of CS 4.0 tRDDIS Time MISO needs to become inactive after the falling edge of CS 4.0 Notes 26. This table reflects a maximum SPI clock frequency of 26 MHz. Slew rate for SPI MISO output driver is programmable from 0.16 to 0.66 V/ns 13892 32 Analog Integrated Circuit Device Data Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION CHARGER CHRGRAW 1. Charger input. The charger voltage is measured through an ADC at this pin. The UVBUS pin must be shorted to CHRGRAW in cases where the charger is being supplied from the USB cable. The minimum voltage for this pin depends on BATTMIN threshold value (see Battery Management). 2. Output to battery supplied accessories. The battery voltage can be applied to an accessory by enabling the charge path for the accessory via the CHRGRAW pin. To accomplish this, the charger needs to be configured in reverse supply mode. CHRGCTRL1 Driver output for charger path FET M1. CHRGCTRL2 Driver output for charger path FET M2. CHRGISNS Charge current sensing point 1. The charge current is read by monitoring the voltage drop over the charge current 100 mΩ sense resistor connected between CHRGISNS and BPSNS. BPSNS 1. BP sense point. BP voltage is sensed at this pin and compared with the voltage at CHRGRAW. 2. Charge current sensing point 2. The charge current is read by monitoring the voltage drop over the charge current 100 mΩ sense resistor. This resistor is connected between CHRGISNS and BPSNS. BP This pin is the application supply point, the input supply to the IC core circuitry. The application supply voltage is sensed through an ADC at this pin. BATTFET Driver output for battery path FET M3. If no charging system is required, the pin BATTFET must be floating. When single path is implemented, it must be connected to ground. BATTISNS Battery current sensing point 1. The current flowing out of and into the battery can be read via the ADC by monitoring the voltage drop over the sense resistor between BATT and BATTISNS. BATT Battery positive terminal. Battery current sensing point 2. The supply voltage of the battery is sensed through an ADC on this pin. The current flowing out of and into the battery can be read via the ADC by monitoring the voltage drop over the sense resistor between BATT and BATTISNS. BATTISNSCC Accumulated current counter current sensing point. This is the coulomb counter current sense point. It should be connected directly to the 0.020 Ω sense resistor via a separate route from BATTISNS. The coulomb counter monitors the current flowing in/out of the battery by integrating the voltage drop over the BATTISNCC and the BATT pin. CFP AND CFM Accumulated current filter cap plus and minus terminals respectively. The coulomb counter will require a 10 µF output capacitor connected between these pins to perform a first order filtering of the signal across R1. CHRGSE1B An unregulated wall charger configuration can be built in which case this pin must be pulled low. When charging through USB, it can be left open since it is internally pulled up to VCORE. The recommendation is to place an external FET that can pull it low or left it open, depending on the charge method. CHRGLED Trickle LED driver output 1. Since normal LED control via the SPI bus is not always possible in the standalone operation, a current sink is provided at the CHRGLED pin. This LED is to be connected between this pin and CHRGRAW. GNDCHRG Ground for charger interface. LEDR, LEDG AND LEDB General purpose LED driver output Red, Green and Blue respectively. Each channel provides flexible LED intensity control. These pins can also be used as general purpose open drain outputs for logic signaling, or as generic PWM generator outputs. GNDLED E5 Ground for LED drivers 13892 Analog Integrated Circuit Device Data Freescale Semiconductor 33 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION IC CORE VCORE Regulated supply output for the IC analog core circuitry. It is used to define the PUMS VIH level during initialization. The bandgap and the rest of the core circuitry are supplied from VCORE. Place a 2.2 μF capacitor from this pin to GNDCORE. VCOREDIG Regulated supply output for the IC digital core circuitry. No external DC loading is allowed on VCOREDIG. VCOREDIG is kept powered as long as there is a valid supply and/or coin cell. Place a 2.2 μF capacitor from this pin to GNDCORE. REFCORE Main bandgap reference. All regulators use the main bandgap as the reference. The main bandgap is bypassed with a capacitor at REFCORE. No external DC loading is allowed on REFCORE. Place a 100 nF capacitor from this pin to GNDCORE. farther point of each of their respective SWxOUT pin, in order to sense and maintain voltage stability. SW1OUT Switcher 1 output. Buck switcher for processor core(s). GNDSW1 Ground for Switcher 1. SW2OUT Switcher 2 output. Buck switcher for processor SOG, etc. GNDSW2 Ground for Switcher 2. SW3OUT Switcher 3 output. Buck switcher for internal processor memory and peripherals. GNDSW3 Ground for switcher 3. GNDCORE Ground for the IC core circuitry. SW4OUT POWER GATING Switcher 4 output. Buck switcher for external memory and peripherals. PWGTDRV1 AND PWGTDRV2 GNDSW4 Ground for switcher 4. Power Gate Drivers. PWGTDRV1 is provided for power gating peripheral loads sharing the processor core supply domain(s) SW1, and/or SW2, and/or SW3. In addition, PWGTDRV2 provides support to power gate peripheral loads on the SW4 supply domain. In typical applications, SW1, SW2, and SW3 will both be kept active for the processor modules in state retention, and SW4 retained for the external memory in self refresh mode. SW1, SW2, and SW3 power gating FET drive would typically be connected to PWGTDRV1 (for parallel NMOS switches). SW4 power gating FET drive would typically be connected to PWGTDRV2. When low power Off mode is activated, the power gate drive circuitry will be disabled, turning off the NMOS power gate switches to isolate the maintained supply domains from any peripheral loading. Switcher BST input. The 2.2 μH switcher BST inductor must be connected here. SWITCHERS SWBSTOUT SW1IN, SW2IN, SW3IN AND SW4IN Power supply for gate driver for the internal power NMOS that charges SWBST inductor. It must be connected to BP. Switchers 1, 2, 3, and 4 input. Connect these pins to BP to supply Switchers 1, 2, 3, and 4. SW1FB, SW2FB, SW3FB AND SW4FB Switchers 1, 2, 3, and 4 feedback. Switchers 1, 2, 3, and 4 output voltage sense respectively. Connect these pins to the DVS1 AND DVS2 Switcher 1 and 2 DVS input pins. Provided for pin controlled DVS on the buck switchers targeted for processor core supplies. The DVS pins may be reconfigured for Switcher Increment / Decrement (SID) mode control. When transitioning from one voltage to another, the output voltage slope is controlled in steps of 25 mV per time step. These pins must be set high in order for the DVS feature to be enabled for each of switchers 1 or 2, or low to disable it. SWBSTIN SWBSTFB Switcher BST feedback. When SWBST is configured to supply the UVBUS pin in OTG mode the feedback will be switched to sense the UVBUS pin instead of the SWBSTFB pin. 13892 34 Analog Integrated Circuit Device Data Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION GNDSWBST Ground for switcher BST. VINCAMDRV VINIOHI 1. Input regulator camera using internal PMOS FET. Typically connected to BP. 2. Drive output regulator for camera voltage using external PNP device. In this case, this pin must be connected to the base of the PNP in order to drive it. Input of VIOHI regulator. Connect this pin to BP in order to supply VIOHI regulator. VCAM VIOHI Output regulator for the camera module. When using an external PNP device, this pin must be connected to its collector. REGULATORS Output regulator for high voltage IO. Fixed 2.775 V output for high voltage level interface. VINPLL AND VINDIG The input of the regulator for processor PLL and Digital regulators respectively. VINDIG and VINPLL can be connected to either BP or a 1.8 V switched mode power supply rail, such as from SW4 for the two lower set points of each regulator (the 1.2 and 1.25 V output for VPLL, and 1.05 and 1.25 V output for VDIG). In addition, when the two upper set points are used (1.50 and 1.8V outputs for VPLL, and 1.65 and 1.8V for VDIG), they can be connected to either BP or a 2.2V nominal external switched mode power supply rail, to improve power dissipation. VPLL Output of regulator for processor PLL. Quiet analog supply (PLL, GPS). VDIG Output regulator Digital. Low voltage digital (DPLL, GPS). VVIDEODRV Drive output for VVIDEO external PNP transistor. VVIDEO Output regulator TV DAC. This pin must be connected to the collector of the external PNP transistor of the VVIDEO regulator. VINAUDIO Input regulator VAUDIO. Typically connected to BP. VAUDIO Output regulator for audio supply. VINUSB2 Input regulator VUSB2. This pin must always be connected to BP even if the regulators are not used by the application. VUSB2 Output regulator for powering USB PHY. VSDDRV Drive output for the VSD external PNP transistor. VSD Output regulator for multi-media cards such as micro SD, RS-MMC. VGEN1DRV Drive output for the VGEN1 external PNP transistor. VGEN1 Output of general purpose 1 regulator. VGEN2DRV Drive output for the VGEN2 external PNP transistor. VGEN2 Output of general purpose 2 regulator. VINGEN3DRV 1. Input for the VGEN3 regulator when no external PNP transistor used. Typically connected to BP. 2. Drive output for VGEN3 in case an external PNP transistor is used on the application. In this case, this pin must be connected the base of the PNP transistor. VGEN3 Output of general purpose 3 regulator. VSRTC Output regulator for the SRTC module on the processor. The VSRTC regulator provides the CLK32KMCU output level (1.2 V). Additionally, it is used to bias the Low Power SRTC domain of the SRTC module integrated on certain FSL processors. GNDREG1 Ground for regulators 1. GNDREG2 Ground for regulators 2. 13892 Analog Integrated Circuit Device Data Freescale Semiconductor 35 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION GNDREG3 Ground for regulators 3. GPO1 General purpose output 1. Intended to be used for battery thermistor biasing. In this case, connect a 10 KΩ resistor from GPO1 to ADIN5, and one from ADIN5 to GND. GPO2 General purpose output 2. GPO3 General purpose output 3. GPO4 General purpose output 4. It can be configured for a muxed connection into Channel 7 of the GP ADC. CONTROL LOGIC LICELL Coin cell supply input and charger output. The LICELL pin provides a connection for a coin cell backup battery or supercap. If the main battery is deeply discharged, removed, or contact-bounced (i.e., during a power cut), the RTC system and coin cell maintained logic will switch over to the LICELL for backup power. This pin also works as a currentlimited voltage source for battery charging. A small capacitor should be placed from LICELL to ground under all circumstances. XTAL1 32.768 kHz Oscillator crystal connection 1. XTAL2 32.768 kHz Oscillator crystal connection 2. GNDRTC Ground for the RTC block. CLK32K peripheral clock reference), which is referenced to SPIVCC. The CLK32K is restricted to state machine activation in normal on mode. CLK32KMCU 32 kHz Clock output for processor. At system start-up, the 32 kHz clock is driven to CLK32KMCU (intended as the CKIL input to the system processor) referenced to VSRTC. The driver is enabled by the start-up sequencer and the CLK32KMCU is programmable for Low Power Off mode control by the state machine. RESETB AND RESETBMCU Reset output for peripherals and processor respectively. These depend on the Power Control Modes of operation (See Functional Device Operation on page 42). These are meant as reset for the processor, or peripherals in a power up condition, or to keep one in reset while the other is up and running. WDI Watchdog input. This pin must be high to stay in the On mode. The WDI IO supply voltage is referenced to SPIVCC (normally connected to SW4=1.8 V). SPIVCC must therefore remain enabled to allow for proper WDI detection. If WDI goes low, the system will transition to the Off state or Cold Start (depending on the configuration). STANDBY AND STANDBYSEC Standby input signal from processor and from peripherals respectively. To ensure that shared resources are properly powered when required, the system will only be allowed into Standby when both the application processor (which typically controls the STANDBY pin) and peripherals (which typically control the STANDBYSEC pin) allow it. This is referred to as a Standby event. The Standby pins are programmable for Active High or Active Low polarity, and that decoding of a Standby event will take into account the programmed input polarities associated with each pin. Since the Standby pin activity is driven asynchronously to the system, a finite time is required for the internal logic to qualify and respond to the pin level changes. 32 kHz Clock output for peripherals. At system start-up, the 32 kHz clock is driven to CLK32K (provided as a 13892 36 Analog Integrated Circuit Device Data Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION Table 7. Standby Control Pins STANDBY (PIN) STANDBYINV (SPI BIT) STANDBYSEC (PIN) STANDBYSECINV (SPI BIT) STANDBY CONTROL(27) 0 0 x x 0 x x 0 0 0 1 1 x x 0 x x 1 1 0 0 1 0 1 1 0 1 1 0 1 1 0 0 1 1 1 0 1 0 1 Notes 27. STANDBY = 0: System is not in Standby; STANDBY=1: System is in Standby and Standby programmability is activated. The state of the Standby pins only have influence in the On mode and are therefore ignored during start up and in the Watchdog phase. This allows the system to power up without concern of the required Standby polarities, since software can make adjustments accordingly, as soon as it is running. INT Interrupt to processor. Unmasked interrupt events are signaled to the processor by driving the INT pin high. PWRON1, 2 AND 3 A turn on event can be accomplished by connecting an open drain NMOS driver to the PWRONx pin of the 13892, so that it is in effect a parallel path for the power key. In addition to the turn on event, the 13892A/B versions include a global reset feature on the PWRON3 pin. The 13892A version has the global reset feature enabled by default. The 13892B version has the global reset feature disabled by default, but can be enabled by setting the SPI bit GLBRSTENB = 0. The global reset feature powers down the part, disables the charger, resets the SPI registers to their default value and then powers back on. To enable a global reset the PWRON3 pin needs to be pulled low for greater than 12 seconds and then pulled back high. If the PWRON3 pin is held low for less than 12 seconds the pin will act as a normal PWRON pin. PUMS1 AND PUMS2 Power up mode supply setting. Default start-up of the device is selectable by hardwiring the Power Up Mode Select pins. The Power Up Mode Select pins (PUMS1 and PUMS2) are used to configure the start-up characteristics of the regulators. Supply enabling and output level options are selected by hardworking the PUMS pins for the desired configuration. The following power up defaults table shows the initial setup for the voltage level of the switchers and regulators, and if they get enabled or not, according to the PUMS pins configuration. 13892 Analog Integrated Circuit Device Data Freescale Semiconductor 37 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION Table 8. Power Up Defaults i.MX 37/51 37/51 37/51 37/51 35 27/31 PUMS1 GND OPEN VCOREDIG VCORE GND OPEN PUMS2 OPEN OPEN OPEN OPEN GND GND (28) 0.775 1.050 1.050 0.775 1.200 1.200 SW2(28) 1.025 1.225 1.225 1.025 1.350 1.450 SW3(28) 1.200 1.200 1.200 1.200 1.800 1.800 (28) 1.800 1.800 1.800 1.800 1.800 1.800 Off Off Off Off 5.000 5.000 VUSB 3.300(29) 3.300(29) 3.300(29) 3.300(29) 3.300(31) 3.300(31) VUSB2 2.600 2.600 2.600 2.600 2.600 2.600 VPLL 1.800 1.800 1.800 1.800 1.500 1.500 VDIG 1.250 1.250 1.250 1.250 1.250 1.250 VIOHI 2.775 2.775 2.775 2.775 2.775 2.775 VGEN2 3.150 Off 3.150 Off 3.150 3.150 Off Off Off Off 3.15 3.15 SW1 SW4 SWBST VSD Notes 28. The switchers SWx are activated in PWM pulse skipping mode allowed when enabled by the startup sequencer. 29. USB supplies VUSB, is only enabled if 5.0 V is present on UVBUS. 30. The following supplies are not included in the matrix, since they are not intended for activation by the start-up sequencer: VCAM, VGEN1, VGEN3, VVIDEO, and VAUDIO. 31. SWBST = 5.0 V, powers up, as does VUSB, regardless of the 5.0 V present on UVBUS. By default VUSB will be supplied by SWBST. 13892 38 Analog Integrated Circuit Device Data Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION Table 9. Power Up Sequence Tap x 2.0 ms PUMS2 = OPEN (I,MX37,i.MX51) PUMS2 = GND (i.MX35,i.MX27) 0 SW2 SW2 1 SW4 VGEN2 2 VIOHI SW4 3 VGEN2 VIOHI, VSD 4 SW1 SWBST, VUSB(35) 5 SW3 SW1 6 VPLL VPLL 7 VDIG SW3 8 VDIG VUSB(34), 9 VUSB2 VUSB2 Notes 32. Time slots may be included for blocks which are defined by the PUMS pins as disabled, to allow for potential activation. 33. The following supplies are not included in the matrix, since they are not intended for activation by the start-up sequencer: VCAM, VGEN1, VGEN3, VVIDEO, and VAUDIO. SWBST is not included on the PUMS2 = Open column 34. USB supplies VUSB, is only enabled if 5.0 V is present on UVBUS. 35. SWBST = 5.0 V, powers up, as does VUSB, regardless of the 5.0 V present on UVBUS. By default VUSB will be supplied by SWBST. MODE USB LBP mode, normal mode, test mode selection & antifuse bias. During evaluation and testing, the IC can be MODE PIN STATE configured for normal operation or test mode via the MODE pin as summarized in the following table. MODE Ground Normal Operation VCOREDIG USB Low Power Boot Allowed VCORE Test Mode GNDCTRL Ground for control logic. SPIVCC Supply for SPI bus and audio bus CS CS held low at Cold Start configures the interface for SPI mode. Once activated, CS functions as the SPI Chip Select. CS tied to VCORE at Cold Start configures the interface for I2C mode; the pin is not used in I2C mode other than for configuration. Because the SPI interface pins can be reconfigured for reuse as an I2C interface, a configuration protocol mandates that the CS pin is held low during a turn on event for the IC (a weak pull-down is integrated on the CS pin). CLK Primary SPI clock input. In I2C mode, this pin is the SCL signal (I2C bus clock). MOSI Primary SPI write input. In I2C mode, the MOSI pin hard wired to ground or VCORE is used to select between two possible addresses (A0 address selection). MISO Primary SPI read output. In I2C mode, this pin is the SDA signal (bi-directional serial data line). GNDSPI Ground for SPI interface. 13892 Analog Integrated Circuit Device Data Freescale Semiconductor 39 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION USB can be read via the SPI, to poll dedicated sense bits for a floating, grounded, or factory mode condition on the UID pin. UID This pin identifies if a mini-A or mini-B style plug has been connected to the application. The state of the ID detection Table 10. UID Pin Levels UID PIN EXTERNAL CONNECTION UID PIN VOLTAGE ACCESSORY Resistor to Ground 0.18*VCORE<UID<0.77*VCORE Non-USB accessory is attached Grounded 0<UID<0.12*VCORE A type plug (USB Host) Floating 0.89*VCORE<UID<VCORE B type plug (USB peripheral, OTG device or no device) is attached Voltage Applied 3.6 V<UID(36) Factory mode Notes 36. UID maximum voltage is 5.25 V UVBUS 1. USB transceiver cable interface. 2. OTG supply output. When SWBST is configured to supply the UVBUS pin in OTG mode, the feedback will switch to sense the UVBUS pin instead of the SWBSTFB pin. thermistor must be biased with an external pull-up to a voltage rail greater than the ADC input range. In order to save current when the thermistor reading is not required, it can be biased from one of the general purpose IOs such as GPO1. A resistor divider network should assure the resulting voltage falls within the ADC input range, in particular when the thermistor check function is used. VUSB ADIN6 This is the regulator used to provide a voltage to an external USB transceiver IC. ADC generic input channel 6. ADIN6 may be used as a general purpose unscaled input, but in a typical application, the PA thermistor is connected here. VINUSB Input option for VUSB; supplied by SWBST. This pin is internally connected to the UVBUS pin for OTG mode operation (for more details about OTG mode See OTG mode (On the Go) on page 57). Note: When VUSBIN =1, UVBUS will be connected via internal switches to VINUSB and incur some current drain on that pin, as much as 270uA maximum, so care must be taken to disable this path and set this SPI bit (VUSBIN) to 0 to minimize current drain, even if SWBST and/or VUSB are disabled. VBUSEN External VBUS enable pin for the OTG supply. VBUS is defined as the power rail of the USB cable (+5.0 V). A TO D CONVERTER Note: The ADIN5/6/7 inputs must not exceed BP. ADIN5 ADC generic input channel 5. ADIN5 may be used as a general purpose unscaled input, but in a typical application, ADIN5 is used to read out the battery pack thermistor. The ADIN7 ADC generic input channel 7, group 1. ADIN7 may be used as a general purpose unscaled input or as a divide by 2 scaled input. In a typical application, an ambient light sensor is connected here. A second general purpose input ADIN7B is available on channel 7. This input is muxed on the GPO4 pin. In the application, a second ambient light sensor is supposed to be connected here. TSX1 AND TSX2, TSY1 AND TSY2 Note: The TS[xy] [12] inputs must not exceed BP or VCORE. Touch Screen Interfaces X1 and X2, Y1 and Y2. The touch screen X plate is connected to TSX1 and TSX2, while the Y plate is connected to Y1 and Y2. In inactive mode, these pins can also be used as general purpose ADC inputs. They are respectively mapped on ADC channels 4, 5, 6, and 7. In interrupt mode, a voltage is applied to the X-plate (TSX2) via a weak current source to VCORE, while the Yplate is connected to ground (TSY1). 13892 40 Analog Integrated Circuit Device Data Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION TSREF Touch Screen Reference regulator. This regulator is powered from VCORE. In applications not supporting touch screen, the TSREF can be used as a low current general purpose regulator, or it can be kept disabled and the bypass capacitor omitted. ADTRIG GNDADC Ground for A to D circuitry. THERMAL GROUNDS GNDSUB1-9 Non critical signal grounds and thermal heat sinks. ADC trigger input. A rising edge on this pin will start an ADC conversion. 13892 Analog Integrated Circuit Device Data Freescale Semiconductor 41 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. FUNCTIONAL DEVICE OPERATION FUNCTIONAL DEVICE OPERATION PROCESSOR LOGIC INTERFACING CLOCK GENERATION A system clock is generated for internal digital circuitry as well as for external applications utilizing the clock output pins. A crystal oscillator is used for the 32.768 kHz time base and generation of related derivative clocks. If the crystal oscillator is not running (for example, if the crystal is not present), an internal 32 kHz oscillator will be used instead. Support is also provided for an external Secure Real Time Clock (SRTC), which may be integrated on a companion system processor IC. For media protection in compliance with Digital Rights Management (DRM) system requirements, the CLK32KMCU can be provided as a reference to the SRTC module, where tamper protection is implemented. The internal 32kHz oscillator is an integrated backup for the crystal oscillator and provides a 32.768 kHz nominal frequency at 20% accuracy if running. The internal oscillator only runs if a valid supply is available at BP and would not be used as long as the crystal oscillator is active. In absence of a valid supply at the BP supply node (for instance due to a dead battery), the crystal oscillator continues running supplied from the coin cell battery until the coin cell is depleted. All control functions will run off the crystal derived frequency, occasionally referred to as “32 kHz” for brevity’s sake. The crystal oscillator has been optimized for use in conjunction with the Micro Crystal CC7V-T1A32.768 kHz-9.0 pF-30 ppm or equivalent (such as the Micro Crystal CC5V-T1A or Epson FC135) is capable of handling its parametric variations. The electrical characteristics of the 32 kHz crystal oscillator are given in Tables 4 and 5, taking into account the crystal characteristics noted previously. The oscillator accuracy depends largely on the temperature characteristics of the used crystal. Application circuits can be optimized for required accuracy by adapting the external crystal oscillator network (via component accuracy and/or tuning). Additionally, a clock calibration system is provided to adjust the 32,768 cycle counter that generates the 1.0 Hz timer and RTC registers; see the RTC section for more detail. by connecting an open drain NMOS driver to the PWRON pin of 13892 so that it is in effect a parallel path for the power key. The 13892 will not be able to discern the turn on event from a normal power key initiated turn on, but the processor should have the knowledge since the RTC initiated turn on is generated locally. The VSRTC regulator provides the CLK32KMCU output level. It is also used to bias the Low Power SRTC domain of the SRTC module integrated on certain FSL processors. The VSRTC regulator is enabled as soon as the RTCPORB is detected. The VSRTC cannot be disabled. VSRTC REAL TIME CLOCK A Real Time Clock (RTC) is provided with time and day counters as well as an alarm function. The RTC utilizes the 32.768 kHz crystal oscillator for the time base, and is powered by the coin cell backup supply when BP has dropped below operational range. In configurations where the SRTC is used, the RTC can be disabled to conserve current drain by setting the RTCDIS bit to a 1 (defaults on at power up). TIME AND DAY COUNTERS The 32.768 kHz clock is divided down to a 1.0 Hz time tick which drives a 17 bit Time Of Day (TOD) counter. The TOD counter counts the seconds during a 24 hour period from 0 to 86,399 and will then roll over to 0. When the roll over occurs, it increments the 15 bit DAY counter. The DAY counter can count up to 32767 days. The 1.0 Hz time tick can be used to generate a 1.0 Hz interrupt if unmasked. TIME OF DAY ALARM A Time Of Day Alarm (TODA) function can be used to turn on the application and alert the processor. If the application is already on, the processor will be interrupted. The TODA and DAYA registers are used to set the alarm time. When the TOD counter is equal to the value in TODA and the DAY counter is equal to the value in DAYA, the TODAI interrupt will be generated. TIMER RESET SRTC SUPPORT AND VSRTC When configured for DRM mode (SPI bit DRM=1), the CLK32KMCU driver will be kept enabled through all operational states to ensure that the SRTC module always has its reference clock. If DRM=0, the CLK32KMCU driver will not be maintained in the Off state. It is also necessary to provide a means for the processor to do an RTC initiated wake-up of the system if it has been programmed for such capability. This can be accomplished As long as the supply at BP is valid, the real time clock will be supplied from VCORE. If not, it can be backed up from a coin cell via the LICELL pin. When the backup voltage drops below RTCUVDET, the RTCPORB reset signal is generated and the contents of the RTC will be reset. Additional registers backed up by coin cell will also reset with RTCPORB. To inform the processor that the contents of the RTC are no longer valid due to the reset, a timer reset interrupt function is implemented with the RTCRSTI bit. 13892 42 Analog Integrated Circuit Device Data Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. FUNCTIONAL DEVICE OPERATION COIN CELL BATTERY BACKUP The LICELL pin provides a connection for a coin cell backup battery or supercap. If the main battery is deeply discharged, removed, or contact-bounced (i.e., during a power cut), the RTC system and coin cell maintained logic will switch over to the LICELL for backup power. A small capacitor should be placed from LICELL to ground under all circumstances. Coin cells can get damaged and their lifetime reduced when deeply discharged. In order to avoid this, the internal circuitry supplied from LICELL is disconnected for voltages below the coin cell disconnect threshold. This will also cause the ADC reading of the coin cell voltage to yield zero. The coin cell charger circuit will function as a currentlimited voltage source, resulting in the CC/CV taper characteristic typically used for rechargeable Lithium-Ion batteries. The coin cell voltage is programmable from 2.5 to 3.3 V in 0.1 V steps, excepting 2.6 V. The coin cell charger voltage is programmable in the ON state where the charge current is fixed at ICOINHI. When the device is working in any of the low Power Off modes, the coin cell charger will also go into a low power mode in which the current it supplies to the coin cell will be reduced in order to save power. Table 11. 13892 Coin Cell Battery Electrical Characteristics PARAMETER TYP UNITS Voltage Accuracy 100 mV Coin Cell Charge Current in On and Watchdog modes ICOINHI 60 µA Coin Cell Charge Current in Off and Low Power Off modes (User Off/Memory Hold) ICOINLO 10 µA Current Accuracy 30 % LICELL Bypass Capacitor 100 nF LICELL Bypass Capacitor as coin cell 4.7 µF CONTROL INTERFACE SPI/I2C The IC contains a number of programmable registers for control and communication. The majority of registers are accessed through an SPI interface in a typical application. The same register set may be alternatively accessed with an I2C interface that is muxed on SPI pins. The following table describes the muxed pin options for the SPI and I2C interfaces. Table 12. 13892 Muxed Pin Options for SPI and I2C Interfaces (SPI Functions) PIN NAME CS SPI MODE FUNCTIONALITY Configuration (37) Chip Select CLK SPI Clock MISO Master In, Slave Out (data input) MOSI Master Out, Slave In (data input) Notes 37. CS held low at Cold Start configures the interface for SPI mode; once activated, CS functions as the SPI Chip Select. 13892 Analog Integrated Circuit Device Data Freescale Semiconductor 43 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. FUNCTIONAL DEVICE OPERATION SPI INTERFACE I2C INTERFACE The IC contains a SPI interface port which allows access by a processor to the register set. Via these registers, the resources of the IC can be controlled. The registers also provide status information about how the IC is operating as well as information on external signals. The SPI port utilizes 32-bit serial data words comprised of 1 write/read_b bit, 6 address bits, 1 null bit, and 24 data bits. The addressable register map spans 64 registers of 24 data bits each. When configured for I2C mode, the interface may be used to access the complete register map. Since SPI configuration is more typical, references within this document will generally refer to the common register set as a “SPI map” and bits as “SPI bits”. However, it should be understood that access reverts to I2C mode when configured as such. The SPI pins CLK and MISO are reused for the SCL and SDA lines respectively. Selection of I2C mode for the interface is configured by hardwiring the CS pin to VCORE on the application board. Table 13. Muxed Pin Options for SPI and I2C Interfaces (I2C Functions) PIN NAME I2C Mode Functionality CS Configuration(38) CLK SCL: I2CBUS clock MISO SDA: Bi-directional serial data line MOSI A0 Address Selection(39) Notes 38. CS tied to VCORE at Cold Start configures interface for I2C mode; the pin is not used in I2C mode other than for configuration. 39. In I2C mode, the MOSI pin hard wired to ground or VCORE is used to select between two possible addresses. The I2C mode of the interface is implemented generally following the Fast Mode definition, which supports up to 400 kbits/s operation. (exceptions to the standard are noted to be 7-bit only addressing and no support for General Call addressing). Timing diagrams, electrical specifications, and further details can be found in the I2C specification, which is available for download at: http://www.nxp.com/acrobat_download/literature/9398/ 39340011.pdf INTERRUPT CONTROL The system is informed about important events based on interrupts. Unmasked interrupt events are signaled to the processor by driving the INT pin high; this is true whether the communication interface is configured for SPI or I2C. Each interrupt is latched so that even if the interrupt source becomes inactive, the interrupt will remain set until cleared. Each interrupt can be cleared by writing a 1 to the appropriate bit in the Interrupt Status register. This will also cause the interrupt line to go low. If a new interrupt occurs while the processor clears an existing interrupt bit, the interrupt line will remain high. Each interrupt can be masked by setting the corresponding mask bit to a 1. As a result, when a masked interrupt bit goes high, the interrupt line will not go high. A masked interrupt can still be read from the Interrupt Status register. This gives the processor the option of polling for status from the IC. The IC powers up with all interrupts masked, so the processor must initially poll the device to determine if any interrupts are active. Alternatively, the processor can unmask the interrupt bits of interest. If a masked interrupt bit was already high, the interrupt line will go high after unmasking. Interrupts generated by external events are debounced; therefore, the event needs to be stable throughout the debounce period before an interrupt is generated. Nominal debounce periods for each event are documented in the INT summary table following later in this chapter. Due to the asynchronous nature of the debounce timer the effective debounce time can vary slightly. 13892 44 Analog Integrated Circuit Device Data Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. FUNCTIONAL DEVICE OPERATION SUPPLIES The switch mode supply subsystem include a core block for clock generation, 4 step down (buck) switching regulators and two step up (boost) switching regulators. Linear regulators are provided for key power domains not supplied directly by switching regulators or the battery. Pass devices are integrated for most regulators for board area and cost advantages. External PNP pass devices are used selectively to help manage internal power dissipation. A general application of the power tree is illustrated in the Figure 6 diagram. Supply names are suggestive of typical applications, but not restrictive. A system power scheme for portable devices is provided which includes both switching and linear regulators. Various operational modes are available for the power circuitry, which may be accessible through SPI programming and the state of the STANDBY pins. Programmable Standby mode configuration allows automated system level control to optimize quiescent efficiency without the need for or latency of SPI intervention. Charger and USB Cable Interface Accessory Battery Voltage & Current Control Protect Detect Power Audio CC Charge RTC, MEMA/B BP Coincell Peripherals SWBST 5.0V UVBUS PGATE USB PHY VUSB2 SW1 0.6 to 1.15V Coin Cell Serial Backlight Drivers Vcoredig SW2 0.6 to 1.25V SW3 1.25V SOG Core DVS Domain Internal Processor Memory Peripherals GP Core DVS Domain Alternate hardwired bias option from SW4 APL Core External Memory IO and Digital SW4 1.8V VUSB GPOs PGATE Processor Interfaces Alternate hardwired bias option from external 2.2V switcher Vcore Vcam Viohi Vpll Vdig PNP Camera VVIDEO VAUDIO PNP PNP Peripherals IO, EFUSE Core PLLs (Analog) GPS Core TV-DAC Vsd Audio SD, Tflash VGEN3 PNP Peripherals VGEN1 VGEN2 PNP PNP WLAN, BT MLC NAND Legend System Supplies External Loads Internal Loads Energy Source Figure 6. General Application of the Power Tree The minimum operating voltage for the supply tree while devices and interfaces, which can run at the same voltage maintaining the performance as specified is 3.0 V. For lower level. SW4 is used for powering external memory as well as voltages, the performance may be degraded. low voltage peripheral devices and interfaces, which can run at the same voltage level. An anticipated platform use case applies SW1 and SW2 to BUCK CONVERTERS processor power domains that require voltage alignment to Four buck switchers are provided with integrated power allow direct interfacing without bandwidth limiting switches and synchronous rectification. In a typical synchronizers. application, SW1 and SW2 are used for supplying the The buck switchers are supplied from the system supply Application Processor core power domains. Split power BP, which is drawn from the main battery or the battery domains allow independent DVS control for processor power charger (when present). Figure 7 shows a high level block optimization, or to support technologies with a mix of device diagram of the buck switchers. types with different voltage ratings. SW3 is used for powering internal processor memory as well as low voltage peripheral 13892 Analog Integrated Circuit Device Data Freescale Semiconductor 45 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. FUNCTIONAL DEVICE OPERATION SW1 SPI Control SPI Registers SW1IN Output Drive BP Bucked Output Voltage SW1 SW1OUT SW1FB 32KHz GNDSW1 Switcher Core DVS1 DVS2 GNDSW1 SW2 Control SW2IN Output Drive BP Bucked Output Voltage SW2 BP Bucked Output Voltage SW3 BP Bucked Output Voltage SW4 SW2OUT SW2FB STANDBYPRI GNDSW2 STANDBYSEC STBYDLY[1:0] SW3 Control SW3IN Output Drive SW3OUT SW3FB GNDSW3 SW4 Control SW4IN Output Drive SW4OUT SW4FB GNDSW4 = Package Pin Figure 7. Buck Switch Diagram The Buck switcher topology includes an integrated (DVS) by using SPI driven voltage steps, state machine synchronous rectifier, meaning that the rectifying diode is defined modes, and direct DVSx pin control. SW1 and SW2 implemented on chip as a low ohmic FET. The placement of also include the Switcher Increment/Decrement (SID) an external diode is therefore not required, but overall feature, with which, an increment command will increase the switcher efficiency may benefit from this. The buck set point voltage by a single 25 mV step, and a decrement command will decrease it in the same amount of voltage. The converters permit a 100% duty cycle operation. transition time for the step will be the same as programmed During normal operation several power modes are for the DVS feature. Maximum and minimum voltages are possible, depending on the loading. For medium and full programmable to ensure the switcher voltage does not go out loading, synchronous PWM control is the most efficient while a specific range. Panic mode is also included to quickly return maintaining a constant switching frequency. the switcher voltage to its normal programmed set point. The output voltages of the buck switchers are SPI When initially activated, switcher outputs will apply configurable and two output ranges are available, individually controlled stepping to the programmed value. The soft start programmed with SWxHI for SW2, SW3, and SW4 bucks, feature limits the inrush current at startup. SW1 is limited to only one output range. Presets are available Point of Load feedback is intended for minimizing errors for both the Normal and Standby operation. due to board level IR drops. The first voltage range that applies for all the Buck switchers goes from 0.6 to 1.375 V in 25 mV steps. The MODES OF OPERATION second one does not apply for SW1 and goes from 1.1 to 1.85 V also in 25 mV steps. Two PWM modes are available: SW1 and SW2 include pin controlled Dynamic Voltage PWM-NPS: sacrifices low load efficiency for a continuous Scaling (DVS) operation. When transitioning from one switching operation. voltage to another, the output voltage slope is controlled in PWM-PS: offers better low load efficiency by allowing the steps of 25 mV per time step (time step as defined for DVS absence of switching cycles at low output loading. This pulse stepping for SW1 and SW2, fixed at 4.0 μs for SW3, and SW4). This allows for support of dynamic voltage scaling 13892 46 Analog Integrated Circuit Device Data Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. FUNCTIONAL DEVICE OPERATION skipping feature improves efficiency by reducing dynamic switching losses simply by switching less often. In its lowest power mode, the switcher can regulate using hysteresis control known as a Pulse Frequency Modulation (PFM) control scheme. The frequency spectrum will be a function of input and output voltage, loading, and the external components. Due to its spectral variance and lighter drive capability, PFM mode is generally reserved for non-active radio modes and Deep Sleep operation. CURRENT LIMITER There is no max current limit. Immediately after power up, firmware should write the SWILIMB=1 SPI bit to allow max load current (refer to Electrical Characteristics). Application needs to provide current limit protection circuitry either in battery or as pre regulated supply to BP. SWITCHING FREQUENCY A PLL generates the switcher system clocking from the 32.768 kHz crystal oscillator reference. To allow for spectral optimization for reduction of spurious influence in a radio environment, the PLL can be programmed via SPI from a multiplication factor of 84 to 105, in steps of 3. BOOST CONVERTERS SWBST SWBST is a boost switching regulator with a fixed 5.0 V output. It runs at 2/3 of the switcher PLL frequency. SWBST supplies the VUSB regulator for the USB system in OTG mode, as well as the VBUS voltage at the UVBUS pin. When SWBST is configured to supply the UVBUS pin in OTG mode, the feedback will be switched to sense the UVBUS pin instead of the SWBSTFB pin. Therefore, when driving the VBUS for OTG mode, the output of the switcher may rise to 5.75 V to compensate for the voltage drops in the internal switches. Note that the parasitic leakage path for a boost switcher will cause the output voltage SWBSTOUT and SWBSTFB to sit at a Schottky drop below the battery voltage, whenever SWBST is disabled. The switching NMOS transistor is integrated on-chip. An external fly back Schottky diode, inductor, and capacitor are required. BP BP SWBSTOUT 4.7u SWBST SPI SPI Registers 32KHz 2.2uH Switcher Core SWBSTOUT SWBSTIN Control Boosted Output Voltage SWBST Output Drive 10uF SWBSTFB GNDSWBST = Package Pin Figure 8. 13892 SWBST Block Diagram. 13892 Analog Integrated Circuit Device Data Freescale Semiconductor 47 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. FUNCTIONAL DEVICE OPERATION Main characteristics of SWBST are summarized in Tables 4 and 5. PROTECTION FUNCTIONS Current Limit SWBST has an over-current limit protection of 1.5 A. A portion of the output current is sensed across an internal sense resistor which creates a drop that is then compared to a fixed voltage. The output of the comparator is the flag of over-current in the output driver of the boost converter. When an over-current is detected, the PWM cycle is stopped by turning off the internal NMOS, which allows the current in the coil to decrease. LDOS The following is a description of the linear regulators. For convenience these regulators are named to indicate their typical or possible applications, but the supplies are not limited to these uses, and may be applied to any loads within the specified regulator capabilities. A low power standby mode controlled by STANDBY is provided in which the bias current is aggressively reduced. This mode is useful for deep sleep operations, where certain supplies cannot be disabled, but active regulation can be tolerated with lesser parametric requirements. The output drive capability and performance are limited in this mode. Apart from the integrated linear regulators, there are also GPO output pins provided to enable and disable discrete regulators or functional blocks, or to use as general purpose outputs for any system need. For example, one application may be to enable a battery pack thermistor bias in synchronization with timed ADC conversions. All regulators use the main bandgap as the reference. The main bandgap is bypassed with a capacitor at REFCORE. The bandgap and the rest of the core circuitry is supplied from VCORE. The performance of the regulators is directly dependent on the performance of VCOREDIG and the bandgap. No external DC loading is allowed on VCOREDIG or REFCORE. VCOREDIG is kept powered as long as there is a valid supply and/or coin cell. The following table captures the main characteristics of the core circuitry. Table 14. Core Circuitry Main Characteristics REFERENCE PARAMETER TYPICAL Output voltage in ON mode VCOREDIG (Digital core supply) (40), (41) Output voltage in OFF mode(41) Bypass Capacitor REFCORE (Bandgap/Regulator Reference) 1.2 V 2.2 µF typ (0.65 µF derated) Output voltage in ON mode (40), (41) VCORE (Analog core supply) 1.5 V Output voltage in OFF mode(41) 2.775 V 0V Bypass Capacitor 2.2 µF typ (0.65 µF derated) Output voltage(40) 1.20 V Bypass Capacitor 100 nF typ (65 nF derated) Notes 40. 3.0 V < BP < 4.65 V, no external loading on VCOREDIG, VCORE, or REFCORE. Extended operation down to UVDET with VCORE down to UVDET, but no system malfunction. 41. The core is in On mode when charging, or when the state machine of the IC is not in the Off mode, nor in the power cut mode. Otherwise, the core is in Off mode. The transient load and line response are specified with the waveforms as depicted in Figure 9. Note that where the transient load response refers to the overshoot only, so excluding the DC shift itself, the transient line response refers to the sum of both overshoot and DC shift. This is also valid for the mode transition response. 13892 48 Analog Integrated Circuit Device Data Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. FUNCTIONAL DEVICE OPERATION Imax Vnom + 0.8V Iload Vin 0mA Vnom + 0.3V 1us 1us 10us Iload for Transient Load Response IL = 0mA 10us Vin for Transient Line Response IL = Imax Overshoot Vout Overshoot Vout for Transient Load Response Active Mode Low Power Mode Active Mode Overshoot Vout Overshoot IL < ILmax Mode Transition Time IL < ILmaxlp IL < ILmax Vout for Mode Transition Response (VGEN1/2/3, VVIDEO, VCAM, VSD) Figure 9. Transient Response Waveforms VAUDIO AND VVIDEO SUPPLIES The primary applications of these power supplies are for audio, and TV-DAC. These supplies could also be used for other peripherals if one of these functions is not required. Low Power modes and programmable Standby options can be used to optimize power efficiency during deep sleep modes. VAUDIO is implemented with an integrated PMOS pass FET and has a dedicated input supply pin VINAUDIO. The nominal output voltage (VNOM as referred in Table Table 4) of VVIDEO can go from 2.5 to 2.7 V on 0.1 V steps, it also can be programmed to be 2.775 V. Its output current depends on the external pass device. The nominal output voltage (VNOM as referred in Table Table 4) of VAUDIO can be programmed to be 2.3, 2.5, 2.775 or 3.0 V. LOW VOLTAGE SUPPLIES VDIG and VPLL are provided for isolated biasing of the Baseband system PLLs for clock generation in support of protocol and peripheral needs. Depending on the lineup and power requirements, these supplies may be considered for sharing with other loads, but noise injection must be avoided and filtering added if necessary, to ensure suitable PLL performance. The VDIG and VPLL regulators have a dedicated input supply pin: VINDIG for the VDIG regulator and VINPLL for the VPLL regulator. VINDIG and VINPLL can be connected to either BP or a 1.8 V switched mode power supply rail such as from SW4 for the two lower set points of each regulator (1.2 V and 1.25 V output for VPLL and 1.05 and 1.25 V output for VDIG). In addition, when the two upper set points are used (1.50 V and 1.8 V output for VPLL and 1.65 V and 1.8 V for VDIG) can be connected to either BP or a 2.2 V nominal external switched mode power supply rail to improve power dissipation. The nominal programmable output voltage of VPLL (VNOM as referred in Table 4) could be 1.2, 1.25, 1.50 or 1.8 V, while VDIG can be configured to 1.05, 1.25, 1.65 and 1.8 V. PERIPHERAL INTERFACING IC interfaces in the lineups generally fall in two categories: low voltage IO primarily associated with the AP IC and certain 13892 Analog Integrated Circuit Device Data Freescale Semiconductor 49 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. FUNCTIONAL DEVICE OPERATION peripherals at the SPIVCC level (powered from SW4), and a higher voltage interface level associated with other peripherals not compatible with the 1.8 V SPIVCC. VIOHI is provided at a fixed nominal output voltage 2.775 V level (VNOM as referred in Table 4) for such interfaces, and may also be applied to other system needs within the guidelines of the regulator specifications. The input VINIOHI is not only used by the VIOHI regulator, but also by other blocks. Therefore it should always be connected to BP, even if the VIOHI regulator is not used by the system. VIOHI has an internal PMOS pass FET which will support loads up to 100 mA. CAMERA The camera module is supplied by the regulator VCAM. This allows for powering the entire module independent of the rest of other parts of the system, as well as to select from a number of VCAM output levels for camera vendor flexibility. In applications with a dual camera, it is anticipated that only one of the two cameras is active at a time, allowing the VCAM supply to be shared between them. VCAM has an internal PMOS pass FET, which will support up to 2Mpixel Camera modules (<65 mA). To support higher resolution cameras, an external PNP is provided. The external PNP configuration is offered to avoid excess on-chip power dissipation at high loads and large differential between BP and output settings. For lower current requirements, an integrated PMOS pass FET is included. The input pin for the integrated PMOS option is shared with the base current drive pin for the PNP option. The nominal output voltage of this regulator (VNOM as referred in Table 4) is SPI configurable, and can be 2.5, 2.6, 2.75, or 3.0 V. The output current when working with the internal pass FET is 65 mA, and could be up to 250 mA when working with an external PNP. MULTI-MEDIA CARD SUPPLY This supply domain is generally intended for user accessible multi-media cards such as Micro-SD (TransFlash), RS-MMC, and the like. An external PNP is utilized for this LDO to avoid excess on-chip power dissipation at high loads and large differential between BP and output settings. The external PNP device is always connected to the BP line in the application. VSD may also be applied to other system needs within the guidelines of the regulator specifications. At the 1.8 V set point, the VSD regulator can be powered from and external buck switcher (2.2 V typ) for an efficiency advantage and reduced power dissipation in the pass devices. This regulator can be configured for nominal output voltages (VNOM as referred in Table 4) of 1.8, 2.00, 2.60, 2.70, 2.8, 2.9, 3.00, and 3.15 V. All of these configurations can draw a current of 250 mA. USB SUPPLY The VUSB regulator is used to supply a nominal output voltage (VNOM as referred in Table 4) of 3.3 V to the external USB PHY. The UVBUS line of the USB interface is supplied by the host, in the case of host mode operation, or by the integrated VBUS generation circuit, in the case of USB OTG mode operation. The VBUS circuit is powered from the SWBST boost supply, to ensure OTG current sourcing compliance through the normal discharge range of the main battery. The VUSB regulator can be supplied from the VBUS wire of the USB cable (power rail of the USB cable), when supplied by a host, in the case of host mode operation, or by the SWBST voltage for OTG mode operation. The SWBST voltage supplies the VUSB regulator from the VINUSB pin, which is internally connected to SWBST, and also to the UVBUS pin to drive the VBUS on this mode (as long as VBUSEN pin is logic high =1). When UVBUS/CHARGRAW is detected in host mode, the USB regulators, VUSB and VUSB2 should be automatically enabled. It will be up to the processor to determine what type of device is connected, either a USB host or a wall charger, and take appropriate action. The VUSB and VUSB2 regulators can be enabled independent of OTG or Host Mode by setting the individual SPI enable bits, VUSBEN and VUSB2EN respectively. Since UVBUS can be shared with the charger input at the board level, the UVBUS node must be able to withstand the same high voltages as the charger. In over-voltage conditions, the VUSB regulator is disabled. USB supplies characteristics are shown in Tables 4 and 5. Note: When VUSBIN =1, UVBUS will be connected via internal switches to VINUSB and incur some current drain on that pin, as much as 270 μA maximum, so care must be taken to disable this path and set this SPI bit (VUSBIN) to 0 to minimize current drain, even if SWBST and/or VUSB are disabled. VUSB REGULATOR VUSB2 is implemented with an integrated PMOS pass FET and has a dedicated supply pin VINUSB2. The pin VINUSB2 should always be connected to BP, even in case the regulators are not used by the application. The nominal output voltage of this regulator (VNOM as referred in Table 4) can be programmed to be 2.400, 2.600, 2.700, and 2.775 V with a load capability of 50 mA. GEN1, GEN2 AND GEN3 REGULATORS General purpose LDOs VGEN1, VGEN2, and VGEN3 are provided for expansion of the power tree, to support peripheral devices which could include WLAN, BT, GPS, or other functional modules. All the regulators include programmable set points for system flexibility. At the 1.2 V and 1.5 V set points, both VGEN1 and VGEN2 can be powered from an external buck switcher (2.2 V typ), for an 13892 50 Analog Integrated Circuit Device Data Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. FUNCTIONAL DEVICE OPERATION efficiency advantage and reduced power dissipation in the pass devices. VGEN1 nominal output voltage (VNOM as referred in Table 4) can be 1.20, 1.50, 2.7775, or 3.15 V, and has a capability of 200 mA. VGEN2 is configurable for 1.20, 1.50, 1.60, 1.80, 2.70, 2.80, 3.00, and 3.15 V, and can supply up to 350 mA. control. Key use cases for GPO outputs include battery pack thermistor biasing and enabling of peripheral devices, such as light sensor(s), camera flash, or even supplemental regulators. SPI enabling can be used for coordinating GPOs with ADC conversions for consumption efficiency and desired settling characteristics. VGEN3 has an internal PMOS pass FET, which will support loads up to 50 mA. For higher current capability, drive for an external PNP is provided. The external PNP configuration is offered to avoid excess on-chip power dissipation at high loads and large differential between BP and output settings. The input pin for the integrated PMOS option is shared with the base current drive pin for the PNP option. This regulator is configurable for nominal output voltages (VNOM as referred in Table 4) of 1.80 and 2.90 V with a capability of 200 mA when working with an external PNP. The GPO1 output is intended to be used for battery thermistor biasing. For accurate thermistor reading by the ADC, the output resistance of the GPO1 driver is of importance. Finally, a muxing option is included to allow GPO4 to be configured for a muxed connection into Channel 7 of the GP ADC. As an example for a dual light sensor application, Channel 7 can be toggled between the ADIN7 (ADINSEL7=00) and GPO4 (ADINSEL7=11), for convenient connectivity and monitoring of two sensors. The GPO4 pin is configured for ADC input mode by default (GPO4ADIN=1), so that the GPO driver stage is at high impedance at power up. The GPO4 pin can be configured by software for GPO operation with GPO4ADIN=0. GENERAL PURPOSE OUTPUTS The GPO drivers included can provide useful system level signaling with SPI enabling and programmable Standby Table 15. 13892 General Purpose Outputs Electrical Characteristics PIN NAME GPO1 GPO2, GPO3, GPO4 PARAMETER LOAD CONDITION MIN MAX UNIT Output Low -400 µA 0 0.2 V Output High 400 µA VCORE-0.2 VCORE V Output Low -100 µA 0 0.2 V Output High 100 µA VIOHI-0.2 VIOHI V PROTECTION FUNCTIONS SHORT-CIRCUIT PROTECTION The higher current LDOs, and those most accessible in product applications, include short-circuit detection and protection (VVIDEO, VAUDIO, VCAM, VSD, VGEN1, VGEN2, and VGEN3). The short-circuit protection (SCP) system includes debounced fault condition detection, regulator shutdown, and processor interrupt generation to contain failures and minimize chance of product damage. If a short-circuit condition is detected, the LDO will be disabled by resetting its VxEN bit while at the same time an interrupt SCPI will be generated to flag the fault to the system processor. BATTERY MANAGEMENT The 13892 supports single path and serial path charging. In single path charging, the device is always supplied from the battery and therefore always has to be present and valid. In a serial path charging scheme, the device may operate directly from the charger while the battery is removed or deeply discharged. The charger supports charging from a USB host or a wall charger. The charger interface provides linear operation via an integrated DAC at programmable current levels. It incorporates a standalone trickle charge mode, in case of a dead battery with dual LED indicator driver. Over-voltage, short-circuit, and under-voltage detectors are included as well as charger detection and removal. The charger includes the necessary circuitry to allow for USB charging and for reverse supply to an external accessory. The battery management system also provides a battery presence detector, and an A to D converter that serves for measuring the charge current, battery and other supply voltages, as well as for measuring the battery thermistor and die temperature. Finally, a system is included for monitoring the current drawn from, or charged into the main battery for support of a Coulomb Counter function. 13892 Analog Integrated Circuit Device Data Freescale Semiconductor 51 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. FUNCTIONAL DEVICE OPERATION To Application B+ To/From Charger Connector 10u M2 M3 Charge LED Indicator R1 20 mΩ 0.1 Ω R2 Connect for devices with single charger input on USB connector VBUS CHRGSE1B CHRGCTRL1 CHRGCTRL2 CHRGISNS BPSNS BP BATTFET BATTISNS BATTISNSCC BATT FET Driver ADIN5 Thermistor Check SE1 Charger Control Logic Charger Presence Detection Charger Overvoltage Protection Power Limiter Charge Path Voltage Regulation Charge Path Current Regulation Trickle Charge To ADC + - VBUS Overvoltage Protection To/From USB Blocks CHRGRAW 10u + - CHRGLED Battery NTC 10K M1 To Core Supply and Control 10K 2.2u GPO1 VCORE To ADC and ACC Figure 10. 13892 Charge Path Transistors M1 and M2 control the charge current and INTERNAL TRICKLE CHARGE CURRENT SOURCE provide voltage regulation. The latter is used as the top off An internal current source between BP and BATTISNS change voltage, and as the regulated supply voltage to the provides small currents to the battery, in case of trickle application, in case of dead battery operation. In order to charging a dead battery. support dead battery operation, a so called “serial path” charging configuration including M3 needs to be used. Then COMPARATORS in case of a dead battery, the transistor M3 is made nonThe charger detection is based on three comparators. The conducting and the internal trickle charge current charges the “charger valid”, which monitors CHRGRAW, the “charger battery. If the battery is sufficiently charged, the transistor M3 presence”, which monitors the voltage drop between is made conducting which connects the battery to the CHRGRAW and BPSNS, and the “CHGCURR” comparator, application, just like during normal operation without a which monitors the current through the sense resistor charger. In so called single path charging, M3 is replaced by connected between CHRGISNS and BPSNS. A charger a short and the pin BATTFET must be floating. Dead battery insertion is detected, based on the charger presence operation is not supported in that case. Transistors M1 and comparator and the “charger valid” comparator both going M2 become non-conducting if the charger voltage is too high. high. For all but the lowest current setting, a charger removal The UVBUS pin must be shorted to CHRGRAW in cases is detected, based on both the “charger presence” where the charger is being supplied from the USB cable. A comparator going low and the charger current falling below current can be supplied from the battery to an accessory with CHGCURR. In addition, for the lowest current settings, or if all transistors M1, M2, and M3 conducting by enabling the not charging, the “charger valid” comparator going low is an reverse supply mode. An unregulated wall charger additional cause for charger removal detection. configuration can be built, in which case CHRGSE1B must be In addition to the aforementioned comparators, three more pulled low. The battery current monitoring resistor R1 and the comparators play a role in battery charging. These charge LED indicator are optional. comparators are “BATTMIN”, which monitors BATT for the safe charging battery voltage, “BATTON”, which monitors CHARGE PATH REGULATOR BATT for the safe operating battery voltage, and M1 and M2 are permanently used as a combined pass “BATTCYCL”, which monitors BPSNS for the constant device for a super regulator, with a programmable output current to constant voltage transition. The BATTMIN and voltage and programmable current limit. BATTON comparators have a normal and a long (slow) The voltage loop consists of M1, M2, and an amplifier with debounced output. The slow output is used in some places in voltage feedback taken from the BPSNS pin. The value of the the charger flow to provide enough time to the battery sense resistor is of no influence on the output voltage. The protection circuit to reconnect the battery cell. output voltage is programmable by SPI from 3.8 to 4.45 V. The current loop is composed of the M1 and M2 as control BATTERY THERMISTOR CHECK CIRCUITRY elements, the external sense resistor, a programmable A battery pack may be equipped with a thermistor, which current limit, and an amplifier. The control loop will regulate value decreases over temperature. the voltage drop over the external resistor. The charge current is programmable by SPI from 0 to 1600 mA. 13892 52 Analog Integrated Circuit Device Data Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. FUNCTIONAL DEVICE OPERATION By default, the battery thermistor value is taken into account for charging the battery CHARGE LED INDICATOR Since normal LED control via the SPI bus is not always possible in the standalone operation, a current sink is provided at the CHRGLED pin. The driver at CHRGLED serves as the trickle (sign of life) LED and will be activated when standalone charging is started, and will remain on also when the device is powered on, until the charger is programmed by SPI. MODES OF OPERATION REVERSE SUPPLY MODE The battery voltage can be applied to an external accessory via the charge path. The path is only established if the normal charge path is disabled. The turn on of M1 and M2 is intentionally slow. The current through the accessory supply path is monitored via the charge path sense resistor R2. It can be read out via the ADC. The accessory supply path is disabled and an interrupt CHGSHORTI is generated when the slow threshold or the fast threshold is crossed. The reverse path is disabled when a current reversal occurs, and an interrupt CHREVI is generated. This function operates up to 40°C. STANDALONE CHARGING A standalone charge mode of operation is provided to minimize software interaction. It also allows that a completely discharged battery can be revived without processor control. This is especially important when charging from a USB host or when the optional transistor M3 is not placed. SOFTWARE CONTROLLED CHARGING The charger can also be operated under software control. In this mode, full control of the charger settings is assumed by software; the state machine will no longer determine the mode of charging. FACTORY MODE In factory mode, power is provided to the application with no battery present. It is not a situation which should occur in the field. The factory mode is differentiated from a USB Host by, in addition to a valid VBUS, a UID being pulled high to VBUS level during the attach, See Connectivity (USB Interface) on page 56. Notes: When using the battery charger as the only source of power, as in a battery-less application, the following precautions should be observed: It is still necessary to connect ADIN5 to either VCOREDIG or a midpoint of a divider from GPIO1 to ground since the battery charger will still interpret this voltage as the battery pack thermistor by default. Very careful budgeting of the total current consumption and voltage standoff from CHRGRAW to BPSNS must be made, since the power limiter is operational by default, and a battery less system won't have a source of current if the power dissipation limit is reached. If operating from a USB host the unit load limit (100 mA max.) must still be observed. If operating from a “wall charger”, and if there is no battery, there is an period of approximately 85 ms after RESETB is released, but before the current limit is set to a nominal 560 mA. If the total current demand is greater than this limit, the voltage may collapse and RESETB may pulse a few times (depending in part in the system load and dependence on RESETB.) Therefore, at the end of this time, RESETB may or may not be active. It may be necessary to use one of the other turn on events (such as PWRONx) to turn the 13892 back on. PROTECTION FUNCTIONS OVER-VOLTAGE PROTECTION In order to protect the application, the voltage at the CHRGRAW pin is monitored. When crossing the threshold (16 V high to low and low to high), the charge path regulator will be turned off by opening the mosfets connected to pins CHRGCTRL1 and CHRGCTRL2. An interrupt CHGFAULTI is generated with the associated CHGFAULTM mask bit. In order to ensure immediate protection, the control of M1, M2, and M3 occurs in real time. The UVBUS pin is also protected against over-voltages. This will occur at much lower levels then for CHRGRAW. When a VBUS over-voltage is detected the internal circuitry of the USB block is disconnected. An USBOVI is generated in this case. When the maximum voltage of the IC is exceeded, damage will occur to the IC, and the state of the mosfets connected to pins CHRGCTRL1 and CHRGCTRL2 cannot be guaranteed. If one wants to protect against these failure conditions, additional protection will be required. The same is valid for charger polarity inversion protection. USB LOW POWER BOOT USB low power boot allows the application to boot with a dead battery within the 100 mA USB budget, until the processor has negotiated for the full current capability. This mode expedites the charging of the dead battery and allows the software to bring up the LCD display screen with the message “Charging battery”. OVER-POWER DISSIPATION PROTECTION Since the charge path operates in a linear fashion, the dissipation can be significant and care must be taken to ensure that the external pass FETs M1 and M2 are not over dissipating when charging. By default, the charge system will protect against this by a built in power limitation circuit.This circuit will monitor the voltage drop between CHRGRAW and 13892 Analog Integrated Circuit Device Data Freescale Semiconductor 53 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. FUNCTIONAL DEVICE OPERATION CHRGISNS, and the current through the external sense resistor connected between CHRGISNS and BPSNS. When required, a duty cycle is applied to the FETs connected on CHRGCTRL1 and CHRGCTRL2, and thus the charge current, in order to stay within the power budget. At the same time the FET connected to BATTFET pin is forced to conduct to keep the application powered. In case of excessive supply conditions, the power limiter minimum duty cycle may not be sufficiently small to maintain the actual power dissipation within budget. In that case, the charge path will be disabled and the CHGFAULTI interrupt generated. The power budget can be programmed by the SPI through the PLIM[1:0] bits, which establishes a power limit from 600 to 1200 mW in 200 mV steps. The power dissipation limiter can be disabled by setting the PLIMDIS bit. In this case, it is advised to use close software control to estimate the dissipated power in the external pass FETs. The power limiter is automatically disabled in serial path factory mode and in reverse mode. Since a charger attachment can be a Turn On event when a product is initially in the Off state, any nondefault settings that are intended for PLIM[1:0] and PLIMDIS should be programmed early in the configuration sequence to ensure proper supply conditions adapted to the application. To avoid any false detection during power up, the power limiter output is blanked at the start of the charge cycle. As a safety precaution, the power dissipation is monitored and the desired duty cycle is estimated. When this estimated duty cycle falls below the power limiter minimum duty cycle, the charger circuit will be disabled. ADC SUBSYSTEM The ADC core is a 10 bit converter. The ADC core and logic run on 2/3 of the switcher PLL generated frequency, so approximately 2.0 MHz. If an ADC conversion is requested while the PLL is not active, it will be automatically enabled by the ADC. A 32.768 kHz equivalent time base is derived from the 2.0 MHz clock to time ADC events. The ADC is supplied from VCORE. The ADC core has an integrated auto calibration circuit which reduces the offset and gain errors. The switcher PLL is programmable, so when the switcher frequency is changed, the frequency applied to the ADC converter will change accordingly. Although the conversion time is inversely proportional to the PLLX[2:0] setting, this will not influence the ADC performance. The locally derived 32.768 kHz will remain constant in order to not influence the different timings depending on this time base. The ADC Subsystem has 8 channels: Channel 0 Battery Voltage: The battery voltage is read at the BATT pin at channel 0. Channel 1 Battery Current: The current flowing out of and into the battery can be read via the ADC by monitoring the voltage drop over the sense resistor between BATT and BATTISNSCC. Channel 2 Application Supply: The application supply voltage is read at the BP pin at channel 2. Channel 3 Charger Voltage: The charger voltage is measured at the CHRGRAW pin at channel 3. Channel 4 Charger Current: The charge current is read by monitoring the voltage drop over the charge current sense resistor. This resistor is connected between CHRGISNS and BPSNS. Channel 5 ADIN5, Battery Thermistor and Battery Detect: On channel 5, ADIN5 may be used as a general purpose input, but in a typical application, ADIN5 is used to read out the battery pack thermistor. The thermistor will have to be biased with an external pull-up to a voltage rail greater than the ADC input range. In order to save current when the thermistor reading is not required, it can be biased from one of the general purpose IOs such as GPO1. A resistor divider network should assure the resulting voltage falls within the ADC input range, especially when the thermistor check function is used. When the application is on and supplied by the charger, a battery removal can be detected by a battery thermistor presence check. When the thermistor terminal becomes high-impedance, the battery is considered being removed. This detection function is available at the ADIN5 input. Channel 6 ADIN6 and Coin Cell Voltage: On channel 6, ADIN6 may be used as a general purpose unscaled input but in a typical application, the PA thermistor is connected here. In addition, on channel 6, the voltage of the coin cell connected to the LICELL pin can be read. Channel 7 ADIN7 and ADIN7B, UID and Die Temperature: On channel 7, ADIN7 may be used as a general purpose input. In a typical application, an ambient light sensor is connected here. A second general purpose input ADIN7B is available. In the application, a second ambient light sensor is supposed to be connected here. In addition, on channel 7, the voltage of the USB ID line connected to the UID pin and the die temperature can be read. COULOMB COUNTER As discussed previously, the current into and from the battery can be read out through the general purpose ADC as 13892 54 Analog Integrated Circuit Device Data Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. FUNCTIONAL DEVICE OPERATION a voltage drop over the R1 sense resistor. Together with the battery voltage reading the battery capacity can be estimated. A more accurate battery capacity estimation can be obtained by using the integrated Coulomb Counter. From Charger Path The Coulomb Counter (or CC) monitors the current flowing in/out of the battery by integrating the voltage drop across the battery current sense resistor R1, followed by an A to D conversion. The result of the A to D conversion is used to increase/decrease the contents of a counter that can be read out by software. SPI BITS RESETB Battery Current BATTISNSCC CFP R1 20mOhm CF 10uF Coulomb Counter CCOUT CFM BATT RTC References Figure 11. 13892 Coulomb Counter Block Diagram. PROTECTIONS AGAINST FAULT CONDITIONS Touch Screen Interface Counter roll over: CCOUT[15:0]=8000HEX The touch screen interface provides all circuitry required for the readout of a 4-wire resistive touch screen. The touch screen X plate is connected to TSX1 and TSX2, while the Y plate is connected to TSY1 and TSY2. A local supply TSREF will serve as a reference. Several readout possibilities are offered. To perform touch screen readings, the processor will have to select the touch screen mode, program the delay between the conversions via the ATO and ATOX settings, trigger the ADC via one of the trigger sources, wait for an interrupt indicating the conversion is done, and then read out the data. In order to reduce the interrupt rate and to allow for easier noise rejection, the touch screen readings are repeated in the readout sequence. The reference for the touch screen is This occurs when the contents of CCOUT[15:0] go from a negative to a positive value or vice versa. Software may interpret incorrectly the battery charge by this change in polarity. When CCOUT[15:0] becomes equal to 8000HEX the CCFAULT is set. The counter stays counting so its contents can still be exploited. Battery removal: ‘BP<UVDET’ When removing and replacing the battery, the contents of the counter are no longer valid. A battery removal is characterized by the input supply to the IC dropping below the under-voltage detect threshold, so BP<UVDET. To avoid false detection due to short power cuts, the CCFAULT is set only after a long debounce of 1.0 second. Battery removal when charging: BATTDETBS=1 The battery removal detection as described previously is not applicable when charging, since in this case, the charger will continue to supply the application and the BP will not drop below UVDET. To still detect a battery removal, one can use the battery detect function, as described in ADC Subsystem on page 54. When the sense bit BATTDETBS becomes a 1, the CCFAULT is set only after a long debounce of 1.0 second. TSREF and is powered from VCORE. In touch screen operation, TSREF is a dedicated regulator that is to say, no other loads than the touch screen should be connected here. Table 16. 13892 Touch Screen ADC Readings ADC CONVERSION SIGNALS SAMPLED 0 X position 1 X position 2 Dummy 13892 Analog Integrated Circuit Device Data Freescale Semiconductor 55 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. FUNCTIONAL DEVICE OPERATION Table 16. 13892 Touch Screen ADC Readings ADC CONVERSION SIGNALS SAMPLED 3 Y position 4 Y position 5 Dummy 6 Contact resistance 7 Contact resistance The dummy conversion inserted between the different readings is to allow the references in the system to be prebiased for the change in touch screen plate polarity and will read out as ‘0’. MODES OF OPERATION In inactive mode, the inputs TSX1, TSX2, TSY1, and TSY2 can be used as general purpose inputs. They are respectively mapped on ADC channels 4, 5, 6, and 7. In interrupt mode, a voltage is applied to the X-plate (TSX2) via a weak current source to VCORE, while the Yplate is connected to ground (TSY1). When the two plates make contact both will be at a low potential. This will generate a pen interrupt TSI to the processor. This detection does not make use of the ADC core or the TSREF regulator, so both can remain disabled. In touch screen mode, the XY coordinate pairs and the contact resistance are read. The X-coordinate is determined by applying TSREF over the TSX1 and TSX2 pins while performing a high-impedance reading on the Y-plate through TSY1. The Y-coordinate is determined by applying TSREF between TSY1 and TSY2 while reading the TSX1 pin. The contact resistance is measured by applying a known current into the TSY1 terminal of the touch screen and through the terminal TSX2, which is grounded. The voltage difference between the two remaining terminals TSY2 and TSX1 is measured by the ADC, and equals the voltage across the contact resistance. Measuring the contact resistance helps in determining if the touch screen is touched with a finger or stylus. LED DRIVERS FOR LIGHTING SYSTEM BACKLIGHT LED DRIVERS The lighting system includes backlight drivers for main display, auxiliary display, and keypad. Three additional drivers are provided for RGB or general purpose signaling. Ramp up and ramp down patterns are implemented in hardware to reduce the burden of real time software control via the SPI, to orchestrate dimming and soft start lighting effects. The current level is programmable in a low range mode and in a high range mode from 0 to 21 mA and from 0 to 42 mA respectively. This facilitates the current setting, in case two or more serial LED strings are connected in parallel to the same driver, or when using super bright LEDs. An external boost is required to drive the backlight LEDs. A maximum of only two backlight drivers can be activated at the same time, for instance the main display plus keypad. If all three backlight drivers are enabled meaning none of the duty cycles equals 0/32, then none of the drivers will be activated. SIGNALING LED DRIVERS The signaling LED drivers LEDR, LEDG, and LEDB are independent current sink channels. Each driver channel features programmable current levels from 0 to 21 mA as well as programmable PWM duty cycle settings. By a combination of level and PWM settings, each channel provides flexible LED intensity control. By driving LEDs of different colors, color mixing can be achieved. Blue LEDs or bright green LEDs require more headroom than red and normal green signal LEDs. In the application, a 5.0 V or equivalent supply rail is therefore required. This is provided by the integrated boost converter SWBST. As with the backlight driver channels, the signaling LED drivers include ramp up and ramp down patterns are implemented in hardware. In addition, programmable blink rates are provided. Blinking is obtained by lowering the PWM repetition rate of each of the drivers, while the on period is determined by the duty cycle setting. To avoid high frequency spur coupling in the application, the switching edges of the output drivers are softened.” CONNECTIVITY (USB INTERFACE) The 13892 contains the regulators required to supply the PHY contained in the i.MX51, i.MX37, i.MX35, and i.MX27 processors. The regulators used to power the external PHY in the i.MX51 and i.MX37 are VUSB, VUSB2, and VUSB for the i.MX35 and i.MX27 processors. The IC also provides the 5.0 V supply for USB OTG operation. The USB interface may be used for portable product battery charging. Finally included are comparators/detectors for VBUS and ID detection. VBUS is the power rail of the USB cable that must be connected to the UVBUS pin. The USB interface is illustrated in Figure 12. 13892 56 Analog Integrated Circuit Device Data Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. FUNCTIONAL DEVICE OPERATION USB UID Comparators, & Detectors To Mini-USB Connector UVBUS SPI OTG 5V VBUSEN VUSB Regulator VUSB VINUSB 3.3V USB Analog supply SWBST (5V boosted supply) VBUS Generation Batt Charger System VINUSB2 VUSB2 Regulator VUSB2 BP 2.6V USB Analog supply Figure 12. 13892 USB Interface Block Diagram OTG MODE (ON THE GO) The ID detector is primarily used to determine if a mini-A or mini-B style plug has been inserted into a mini-AB style receptacle on the application. However, it also supports two additional modes which are outside of the USB standards: a factory mode, and a non-USB accessory mode. The state of the ID detection can be read via the SPI to poll dedicated sense bits for a floating, grounded, or factory mode condition on the UID pin. There are also dedicated maskable interrupts for each UID condition as well. Since portable applications have limited capabilities, this supplement to the USB2.0 specification was developed in order to allow a portable device to take the role of a USB host. In this mode of operation, SWBST is internally switched to Parameter supply the VUSB regulator, and SWBST will drive VBUS from the VINUSB pin as long as VBUSEN pin is a logic high = 1. According to the USB2.0 specification, the USB host is the device where the USB Host Controller is installed, through which it interacts with the USB devices. The USB host is responsible for: • Detecting the attachment and removal of USB devices. • Managing control flow between the host and USB devices. • Managing data flow between the host and USB devices. • Collecting status and activity statistics. • Providing power to attached USB devices. When working in host mode, VUSB is supplied from the VBUS wire of the USB cable (VBUS). Condition Min VBUS input impedance As A_device 40 UID 220K Pull-up(42) IDPUCNTRL=0, Resistor to VCORE 132 UID Pull-up(42) IDPUCNTRL=1, Current source from VCORE UID Parallel Pull-up(42) ID100KPU=1, Resistor to VCORE Typ Max Units 100 KΩ 220 308 KΩ 4.75 5 5.25 uA 60 100 140 KΩ Notes 42. Note that the UID Pull-ups are not mutually exclusive of each other, they are independently controlled by their enable bits and thus multiple pull-ups can be engaged simultaneously. 13892 Analog Integrated Circuit Device Data Freescale Semiconductor 57 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. FUNCTIONAL DEVICE OPERATION POWER CONTROL LOGIC (STATE MACHINE) Figure 13 shows the flow of the power control state machine. This diagram serves as the basis for the description of Operational Modes. The power control system interfaces with the processor via different IO signals and the SPI bus. It also uses on chip signals and detector outputs. From Any Mode: Loss of Power with PCEN=0, Thermal Protection Trip, or System Reset PCT[7:0] Expired Off Unqual’d Turn On WDI Low, WDIRESET=0 Unqual’d Turn On WDI Low, WDIRESET=1 and PCMAXCNT is exceeded Turn On Event Start Up Modes Warm Start Reset Timer Expired Reset Timer Expired Watchdog Cold Start WDI Low, WDIRESET=1 and PCMAXCNT not exceeded Watchdog Timer Expired On Turn On Event (Warm Boot) Turn On Event (Warm Start) Processor Request for User Off: USEROFFSPI=1 Low Power Off Modes User Off Warm Start Enabled User Off Wait WARMEN=1 From Any Mode: Loss of Power with Power Cuts enabled (PCEN=1) and PCMAXCNT not exceeded Warm Start Not Enabled Memory Hold PCUT Timer PCT[7:0] Expired PCUTEXPB cleared to 0 WARMEN=0 Internal MemHold Power Cut Application of Power before PCUT Timer PCT[7:0] expiration (PCEN=1 and PCMAXCNT not exceeded) Legend and Notes (refer to text for additional details) Blue Box = Steady State, no specific timer is running Green Circle = Transitional State, a specific timer is running, see text Dashed Boxes = Grouping of Modes for clarification WDI has influence only in the ‘On’ state Complete loss of BP and coin cell power is not represented in state machine Figure 13. Power Control Logic (State Machine) 13892 58 Analog Integrated Circuit Device Data Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES OPERATIONAL MODES The following are text descriptions of the power states of the system with additional details of the state machine to complement Figure 13. Note that SPI control is only possible in the Watchdog, On, and User Off Wait states, and that the interrupt line INT is kept low in all states except for Watchdog and On. OFF If the supply at BP is above the UVDET threshold, only the IC core circuitry at VCOREDIG and the RTC module are powered. All other supplies are inactive. To exit the Off mode, a valid turn on event is required. No specific timer is running in this mode. If the supply at BP is below the UVDET threshold, no turn on events are accepted. If a valid coincell is present, the core gets its power from LICELL. The only active circuitry is the RTC module, and the BP greater than UVDET detection. COLD START This is entered upon a Turn On event from Off, Warm Boot, successful PCUT, or Silent System Restart. The first 8.0 ms are used for initialization which includes bias generation, PUMS / configuration latching, and qualification of the input supply level BP. The switchers and regulators are then powered up sequentially to limit the inrush current. The reset signals RESETB and RESETBMCU are kept low. The Reset timer starts running when entering Cold Start. The input control pins WDI and STANDBYx are ignored. WATCHDOG The system is fully powered and under SPI control. RESETB and RESETBMCU are high. The Watchdog timer starts running when entering the Watchdog state. When expired, the system transitions to the On state, where WDI will be checked and monitored. The input control pins WDI and STANDBYx are ignored while in the Watchdog state. ON The system is fully powered and under SPI control. RESETB and RESETBMCU are high. The WDI pin must be high to stay in this mode. USER OFF WAIT The system is fully powered and under SPI control. The WDI pin no longer has control over the part. The Wait mode is entered by a processor request for User Off. The Wait timer starts running when entering User Off Wait mode. This leaves the processor time to suspend or terminate its tasks. MEMORY HOLD AND USER OFF (LOW POWER OFF STATES) As noted in the User Off Wait description, the system is directed into low power Off states, based on a SPI command in response to an intentional Turn Off by the end user. The only exit then will be a Turn On event. To an end user, the Memory Hold and User Off states look like the product has been shut down completely. However, a faster startup is facilitated by maintaining external memory in self-refresh mode (Memory Hold and User Off mode), as well as powering portions of the processor core for state retention (User Off only). MEMORY HOLD RESETB and RESETBMCU are low, and both CLK32K and CLK32KMCU are disabled (CLK32KMCU active if DRM is set). Upon a Turn On event, the Cold Start state is entered, the default power up values are loaded, and the MEMHLDI interrupt bit is set. A Cold Start out of the Memory Hold state will result in shorter boot times compared to starting out of the Off state, since software does not have to be loaded and expanded from flash. The startup out of Memory Hold is also referred to as Warm Boot. No specific timer is running in this mode. USER OFF RESETB is low and RESETBMCU is kept high. The 32 kHz peripheral clock driver CLK32K is disabled; CLK32KMCU (connected to the processor’s CKIL input) is maintained in this mode, if the CLK32KMCUEN and USEROFFCLK bits are both set, or if DRM is set. Any peripheral loading on SW1 and/or SW2 should be isolated from the output node(s) by the PWGT1 switch, which opens in both low power Off modes, due to the RESETB transition. In this way, leakage is minimized from the power domain, maintaining the processor core. Since power is maintained for the core (which is put into its lowest power state), and since MCU RESETBMCU does not trip, the processor’s state may be quickly recovered when exiting USEROFF upon a Turn On event. The CLK32KMCU clock can be used for very low frequency / low power idling of the core(s), minimizing battery drain while allowing a rapid recovery from where the system left off before the USEROFF command. Upon a Turn On event, Warm Start state is entered, and the default power up values are loaded. A Warm Start out of User Off will result in an almost instantaneous startup of the system, since the internal states of the processor were preserved along with external memory. No specific timer is running in this mode. WARM START Entered with a Turn On event from User Off. The first 8.0 ms is used for initialization which includes bias generation, PUMS latching, and qualification of the input supply level BP. The switches and regulators are then powered up sequentially to limit the inrush current. 13892 Analog Integrated Circuit Device Data Freescale Semiconductor 59 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES RESETB is kept low and RESETBMCU is kept high. CLK32KMCU is kept active if CLK32KMCU was set. The reset timer starts running when entering Warm Start. When expired, the Warm Start state is exited for the Watchdog state, a WARMI interrupt is generated, and RESETB will go high. INTERNAL MEMHOLD POWER CUT Power Cut description: When the supply at BP drops below the UVDET threshold due to battery bounce or battery removal, the Internal MemHold Power Cut mode is entered and a Power Cut (PCUT) timer starts running. The backup coin cell will now supply the RTC as well as the on chip memory registers and some other power control related bits. All other supplies will be disabled. Internal MemHold Power Cut: As previously described, a momentary power interruption will put the system into the Internal MemHold Power Cut state if PCUTs are enabled. The backup coin cell will now supply 13892’s core along with the 32 k crystal oscillator, the RTC system and coin cell backed up registers. All regulators and switchers will be shut down to preserve the coin cell and RTC as long as possible. Both RESETB and RESETBMCU are tripped, bringing the entire system down along with the supplies and external clock drivers, so the only recovery out of a Power Cut state is to reestablish power and initiate a Cold Start. POWER SAVING SYSTEM STANDBY A product may be designed to go into DSM after periods of inactivity, such as if a music player completes a play list and no further activity is detected, or if a gaming interface sits idle for an extended period. Two Standby pins are provided for board level control of timing in and out of such deep sleep modes. When a product is in DSM it may be able to reduce the overall platform current by lowering the switcher output voltage, disabling some regulators, or forcing GPOx low. This can be obtained by SPI configuration of the Standby response of the circuits along with control of the Standby pins. To ensure that shared resources are properly powered when required, the system will only be allowed into Standby when both the application processor (which typically controls the STANDBY pin) and peripherals (which typically control the STANDBYSEC pin) allow it—this is referred to as a Standby event. REGULATOR MODE CONTROL The regulators with embedded pass devices (VDIG, VPLL, VIOHI, VUSB, VUSB2, and VAUDIO) operate in two modes: a normal mode, and a low power mode. The transition between both modes occurs automatically, based on the load current. Therefore, no specific control is required to put these regulators in a low power mode (i.e., “On” implies an adaptive mode control” based on load current). Bits are reserved in case the automatic scheme shows to be insufficient. The regulators with external pass devices (VSD, VVIDEO, VGEN1, and VGEN2) can also operate in a normal and low power mode. However, since a load current detection cannot be performed for these regulators, the transition between both modes is not automatic, and is controlled by setting the corresponding mode bits for the operational behavior desired. The regulators VGEN3, and VCAM can be configured for using the internal pass device or external pass device as explained in LDOs on page 48. Therefore, depending on the configuration selected, the automatic low power mode is or is not available. BUCK SWITCHERS Operational modes of the Buck switchers can be controlled by direct SPI programming, altered by the state of the STANDBY pins, by direct state machine influence (i.e., entering Off or low power Off states, for example), or by load current magnitude when so configured. Available modes include PWM with No Pulse Skipping (PWM), PWM with Pulse Skipping (PWMPS), Pulse Frequency Mode (PFM), and Off. The transition between the two modes PWMPS and PFM can occur automatically based on the load current (auto). Therefore, no specific control is required to put the switchers in a low power mode. When the buck switchers are not configured in the auto mode, power savings may be achieved by disabling the switchers when not needed, or running them in PFM mode, if loading conditions are light enough. SW1, SW2, SW3, and SW4 can be configured for mode switching with STANDBY or autonomously, based on load current with adaptive mode control (Auto). Additionally, provisions are made for maintaining PFM operation in USEROFF and MEMHOLD modes, to support state retention for faster startup from the low power Off modes, for Warm Start or Warm Boot. POWER GATING SYSTEM The low power Off states are provided to allow faster system booting from two pseudo Off conditions: Memory Hold, which keeps external memory powered for self refresh, and User Off, which keeps the processor powered up for state retention. For reduced current drain in low power Off states, parts of the system can benefit from power gating, to isolate the minimum essentials for such operational modes. It is also necessary to ensure that the power budget on backed up domains is within the capabilities of switchers in PFM mode. An additional benefit of power gating peripheral loads during system startup is to enable the processor core to complete booting and begin running software before additional supplies or peripheral devices are powered. This allows system software to bring up the additional supplies and close power gating switches in the most optimum order 13892 60 Analog Integrated Circuit Device Data Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES to avoid problems with supply sequencing or transient current surges. The power gating switch drivers and integrated control are included for optimizing the system power tree. The power gate drivers could be used for other general power gating as well. The text herein assumes the standard application of PWGT1 for core supply power gating and PWGT2 for Memory Hold power gating. USER OFF POWER GATING User Off configuration maintains PFM mode switchers on both the processor and external memory power domains. PWGTDRV1 is provided for power gating peripheral loads sharing the processor core supply domain(s) SW1, and/or SW2, and/or SW3. In addition, PWGTDRV2 provides support to power gate peripheral loads on the SW4 supply domain. In a typical application, SW1, SW2, and SW3 will be kept active for the processor modules in state retention, and SW4 will be retained for the external memory in self refresh mode. SW1, SW2, and SW3 power gating FETs drive would typically be connected to PWGTDRV1 (for parallel NMOS switches). The SW4 power gating FET drive would typically be connected to PWGTDRV2. When low power Off mode is activated, the power gate drive circuitry will be disabled, turning off the NMOS power gate switches, to isolate the maintained supply domains from any peripheral loading. MEMORY HOLD POWER GATING As with the User Off power gating strategy described previously, Memory Hold power gating is intended to allow isolation of the SW4 power domain to selected circuitry in low power modes, while cutting off the switcher domain from other peripheral loads. The only difference is that processor supplies SW1, and/or SW2, and/or SW3 are shut down in Memory Hold, so just the external memory is maintained in self-refresh mode. An external NMOS is to be placed between the directconnected memory supply and any peripheral loading. The PWGTDRV2 pin controls the gate of the external NMOS, and is normally pulled up to a charge pumped voltage (~5.0 V). During Memory Hold or User Off, PWGTDRV2 will go low to turn off the NMOS switch and isolate memory on the SW4 power domain. POWER DISSIPATION During operation, the temperature of the die should not exceed the maximum junction temperature. Depending on the operating ambient temperature and the total internal dissipation, this limit can be exceeded. To optimize the thermal management scheme and avoid overheating, the 13892 provides a thermal management system. The thermal protection is based on a circuit with a voltage output that is proportional to the absolute temperature. This voltage can be read out via the ADC for precise temperature readouts (See Functional Device Operation). THERMAL PROTECTION Thermal protection is integrated to power off the 13892 and disable the charger circuitry in case of over dissipation. This thermal protection will act above the maximum junction temperature to avoid any unwanted power downs. The protection is debounced by one period of the 32kHz clock in order to suppress any (thermal) noise. This protection should be considered as a fail-safe mechanism and therefore the application design should be dimensioned such that this protection is not tripped under normal conditions. The temperature thresholds are listed in the last section of Table 4. 13892 Analog Integrated Circuit Device Data Freescale Semiconductor 61 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. TYPICAL APPLICATIONS TYPICAL APPLICATIONS From Extenal Boost Charger/USB Input (Tied to VBUS) Tied to BATTISNSCC R1 20m Main Battery BP M3 R2 100m M2 M1 2.2u SWBST 10u GNDLED LEDR LEDG LEDB GNDBL LEDKP SW3 Tri-Color LED Drive Backlight LED Drive PWR Gate Drive & Chg Pump ADIN5 General Purpose ADC Inputs: i.e., Battery pack thermistor, PA thermistor, Light Sensor, Etc. SW1 1050 mA Buck ADIN6 TSX1 10 Bit GP ADC MUX SW2 800 mA Buck A/D Result TSX2 Touch Screen Interface TSY1 TSY2 A/D Control Touch Screen Interface Trigger Handling TSREF From AP From M3/R1 connection (needs to be separate route from BATTISNS) Die Temp & Thermal Warning Detection ADTRIG SW3 800 mA Buck To Interrupt Section SW4 800 mA Buck BATTISNSCC BATT CFP Coulomb CCOUT Counter CFM SPIVCC SPI Interface + Muxed I2C Optional Interface MOSI MISO GNDSPI SPI 100n SWBST O/P Drive SW4IN SW4OUT GNDSW4 SW4FB DVS1 DVS2 UID O/P Drive SWBST 300 mA Boost Input Pin Bi-directional Pin MC13892 VBUS/ID Detectors SWBSTIN SWBSTOUT SWBSTFB GNDSWBST SPI VUSB Regulator VUSB2 Pass FET PLL VAUDIO Pass FET VVIOHI Pass FET VPLL Pass FET VDIG Pass FET Pass FET 4.7u SW3 Output 2.2u SW4 Output 2.2u BP From AP 4.7u From AP HOLD Switch To GND, Open, VCOREDIG or VCORE 32.768 KHz Crystal On/Off Button 10u 2.2u 2.2u VIINAUDIO VAUDIO BP VINIOHI VIOHI BP 2.2u VINPLL VPLL BP 2.2u VINDIG VDIG BP 2.2u VCAM VGEN1DRV VGEN1 VGEN2 VGEN2DRV VGEN2 2.2u BP 2.2u BP 2.2u BP LICELL VSRTC RESETB CLK32K To/From Peripherals 2.2u BP 2.2u To/From AP Pass FET BP VGEN3 2.2u Best of Supply GNDREG1 GPO Control VSRTC STANDBYSEC INT WDI To/From AP RESETBMCU STANDBY From Docking station PUMS1 PUMS2 MODE XTAL2 18p SWBST Output (Boost) BP BP VGEN1 VGEN3 32 KHz Buffers Core Control Logic, Timers, & Interrupts GNDCTRL GNDRTC XTAL1 GNDSUB8 GNDSUB9 GNDSUB7 GNDSUB4 GNDSUB5 GNDSUB6 Enables & Control 10u GNDREG2 GNDREG3 1.0u To External Camera Flash or Aux Light Sensor To External Audio Enable To Light Sensor Enable To Thermistor Bias 18p Interrupt Inputs 10u VINGEN3DRV CLK32KMCU SPI Result Registers 32 KHz Crystal Osc GNDSUB3 BP 10u VSDDRV VSD Switchers RTC + Calibration 32 KHz Internal Osc Switch PWRON1 PWRON2 PWRON3 LCELL Li Cell Charger GNDSUB1 GNDSUB2 Control Logic Monitor Timer BP 4.7u 2.2u GPO1 GPO2 GPO3 GPO4 Startup Sequencer Decode Trim? PUMS LICELL BP VINUSB2 VUSB2 VUSB 100n 4.7u BP To Trimmed Circuits Trim-In-Package Control Logic 2.2u Coin Cell Battery SW2 Output BP BP VINCAMDRV OTG 5V To 1.8V Peripherals 2 x22u VVIDEODRV VVIDEO VSD VINUSB 1.5u SPI Control VCAM From AP O/P Drive SW3IN SW3OUT GNDSW3 SW3FB 4.7u Shift Register Reference Generation UVBUS VBUSEN SW2IN SW2OUT GNDSW2 SW2FB VVIDEO Connector Interface ID CHRGRAW REFCORE GNDCORE O/P Drive SW1 Output 2.2u To Enables & Control Registers VCORE VCOREDIG 2.2u To/From USB Cable MC13892 IC Shift Register CS CLK 2.2u SW1IN SW1OUT GNDSW1 SW1FB Package Pin Legend Output Pin AP CSPI O/P Drive DVS CONTROL To SPI 10uF SW4 To Memory User Off, Memory Hold PWGTDRV2 BP Voltage / Current Sensing & Translation ADIN7 SW4 PWGTDRV1 LICELL, UID, Die Temp, GPO4 GNDADC Processor Internal Memory User Off To 1.2V Peripherals Charger Interface and Control: 4 bit DAC, Clamp, Protection, Trickle Generation Battery Interface & Protection LEDAD LEDMD GNDCHRG CHRGSE1B CHRGLED CHRGRAW CHRGCTRL1 CHRGISNS CHRGCTRL2 BP BPSNS BATTFET BATT BATTISNS BP 10u Possible applications, may also be used for enables to adjunct supplies or modules as necessary Figure 14. 13892 Typical Application 13892 62 Analog Integrated Circuit Device Data Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. VK SUFFIX 139-PIN 98ASA10820D REVISION 0 13892 Analog Integrated Circuit Device Data Freescale Semiconductor 63 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. PACKAGING PACKAGE DIMENSIONS VK SUFFIX 139-PIN 98ASA10820D REVISION 0 13892 64 Analog Integrated Circuit Device Data Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. PACKAGING PACKAGE DIMENSIONS VL SUFFIX 186-PIN 98ASA10849D REVISION 0 13892 Analog Integrated Circuit Device Data Freescale Semiconductor 65 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. PACKAGING PACKAGE DIMENSIONS VL SUFFIX 186-PIN 98ASA10849D REVISION 0 13892 66 Analog Integrated Circuit Device Data Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages. How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. 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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2010. All rights reserved. MC13892 Rev. 7.0 4/2010